1fcf5ef2aSThomas Huth /* 2fcf5ef2aSThomas Huth * QEMU SuperH CPU 3fcf5ef2aSThomas Huth * 4fcf5ef2aSThomas Huth * Copyright (c) 2012 SUSE LINUX Products GmbH 5fcf5ef2aSThomas Huth * 6fcf5ef2aSThomas Huth * This library is free software; you can redistribute it and/or 7fcf5ef2aSThomas Huth * modify it under the terms of the GNU Lesser General Public 8fcf5ef2aSThomas Huth * License as published by the Free Software Foundation; either 9fcf5ef2aSThomas Huth * version 2.1 of the License, or (at your option) any later version. 10fcf5ef2aSThomas Huth * 11fcf5ef2aSThomas Huth * This library is distributed in the hope that it will be useful, 12fcf5ef2aSThomas Huth * but WITHOUT ANY WARRANTY; without even the implied warranty of 13fcf5ef2aSThomas Huth * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14fcf5ef2aSThomas Huth * Lesser General Public License for more details. 15fcf5ef2aSThomas Huth * 16fcf5ef2aSThomas Huth * You should have received a copy of the GNU Lesser General Public 17fcf5ef2aSThomas Huth * License along with this library; if not, see 18fcf5ef2aSThomas Huth * <http://www.gnu.org/licenses/lgpl-2.1.html> 19fcf5ef2aSThomas Huth */ 20fcf5ef2aSThomas Huth #ifndef QEMU_SUPERH_CPU_QOM_H 21fcf5ef2aSThomas Huth #define QEMU_SUPERH_CPU_QOM_H 22fcf5ef2aSThomas Huth 232e5b09fdSMarkus Armbruster #include "hw/core/cpu.h" 24db1015e9SEduardo Habkost #include "qom/object.h" 25fcf5ef2aSThomas Huth 26fcf5ef2aSThomas Huth #define TYPE_SUPERH_CPU "superh-cpu" 27fcf5ef2aSThomas Huth 28974e58d2SIgor Mammedov #define TYPE_SH7750R_CPU SUPERH_CPU_TYPE_NAME("sh7750r") 29974e58d2SIgor Mammedov #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r") 30974e58d2SIgor Mammedov #define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785") 31fcf5ef2aSThomas Huth 32*9295b1aaSPhilippe Mathieu-Daudé OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) 33fcf5ef2aSThomas Huth 34fcf5ef2aSThomas Huth /** 35fcf5ef2aSThomas Huth * SuperHCPUClass: 36fcf5ef2aSThomas Huth * @parent_realize: The parent class' realize handler. 37fcf5ef2aSThomas Huth * @parent_reset: The parent class' reset handler. 38fcf5ef2aSThomas Huth * @pvr: Processor Version Register 39fcf5ef2aSThomas Huth * @prr: Processor Revision Register 40fcf5ef2aSThomas Huth * @cvr: Cache Version Register 41fcf5ef2aSThomas Huth * 42fcf5ef2aSThomas Huth * A SuperH CPU model. 43fcf5ef2aSThomas Huth */ 44db1015e9SEduardo Habkost struct SuperHCPUClass { 45fcf5ef2aSThomas Huth /*< private >*/ 46fcf5ef2aSThomas Huth CPUClass parent_class; 47fcf5ef2aSThomas Huth /*< public >*/ 48fcf5ef2aSThomas Huth 49fcf5ef2aSThomas Huth DeviceRealize parent_realize; 50781c67caSPeter Maydell DeviceReset parent_reset; 51fcf5ef2aSThomas Huth 52fcf5ef2aSThomas Huth uint32_t pvr; 53fcf5ef2aSThomas Huth uint32_t prr; 54fcf5ef2aSThomas Huth uint32_t cvr; 55db1015e9SEduardo Habkost }; 56fcf5ef2aSThomas Huth 57fcf5ef2aSThomas Huth 58fcf5ef2aSThomas Huth #endif 59