1 /* 2 * S390x MMU related functions 3 * 4 * Copyright (c) 2011 Alexander Graf 5 * Copyright (c) 2015 Thomas Huth, IBM Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "qemu/error-report.h" 20 #include "exec/address-spaces.h" 21 #include "cpu.h" 22 #include "internal.h" 23 #include "kvm_s390x.h" 24 #include "sysemu/kvm.h" 25 #include "sysemu/tcg.h" 26 #include "exec/exec-all.h" 27 #include "trace.h" 28 #include "hw/s390x/storage-keys.h" 29 30 /* #define DEBUG_S390 */ 31 /* #define DEBUG_S390_PTE */ 32 /* #define DEBUG_S390_STDOUT */ 33 34 #ifdef DEBUG_S390 35 #ifdef DEBUG_S390_STDOUT 36 #define DPRINTF(fmt, ...) \ 37 do { fprintf(stderr, fmt, ## __VA_ARGS__); \ 38 if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0) 39 #else 40 #define DPRINTF(fmt, ...) \ 41 do { qemu_log(fmt, ## __VA_ARGS__); } while (0) 42 #endif 43 #else 44 #define DPRINTF(fmt, ...) \ 45 do { } while (0) 46 #endif 47 48 #ifdef DEBUG_S390_PTE 49 #define PTE_DPRINTF DPRINTF 50 #else 51 #define PTE_DPRINTF(fmt, ...) \ 52 do { } while (0) 53 #endif 54 55 /* Fetch/store bits in the translation exception code: */ 56 #define FS_READ 0x800 57 #define FS_WRITE 0x400 58 59 static void trigger_access_exception(CPUS390XState *env, uint32_t type, 60 uint32_t ilen, uint64_t tec) 61 { 62 S390CPU *cpu = env_archcpu(env); 63 64 if (kvm_enabled()) { 65 kvm_s390_access_exception(cpu, type, tec); 66 } else { 67 CPUState *cs = env_cpu(env); 68 if (type != PGM_ADDRESSING) { 69 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec); 70 } 71 trigger_pgm_exception(env, type, ilen); 72 } 73 } 74 75 static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr, 76 uint64_t asc, int rw, bool exc) 77 { 78 uint64_t tec; 79 80 tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | 4 | asc >> 46; 81 82 DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec); 83 84 if (!exc) { 85 return; 86 } 87 88 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, tec); 89 } 90 91 static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr, 92 uint32_t type, uint64_t asc, int rw, bool exc) 93 { 94 int ilen = ILEN_AUTO; 95 uint64_t tec; 96 97 tec = vaddr | (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ) | asc >> 46; 98 99 DPRINTF("%s: trans_exc_code=%016" PRIx64 "\n", __func__, tec); 100 101 if (!exc) { 102 return; 103 } 104 105 /* Code accesses have an undefined ilc. */ 106 if (rw == MMU_INST_FETCH) { 107 ilen = 2; 108 } 109 110 trigger_access_exception(env, type, ilen, tec); 111 } 112 113 /* check whether the address would be proteted by Low-Address Protection */ 114 static bool is_low_address(uint64_t addr) 115 { 116 return addr <= 511 || (addr >= 4096 && addr <= 4607); 117 } 118 119 /* check whether Low-Address Protection is enabled for mmu_translate() */ 120 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc) 121 { 122 if (!(env->cregs[0] & CR0_LOWPROT)) { 123 return false; 124 } 125 if (!(env->psw.mask & PSW_MASK_DAT)) { 126 return true; 127 } 128 129 /* Check the private-space control bit */ 130 switch (asc) { 131 case PSW_ASC_PRIMARY: 132 return !(env->cregs[1] & ASCE_PRIVATE_SPACE); 133 case PSW_ASC_SECONDARY: 134 return !(env->cregs[7] & ASCE_PRIVATE_SPACE); 135 case PSW_ASC_HOME: 136 return !(env->cregs[13] & ASCE_PRIVATE_SPACE); 137 default: 138 /* We don't support access register mode */ 139 error_report("unsupported addressing mode"); 140 exit(1); 141 } 142 } 143 144 /** 145 * Translate real address to absolute (= physical) 146 * address by taking care of the prefix mapping. 147 */ 148 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr) 149 { 150 if (raddr < 0x2000) { 151 return raddr + env->psa; /* Map the lowcore. */ 152 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) { 153 return raddr - env->psa; /* Map the 0 page. */ 154 } 155 return raddr; 156 } 157 158 /* Decode page table entry (normal 4KB page) */ 159 static int mmu_translate_pte(CPUS390XState *env, target_ulong vaddr, 160 uint64_t asc, uint64_t pt_entry, 161 target_ulong *raddr, int *flags, int rw, bool exc) 162 { 163 if (pt_entry & PAGE_INVALID) { 164 DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, pt_entry); 165 trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw, exc); 166 return -1; 167 } 168 if (pt_entry & PAGE_RES0) { 169 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); 170 return -1; 171 } 172 if (pt_entry & PAGE_RO) { 173 *flags &= ~PAGE_WRITE; 174 } 175 176 *raddr = pt_entry & ASCE_ORIGIN; 177 178 PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, pt_entry); 179 180 return 0; 181 } 182 183 /* Decode segment table entry */ 184 static int mmu_translate_segment(CPUS390XState *env, target_ulong vaddr, 185 uint64_t asc, uint64_t st_entry, 186 target_ulong *raddr, int *flags, int rw, 187 bool exc) 188 { 189 CPUState *cs = env_cpu(env); 190 uint64_t origin, offs, pt_entry; 191 192 if (st_entry & SEGMENT_ENTRY_RO) { 193 *flags &= ~PAGE_WRITE; 194 } 195 196 if ((st_entry & SEGMENT_ENTRY_FC) && (env->cregs[0] & CR0_EDAT)) { 197 /* Decode EDAT1 segment frame absolute address (1MB page) */ 198 *raddr = (st_entry & 0xfffffffffff00000ULL) | (vaddr & 0xfffff); 199 PTE_DPRINTF("%s: SEG=0x%" PRIx64 "\n", __func__, st_entry); 200 return 0; 201 } 202 203 /* Look up 4KB page entry */ 204 origin = st_entry & SEGMENT_ENTRY_ORIGIN; 205 offs = (vaddr & VADDR_PX) >> 9; 206 pt_entry = ldq_phys(cs->as, origin + offs); 207 PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", 208 __func__, origin, offs, pt_entry); 209 return mmu_translate_pte(env, vaddr, asc, pt_entry, raddr, flags, rw, exc); 210 } 211 212 /* Decode region table entries */ 213 static int mmu_translate_region(CPUS390XState *env, target_ulong vaddr, 214 uint64_t asc, uint64_t entry, int level, 215 target_ulong *raddr, int *flags, int rw, 216 bool exc) 217 { 218 CPUState *cs = env_cpu(env); 219 uint64_t origin, offs, new_entry; 220 const int pchks[4] = { 221 PGM_SEGMENT_TRANS, PGM_REG_THIRD_TRANS, 222 PGM_REG_SEC_TRANS, PGM_REG_FIRST_TRANS 223 }; 224 225 PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, entry); 226 227 origin = entry & REGION_ENTRY_ORIGIN; 228 offs = (vaddr >> (17 + 11 * level / 4)) & 0x3ff8; 229 230 new_entry = ldq_phys(cs->as, origin + offs); 231 PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n", 232 __func__, origin, offs, new_entry); 233 234 if ((new_entry & REGION_ENTRY_INV) != 0) { 235 DPRINTF("%s: invalid region\n", __func__); 236 trigger_page_fault(env, vaddr, pchks[level / 4], asc, rw, exc); 237 return -1; 238 } 239 240 if ((new_entry & REGION_ENTRY_TYPE_MASK) != level) { 241 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw, exc); 242 return -1; 243 } 244 245 if (level == ASCE_TYPE_SEGMENT) { 246 return mmu_translate_segment(env, vaddr, asc, new_entry, raddr, flags, 247 rw, exc); 248 } 249 250 /* Check region table offset and length */ 251 offs = (vaddr >> (28 + 11 * (level - 4) / 4)) & 3; 252 if (offs < ((new_entry & REGION_ENTRY_TF) >> 6) 253 || offs > (new_entry & REGION_ENTRY_LENGTH)) { 254 DPRINTF("%s: invalid offset or len (%lx)\n", __func__, new_entry); 255 trigger_page_fault(env, vaddr, pchks[level / 4 - 1], asc, rw, exc); 256 return -1; 257 } 258 259 if ((env->cregs[0] & CR0_EDAT) && (new_entry & REGION_ENTRY_RO)) { 260 *flags &= ~PAGE_WRITE; 261 } 262 263 /* yet another region */ 264 return mmu_translate_region(env, vaddr, asc, new_entry, level - 4, 265 raddr, flags, rw, exc); 266 } 267 268 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr, 269 uint64_t asc, uint64_t asce, target_ulong *raddr, 270 int *flags, int rw, bool exc) 271 { 272 int level; 273 int r; 274 275 if (asce & ASCE_REAL_SPACE) { 276 /* direct mapping */ 277 *raddr = vaddr; 278 return 0; 279 } 280 281 level = asce & ASCE_TYPE_MASK; 282 switch (level) { 283 case ASCE_TYPE_REGION1: 284 if ((vaddr >> 62) > (asce & ASCE_TABLE_LENGTH)) { 285 trigger_page_fault(env, vaddr, PGM_REG_FIRST_TRANS, asc, rw, exc); 286 return -1; 287 } 288 break; 289 case ASCE_TYPE_REGION2: 290 if (vaddr & 0xffe0000000000000ULL) { 291 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 292 " 0xffe0000000000000ULL\n", __func__, vaddr); 293 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); 294 return -1; 295 } 296 if ((vaddr >> 51 & 3) > (asce & ASCE_TABLE_LENGTH)) { 297 trigger_page_fault(env, vaddr, PGM_REG_SEC_TRANS, asc, rw, exc); 298 return -1; 299 } 300 break; 301 case ASCE_TYPE_REGION3: 302 if (vaddr & 0xfffffc0000000000ULL) { 303 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 304 " 0xfffffc0000000000ULL\n", __func__, vaddr); 305 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); 306 return -1; 307 } 308 if ((vaddr >> 40 & 3) > (asce & ASCE_TABLE_LENGTH)) { 309 trigger_page_fault(env, vaddr, PGM_REG_THIRD_TRANS, asc, rw, exc); 310 return -1; 311 } 312 break; 313 case ASCE_TYPE_SEGMENT: 314 if (vaddr & 0xffffffff80000000ULL) { 315 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64 316 " 0xffffffff80000000ULL\n", __func__, vaddr); 317 trigger_page_fault(env, vaddr, PGM_ASCE_TYPE, asc, rw, exc); 318 return -1; 319 } 320 if ((vaddr >> 29 & 3) > (asce & ASCE_TABLE_LENGTH)) { 321 trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw, exc); 322 return -1; 323 } 324 break; 325 } 326 327 r = mmu_translate_region(env, vaddr, asc, asce, level, raddr, flags, rw, 328 exc); 329 if (!r && rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE)) { 330 trigger_prot_fault(env, vaddr, asc, rw, exc); 331 return -1; 332 } 333 334 return r; 335 } 336 337 /** 338 * Translate a virtual (logical) address into a physical (absolute) address. 339 * @param vaddr the virtual address 340 * @param rw 0 = read, 1 = write, 2 = code fetch 341 * @param asc address space control (one of the PSW_ASC_* modes) 342 * @param raddr the translated address is stored to this pointer 343 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 344 * @param exc true = inject a program check if a fault occurred 345 * @return 0 if the translation was successful, -1 if a fault occurred 346 */ 347 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc, 348 target_ulong *raddr, int *flags, bool exc) 349 { 350 static S390SKeysState *ss; 351 static S390SKeysClass *skeyclass; 352 int r = -1; 353 uint8_t key; 354 355 if (unlikely(!ss)) { 356 ss = s390_get_skeys_device(); 357 skeyclass = S390_SKEYS_GET_CLASS(ss); 358 } 359 360 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 361 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) { 362 /* 363 * If any part of this page is currently protected, make sure the 364 * TLB entry will not be reused. 365 * 366 * As the protected range is always the first 512 bytes of the 367 * two first pages, we are able to catch all writes to these areas 368 * just by looking at the start address (triggering the tlb miss). 369 */ 370 *flags |= PAGE_WRITE_INV; 371 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) { 372 if (exc) { 373 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0); 374 } 375 return -EACCES; 376 } 377 } 378 379 vaddr &= TARGET_PAGE_MASK; 380 381 if (!(env->psw.mask & PSW_MASK_DAT)) { 382 *raddr = vaddr; 383 r = 0; 384 goto out; 385 } 386 387 switch (asc) { 388 case PSW_ASC_PRIMARY: 389 PTE_DPRINTF("%s: asc=primary\n", __func__); 390 r = mmu_translate_asce(env, vaddr, asc, env->cregs[1], raddr, flags, 391 rw, exc); 392 break; 393 case PSW_ASC_HOME: 394 PTE_DPRINTF("%s: asc=home\n", __func__); 395 r = mmu_translate_asce(env, vaddr, asc, env->cregs[13], raddr, flags, 396 rw, exc); 397 break; 398 case PSW_ASC_SECONDARY: 399 PTE_DPRINTF("%s: asc=secondary\n", __func__); 400 /* 401 * Instruction: Primary 402 * Data: Secondary 403 */ 404 if (rw == MMU_INST_FETCH) { 405 r = mmu_translate_asce(env, vaddr, PSW_ASC_PRIMARY, env->cregs[1], 406 raddr, flags, rw, exc); 407 *flags &= ~(PAGE_READ | PAGE_WRITE); 408 } else { 409 r = mmu_translate_asce(env, vaddr, PSW_ASC_SECONDARY, env->cregs[7], 410 raddr, flags, rw, exc); 411 *flags &= ~(PAGE_EXEC); 412 } 413 break; 414 case PSW_ASC_ACCREG: 415 default: 416 hw_error("guest switched to unknown asc mode\n"); 417 break; 418 } 419 420 out: 421 /* Convert real address -> absolute address */ 422 *raddr = mmu_real2abs(env, *raddr); 423 424 if (r == 0 && *raddr < ram_size) { 425 if (skeyclass->get_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { 426 trace_get_skeys_nonzero(r); 427 return 0; 428 } 429 430 if (*flags & PAGE_READ) { 431 key |= SK_R; 432 } 433 434 if (*flags & PAGE_WRITE) { 435 key |= SK_C; 436 } 437 438 if (skeyclass->set_skeys(ss, *raddr / TARGET_PAGE_SIZE, 1, &key)) { 439 trace_set_skeys_nonzero(r); 440 return 0; 441 } 442 } 443 444 return r; 445 } 446 447 /** 448 * translate_pages: Translate a set of consecutive logical page addresses 449 * to absolute addresses. This function is used for TCG and old KVM without 450 * the MEMOP interface. 451 */ 452 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages, 453 target_ulong *pages, bool is_write) 454 { 455 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC; 456 CPUS390XState *env = &cpu->env; 457 int ret, i, pflags; 458 459 for (i = 0; i < nr_pages; i++) { 460 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, true); 461 if (ret) { 462 return ret; 463 } 464 if (!address_space_access_valid(&address_space_memory, pages[i], 465 TARGET_PAGE_SIZE, is_write, 466 MEMTXATTRS_UNSPECIFIED)) { 467 trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0); 468 return -EFAULT; 469 } 470 addr += TARGET_PAGE_SIZE; 471 } 472 473 return 0; 474 } 475 476 /** 477 * s390_cpu_virt_mem_rw: 478 * @laddr: the logical start address 479 * @ar: the access register number 480 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying 481 * @len: length that should be transferred 482 * @is_write: true = write, false = read 483 * Returns: 0 on success, non-zero if an exception occurred 484 * 485 * Copy from/to guest memory using logical addresses. Note that we inject a 486 * program interrupt in case there is an error while accessing the memory. 487 * 488 * This function will always return (also for TCG), make sure to call 489 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop. 490 */ 491 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 492 int len, bool is_write) 493 { 494 int currlen, nr_pages, i; 495 target_ulong *pages; 496 int ret; 497 498 if (kvm_enabled()) { 499 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write); 500 if (ret >= 0) { 501 return ret; 502 } 503 } 504 505 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS) 506 + 1; 507 pages = g_malloc(nr_pages * sizeof(*pages)); 508 509 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write); 510 if (ret == 0 && hostbuf != NULL) { 511 /* Copy data by stepping through the area page by page */ 512 for (i = 0; i < nr_pages; i++) { 513 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE)); 514 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK), 515 hostbuf, currlen, is_write); 516 laddr += currlen; 517 hostbuf += currlen; 518 len -= currlen; 519 } 520 } 521 522 g_free(pages); 523 return ret; 524 } 525 526 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra) 527 { 528 /* KVM will handle the interrupt automatically, TCG has to exit the TB */ 529 #ifdef CONFIG_TCG 530 if (tcg_enabled()) { 531 cpu_loop_exit_restore(CPU(cpu), ra); 532 } 533 #endif 534 } 535 536 /** 537 * Translate a real address into a physical (absolute) address. 538 * @param raddr the real address 539 * @param rw 0 = read, 1 = write, 2 = code fetch 540 * @param addr the translated address is stored to this pointer 541 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer 542 * @return 0 if the translation was successful, < 0 if a fault occurred 543 */ 544 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw, 545 target_ulong *addr, int *flags) 546 { 547 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT; 548 549 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 550 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) { 551 /* see comment in mmu_translate() how this works */ 552 *flags |= PAGE_WRITE_INV; 553 if (is_low_address(raddr) && rw == MMU_DATA_STORE) { 554 trigger_access_exception(env, PGM_PROTECTION, ILEN_AUTO, 0); 555 return -EACCES; 556 } 557 } 558 559 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK); 560 561 /* TODO: storage key handling */ 562 return 0; 563 } 564