1 /* 2 * S/390 helpers 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * Copyright (c) 2011 Alexander Graf 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "internal.h" 25 #include "exec/gdbstub.h" 26 #include "qemu/timer.h" 27 #include "exec/exec-all.h" 28 #include "hw/s390x/ioinst.h" 29 #include "sysemu/hw_accel.h" 30 #ifndef CONFIG_USER_ONLY 31 #include "sysemu/sysemu.h" 32 #endif 33 34 #ifndef CONFIG_USER_ONLY 35 void s390x_tod_timer(void *opaque) 36 { 37 cpu_inject_clock_comparator((S390CPU *) opaque); 38 } 39 40 void s390x_cpu_timer(void *opaque) 41 { 42 cpu_inject_cpu_timer((S390CPU *) opaque); 43 } 44 #endif 45 46 #ifndef CONFIG_USER_ONLY 47 48 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) 49 { 50 S390CPU *cpu = S390_CPU(cs); 51 CPUS390XState *env = &cpu->env; 52 target_ulong raddr; 53 int prot; 54 uint64_t asc = env->psw.mask & PSW_MASK_ASC; 55 56 /* 31-Bit mode */ 57 if (!(env->psw.mask & PSW_MASK_64)) { 58 vaddr &= 0x7fffffff; 59 } 60 61 if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) { 62 return -1; 63 } 64 return raddr; 65 } 66 67 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr) 68 { 69 hwaddr phys_addr; 70 target_ulong page; 71 72 page = vaddr & TARGET_PAGE_MASK; 73 phys_addr = cpu_get_phys_page_debug(cs, page); 74 phys_addr += (vaddr & ~TARGET_PAGE_MASK); 75 76 return phys_addr; 77 } 78 79 static inline bool is_special_wait_psw(uint64_t psw_addr) 80 { 81 /* signal quiesce */ 82 return psw_addr == 0xfffUL; 83 } 84 85 void s390_handle_wait(S390CPU *cpu) 86 { 87 if (s390_cpu_halt(cpu) == 0) { 88 #ifndef CONFIG_USER_ONLY 89 if (is_special_wait_psw(cpu->env.psw.addr)) { 90 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 91 } else { 92 qemu_system_guest_panicked(NULL); 93 } 94 #endif 95 } 96 } 97 98 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) 99 { 100 uint64_t old_mask = env->psw.mask; 101 102 env->psw.addr = addr; 103 env->psw.mask = mask; 104 if (tcg_enabled()) { 105 env->cc_op = (mask >> 44) & 3; 106 } 107 108 if ((old_mask ^ mask) & PSW_MASK_PER) { 109 s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env))); 110 } 111 112 /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */ 113 if (tcg_enabled() && (mask & PSW_MASK_WAIT)) { 114 s390_handle_wait(s390_env_get_cpu(env)); 115 } 116 } 117 118 uint64_t get_psw_mask(CPUS390XState *env) 119 { 120 uint64_t r = env->psw.mask; 121 122 if (tcg_enabled()) { 123 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, 124 env->cc_vr); 125 126 r &= ~PSW_MASK_CC; 127 assert(!(env->cc_op & ~3)); 128 r |= (uint64_t)env->cc_op << 44; 129 } 130 131 return r; 132 } 133 134 LowCore *cpu_map_lowcore(CPUS390XState *env) 135 { 136 S390CPU *cpu = s390_env_get_cpu(env); 137 LowCore *lowcore; 138 hwaddr len = sizeof(LowCore); 139 140 lowcore = cpu_physical_memory_map(env->psa, &len, 1); 141 142 if (len < sizeof(LowCore)) { 143 cpu_abort(CPU(cpu), "Could not map lowcore\n"); 144 } 145 146 return lowcore; 147 } 148 149 void cpu_unmap_lowcore(LowCore *lowcore) 150 { 151 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); 152 } 153 154 void do_restart_interrupt(CPUS390XState *env) 155 { 156 uint64_t mask, addr; 157 LowCore *lowcore; 158 159 lowcore = cpu_map_lowcore(env); 160 161 lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env)); 162 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); 163 mask = be64_to_cpu(lowcore->restart_new_psw.mask); 164 addr = be64_to_cpu(lowcore->restart_new_psw.addr); 165 166 cpu_unmap_lowcore(lowcore); 167 env->pending_int &= ~INTERRUPT_RESTART; 168 169 load_psw(env, mask, addr); 170 } 171 172 void s390_cpu_recompute_watchpoints(CPUState *cs) 173 { 174 const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; 175 S390CPU *cpu = S390_CPU(cs); 176 CPUS390XState *env = &cpu->env; 177 178 /* We are called when the watchpoints have changed. First 179 remove them all. */ 180 cpu_watchpoint_remove_all(cs, BP_CPU); 181 182 /* Return if PER is not enabled */ 183 if (!(env->psw.mask & PSW_MASK_PER)) { 184 return; 185 } 186 187 /* Return if storage-alteration event is not enabled. */ 188 if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) { 189 return; 190 } 191 192 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) { 193 /* We can't create a watchoint spanning the whole memory range, so 194 split it in two parts. */ 195 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL); 196 cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL); 197 } else if (env->cregs[10] > env->cregs[11]) { 198 /* The address range loops, create two watchpoints. */ 199 cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10], 200 wp_flags, NULL); 201 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL); 202 203 } else { 204 /* Default case, create a single watchpoint. */ 205 cpu_watchpoint_insert(cs, env->cregs[10], 206 env->cregs[11] - env->cregs[10] + 1, 207 wp_flags, NULL); 208 } 209 } 210 211 struct sigp_save_area { 212 uint64_t fprs[16]; /* 0x0000 */ 213 uint64_t grs[16]; /* 0x0080 */ 214 PSW psw; /* 0x0100 */ 215 uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */ 216 uint32_t prefix; /* 0x0118 */ 217 uint32_t fpc; /* 0x011c */ 218 uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */ 219 uint32_t todpr; /* 0x0124 */ 220 uint64_t cputm; /* 0x0128 */ 221 uint64_t ckc; /* 0x0130 */ 222 uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */ 223 uint32_t ars[16]; /* 0x0140 */ 224 uint64_t crs[16]; /* 0x0384 */ 225 }; 226 QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512); 227 228 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) 229 { 230 static const uint8_t ar_id = 1; 231 struct sigp_save_area *sa; 232 hwaddr len = sizeof(*sa); 233 int i; 234 235 sa = cpu_physical_memory_map(addr, &len, 1); 236 if (!sa) { 237 return -EFAULT; 238 } 239 if (len != sizeof(*sa)) { 240 cpu_physical_memory_unmap(sa, len, 1, 0); 241 return -EFAULT; 242 } 243 244 if (store_arch) { 245 cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1); 246 } 247 for (i = 0; i < 16; ++i) { 248 sa->fprs[i] = cpu_to_be64(get_freg(&cpu->env, i)->ll); 249 } 250 for (i = 0; i < 16; ++i) { 251 sa->grs[i] = cpu_to_be64(cpu->env.regs[i]); 252 } 253 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr); 254 sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env)); 255 sa->prefix = cpu_to_be32(cpu->env.psa); 256 sa->fpc = cpu_to_be32(cpu->env.fpc); 257 sa->todpr = cpu_to_be32(cpu->env.todpr); 258 sa->cputm = cpu_to_be64(cpu->env.cputm); 259 sa->ckc = cpu_to_be64(cpu->env.ckc >> 8); 260 for (i = 0; i < 16; ++i) { 261 sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]); 262 } 263 for (i = 0; i < 16; ++i) { 264 sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]); 265 } 266 267 cpu_physical_memory_unmap(sa, len, 1, len); 268 269 return 0; 270 } 271 272 #define ADTL_GS_OFFSET 1024 /* offset of GS data in adtl save area */ 273 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */ 274 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) 275 { 276 hwaddr save = len; 277 void *mem; 278 279 mem = cpu_physical_memory_map(addr, &save, 1); 280 if (!mem) { 281 return -EFAULT; 282 } 283 if (save != len) { 284 cpu_physical_memory_unmap(mem, len, 1, 0); 285 return -EFAULT; 286 } 287 288 /* FIXME: as soon as TCG supports these features, convert cpu->be */ 289 if (s390_has_feat(S390_FEAT_VECTOR)) { 290 memcpy(mem, &cpu->env.vregs, 512); 291 } 292 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) { 293 memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32); 294 } 295 296 cpu_physical_memory_unmap(mem, len, 1, len); 297 298 return 0; 299 } 300 #endif /* CONFIG_USER_ONLY */ 301 302 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 303 int flags) 304 { 305 S390CPU *cpu = S390_CPU(cs); 306 CPUS390XState *env = &cpu->env; 307 int i; 308 309 if (env->cc_op > 3) { 310 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n", 311 env->psw.mask, env->psw.addr, cc_name(env->cc_op)); 312 } else { 313 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n", 314 env->psw.mask, env->psw.addr, env->cc_op); 315 } 316 317 for (i = 0; i < 16; i++) { 318 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]); 319 if ((i % 4) == 3) { 320 cpu_fprintf(f, "\n"); 321 } else { 322 cpu_fprintf(f, " "); 323 } 324 } 325 326 for (i = 0; i < 16; i++) { 327 cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll); 328 if ((i % 4) == 3) { 329 cpu_fprintf(f, "\n"); 330 } else { 331 cpu_fprintf(f, " "); 332 } 333 } 334 335 for (i = 0; i < 32; i++) { 336 cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i, 337 env->vregs[i][0].ll, env->vregs[i][1].ll); 338 cpu_fprintf(f, (i % 2) ? "\n" : " "); 339 } 340 341 #ifndef CONFIG_USER_ONLY 342 for (i = 0; i < 16; i++) { 343 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); 344 if ((i % 4) == 3) { 345 cpu_fprintf(f, "\n"); 346 } else { 347 cpu_fprintf(f, " "); 348 } 349 } 350 #endif 351 352 #ifdef DEBUG_INLINE_BRANCHES 353 for (i = 0; i < CC_OP_MAX; i++) { 354 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i), 355 inline_branch_miss[i], inline_branch_hit[i]); 356 } 357 #endif 358 359 cpu_fprintf(f, "\n"); 360 } 361 362 const char *cc_name(enum cc_op cc_op) 363 { 364 static const char * const cc_names[] = { 365 [CC_OP_CONST0] = "CC_OP_CONST0", 366 [CC_OP_CONST1] = "CC_OP_CONST1", 367 [CC_OP_CONST2] = "CC_OP_CONST2", 368 [CC_OP_CONST3] = "CC_OP_CONST3", 369 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", 370 [CC_OP_STATIC] = "CC_OP_STATIC", 371 [CC_OP_NZ] = "CC_OP_NZ", 372 [CC_OP_LTGT_32] = "CC_OP_LTGT_32", 373 [CC_OP_LTGT_64] = "CC_OP_LTGT_64", 374 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", 375 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", 376 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", 377 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", 378 [CC_OP_ADD_64] = "CC_OP_ADD_64", 379 [CC_OP_ADDU_64] = "CC_OP_ADDU_64", 380 [CC_OP_ADDC_64] = "CC_OP_ADDC_64", 381 [CC_OP_SUB_64] = "CC_OP_SUB_64", 382 [CC_OP_SUBU_64] = "CC_OP_SUBU_64", 383 [CC_OP_SUBB_64] = "CC_OP_SUBB_64", 384 [CC_OP_ABS_64] = "CC_OP_ABS_64", 385 [CC_OP_NABS_64] = "CC_OP_NABS_64", 386 [CC_OP_ADD_32] = "CC_OP_ADD_32", 387 [CC_OP_ADDU_32] = "CC_OP_ADDU_32", 388 [CC_OP_ADDC_32] = "CC_OP_ADDC_32", 389 [CC_OP_SUB_32] = "CC_OP_SUB_32", 390 [CC_OP_SUBU_32] = "CC_OP_SUBU_32", 391 [CC_OP_SUBB_32] = "CC_OP_SUBB_32", 392 [CC_OP_ABS_32] = "CC_OP_ABS_32", 393 [CC_OP_NABS_32] = "CC_OP_NABS_32", 394 [CC_OP_COMP_32] = "CC_OP_COMP_32", 395 [CC_OP_COMP_64] = "CC_OP_COMP_64", 396 [CC_OP_TM_32] = "CC_OP_TM_32", 397 [CC_OP_TM_64] = "CC_OP_TM_64", 398 [CC_OP_NZ_F32] = "CC_OP_NZ_F32", 399 [CC_OP_NZ_F64] = "CC_OP_NZ_F64", 400 [CC_OP_NZ_F128] = "CC_OP_NZ_F128", 401 [CC_OP_ICM] = "CC_OP_ICM", 402 [CC_OP_SLA_32] = "CC_OP_SLA_32", 403 [CC_OP_SLA_64] = "CC_OP_SLA_64", 404 [CC_OP_FLOGR] = "CC_OP_FLOGR", 405 }; 406 407 return cc_names[cc_op]; 408 } 409