1 /* 2 * S/390 helpers 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * Copyright (c) 2011 Alexander Graf 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "internal.h" 24 #include "exec/gdbstub.h" 25 #include "qemu/timer.h" 26 #include "qemu/qemu-print.h" 27 #include "hw/s390x/ioinst.h" 28 #include "hw/s390x/pv.h" 29 #include "sysemu/hw_accel.h" 30 #include "sysemu/runstate.h" 31 #ifndef CONFIG_USER_ONLY 32 #include "sysemu/tcg.h" 33 #endif 34 35 #ifndef CONFIG_USER_ONLY 36 void s390x_tod_timer(void *opaque) 37 { 38 cpu_inject_clock_comparator((S390CPU *) opaque); 39 } 40 41 void s390x_cpu_timer(void *opaque) 42 { 43 cpu_inject_cpu_timer((S390CPU *) opaque); 44 } 45 46 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) 47 { 48 S390CPU *cpu = S390_CPU(cs); 49 CPUS390XState *env = &cpu->env; 50 target_ulong raddr; 51 int prot; 52 uint64_t asc = env->psw.mask & PSW_MASK_ASC; 53 uint64_t tec; 54 55 /* 31-Bit mode */ 56 if (!(env->psw.mask & PSW_MASK_64)) { 57 vaddr &= 0x7fffffff; 58 } 59 60 /* We want to read the code (e.g., see what we are single-stepping).*/ 61 if (asc != PSW_ASC_HOME) { 62 asc = PSW_ASC_PRIMARY; 63 } 64 65 /* 66 * We want to read code even if IEP is active. Use MMU_DATA_LOAD instead 67 * of MMU_INST_FETCH. 68 */ 69 if (mmu_translate(env, vaddr, MMU_DATA_LOAD, asc, &raddr, &prot, &tec)) { 70 return -1; 71 } 72 return raddr; 73 } 74 75 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr) 76 { 77 hwaddr phys_addr; 78 target_ulong page; 79 80 page = vaddr & TARGET_PAGE_MASK; 81 phys_addr = cpu_get_phys_page_debug(cs, page); 82 phys_addr += (vaddr & ~TARGET_PAGE_MASK); 83 84 return phys_addr; 85 } 86 87 static inline bool is_special_wait_psw(uint64_t psw_addr) 88 { 89 /* signal quiesce */ 90 return (psw_addr & 0xfffUL) == 0xfffUL; 91 } 92 93 void s390_handle_wait(S390CPU *cpu) 94 { 95 CPUState *cs = CPU(cpu); 96 97 if (s390_cpu_halt(cpu) == 0) { 98 if (is_special_wait_psw(cpu->env.psw.addr)) { 99 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 100 } else { 101 cpu->env.crash_reason = S390_CRASH_REASON_DISABLED_WAIT; 102 qemu_system_guest_panicked(cpu_get_crash_info(cs)); 103 } 104 } 105 } 106 107 LowCore *cpu_map_lowcore(CPUS390XState *env) 108 { 109 LowCore *lowcore; 110 hwaddr len = sizeof(LowCore); 111 112 lowcore = cpu_physical_memory_map(env->psa, &len, true); 113 114 if (len < sizeof(LowCore)) { 115 cpu_abort(env_cpu(env), "Could not map lowcore\n"); 116 } 117 118 return lowcore; 119 } 120 121 void cpu_unmap_lowcore(LowCore *lowcore) 122 { 123 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); 124 } 125 126 void do_restart_interrupt(CPUS390XState *env) 127 { 128 uint64_t mask, addr; 129 LowCore *lowcore; 130 131 lowcore = cpu_map_lowcore(env); 132 133 lowcore->restart_old_psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(env)); 134 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); 135 mask = be64_to_cpu(lowcore->restart_new_psw.mask); 136 addr = be64_to_cpu(lowcore->restart_new_psw.addr); 137 138 cpu_unmap_lowcore(lowcore); 139 env->pending_int &= ~INTERRUPT_RESTART; 140 141 s390_cpu_set_psw(env, mask, addr); 142 } 143 144 void s390_cpu_recompute_watchpoints(CPUState *cs) 145 { 146 const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; 147 S390CPU *cpu = S390_CPU(cs); 148 CPUS390XState *env = &cpu->env; 149 150 /* We are called when the watchpoints have changed. First 151 remove them all. */ 152 cpu_watchpoint_remove_all(cs, BP_CPU); 153 154 /* Return if PER is not enabled */ 155 if (!(env->psw.mask & PSW_MASK_PER)) { 156 return; 157 } 158 159 /* Return if storage-alteration event is not enabled. */ 160 if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) { 161 return; 162 } 163 164 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) { 165 /* We can't create a watchoint spanning the whole memory range, so 166 split it in two parts. */ 167 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL); 168 cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL); 169 } else if (env->cregs[10] > env->cregs[11]) { 170 /* The address range loops, create two watchpoints. */ 171 cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10], 172 wp_flags, NULL); 173 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL); 174 175 } else { 176 /* Default case, create a single watchpoint. */ 177 cpu_watchpoint_insert(cs, env->cregs[10], 178 env->cregs[11] - env->cregs[10] + 1, 179 wp_flags, NULL); 180 } 181 } 182 183 typedef struct SigpSaveArea { 184 uint64_t fprs[16]; /* 0x0000 */ 185 uint64_t grs[16]; /* 0x0080 */ 186 PSW psw; /* 0x0100 */ 187 uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */ 188 uint32_t prefix; /* 0x0118 */ 189 uint32_t fpc; /* 0x011c */ 190 uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */ 191 uint32_t todpr; /* 0x0124 */ 192 uint64_t cputm; /* 0x0128 */ 193 uint64_t ckc; /* 0x0130 */ 194 uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */ 195 uint32_t ars[16]; /* 0x0140 */ 196 uint64_t crs[16]; /* 0x0384 */ 197 } SigpSaveArea; 198 QEMU_BUILD_BUG_ON(sizeof(SigpSaveArea) != 512); 199 200 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) 201 { 202 static const uint8_t ar_id = 1; 203 SigpSaveArea *sa; 204 hwaddr len = sizeof(*sa); 205 int i; 206 207 /* For PVMs storing will occur when this cpu enters SIE again */ 208 if (s390_is_pv()) { 209 return 0; 210 } 211 212 sa = cpu_physical_memory_map(addr, &len, true); 213 if (!sa) { 214 return -EFAULT; 215 } 216 if (len != sizeof(*sa)) { 217 cpu_physical_memory_unmap(sa, len, 1, 0); 218 return -EFAULT; 219 } 220 221 if (store_arch) { 222 cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1); 223 } 224 for (i = 0; i < 16; ++i) { 225 sa->fprs[i] = cpu_to_be64(*get_freg(&cpu->env, i)); 226 } 227 for (i = 0; i < 16; ++i) { 228 sa->grs[i] = cpu_to_be64(cpu->env.regs[i]); 229 } 230 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr); 231 sa->psw.mask = cpu_to_be64(s390_cpu_get_psw_mask(&cpu->env)); 232 sa->prefix = cpu_to_be32(cpu->env.psa); 233 sa->fpc = cpu_to_be32(cpu->env.fpc); 234 sa->todpr = cpu_to_be32(cpu->env.todpr); 235 sa->cputm = cpu_to_be64(cpu->env.cputm); 236 sa->ckc = cpu_to_be64(cpu->env.ckc >> 8); 237 for (i = 0; i < 16; ++i) { 238 sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]); 239 } 240 for (i = 0; i < 16; ++i) { 241 sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]); 242 } 243 244 cpu_physical_memory_unmap(sa, len, 1, len); 245 246 return 0; 247 } 248 249 typedef struct SigpAdtlSaveArea { 250 uint64_t vregs[32][2]; /* 0x0000 */ 251 uint8_t pad_0x0200[0x0400 - 0x0200]; /* 0x0200 */ 252 uint64_t gscb[4]; /* 0x0400 */ 253 uint8_t pad_0x0420[0x1000 - 0x0420]; /* 0x0420 */ 254 } SigpAdtlSaveArea; 255 QEMU_BUILD_BUG_ON(sizeof(SigpAdtlSaveArea) != 4096); 256 257 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */ 258 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) 259 { 260 SigpAdtlSaveArea *sa; 261 hwaddr save = len; 262 int i; 263 264 sa = cpu_physical_memory_map(addr, &save, true); 265 if (!sa) { 266 return -EFAULT; 267 } 268 if (save != len) { 269 cpu_physical_memory_unmap(sa, len, 1, 0); 270 return -EFAULT; 271 } 272 273 if (s390_has_feat(S390_FEAT_VECTOR)) { 274 for (i = 0; i < 32; i++) { 275 sa->vregs[i][0] = cpu_to_be64(cpu->env.vregs[i][0]); 276 sa->vregs[i][1] = cpu_to_be64(cpu->env.vregs[i][1]); 277 } 278 } 279 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) { 280 for (i = 0; i < 4; i++) { 281 sa->gscb[i] = cpu_to_be64(cpu->env.gscb[i]); 282 } 283 } 284 285 cpu_physical_memory_unmap(sa, len, 1, len); 286 return 0; 287 } 288 #else 289 /* For user-only, tcg is always enabled. */ 290 #define tcg_enabled() true 291 #endif /* CONFIG_USER_ONLY */ 292 293 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) 294 { 295 #ifndef CONFIG_USER_ONLY 296 uint64_t old_mask = env->psw.mask; 297 #endif 298 299 env->psw.addr = addr; 300 env->psw.mask = mask; 301 302 /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */ 303 if (!tcg_enabled()) { 304 return; 305 } 306 env->cc_op = (mask >> 44) & 3; 307 308 #ifndef CONFIG_USER_ONLY 309 if ((old_mask ^ mask) & PSW_MASK_PER) { 310 s390_cpu_recompute_watchpoints(env_cpu(env)); 311 } 312 313 if (mask & PSW_MASK_WAIT) { 314 s390_handle_wait(env_archcpu(env)); 315 } 316 #endif 317 } 318 319 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env) 320 { 321 uint64_t r = env->psw.mask; 322 323 if (tcg_enabled()) { 324 uint64_t cc = calc_cc(env, env->cc_op, env->cc_src, 325 env->cc_dst, env->cc_vr); 326 327 assert(cc <= 3); 328 r &= ~PSW_MASK_CC; 329 r |= cc << 44; 330 } 331 332 return r; 333 } 334 335 void s390_cpu_dump_state(CPUState *cs, FILE *f, int flags) 336 { 337 S390CPU *cpu = S390_CPU(cs); 338 CPUS390XState *env = &cpu->env; 339 int i; 340 341 qemu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64, 342 s390_cpu_get_psw_mask(env), env->psw.addr); 343 if (!tcg_enabled()) { 344 qemu_fprintf(f, "\n"); 345 } else if (env->cc_op > 3) { 346 qemu_fprintf(f, " cc %15s\n", cc_name(env->cc_op)); 347 } else { 348 qemu_fprintf(f, " cc %02x\n", env->cc_op); 349 } 350 351 for (i = 0; i < 16; i++) { 352 qemu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]); 353 if ((i % 4) == 3) { 354 qemu_fprintf(f, "\n"); 355 } else { 356 qemu_fprintf(f, " "); 357 } 358 } 359 360 if (flags & CPU_DUMP_FPU) { 361 if (s390_has_feat(S390_FEAT_VECTOR)) { 362 for (i = 0; i < 32; i++) { 363 qemu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c", 364 i, env->vregs[i][0], env->vregs[i][1], 365 i % 2 ? '\n' : ' '); 366 } 367 } else { 368 for (i = 0; i < 16; i++) { 369 qemu_fprintf(f, "F%02d=%016" PRIx64 "%c", 370 i, *get_freg(env, i), 371 (i % 4) == 3 ? '\n' : ' '); 372 } 373 } 374 } 375 376 #ifndef CONFIG_USER_ONLY 377 for (i = 0; i < 16; i++) { 378 qemu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); 379 if ((i % 4) == 3) { 380 qemu_fprintf(f, "\n"); 381 } else { 382 qemu_fprintf(f, " "); 383 } 384 } 385 #endif 386 387 #ifdef DEBUG_INLINE_BRANCHES 388 for (i = 0; i < CC_OP_MAX; i++) { 389 qemu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i), 390 inline_branch_miss[i], inline_branch_hit[i]); 391 } 392 #endif 393 394 qemu_fprintf(f, "\n"); 395 } 396 397 const char *cc_name(enum cc_op cc_op) 398 { 399 static const char * const cc_names[] = { 400 [CC_OP_CONST0] = "CC_OP_CONST0", 401 [CC_OP_CONST1] = "CC_OP_CONST1", 402 [CC_OP_CONST2] = "CC_OP_CONST2", 403 [CC_OP_CONST3] = "CC_OP_CONST3", 404 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", 405 [CC_OP_STATIC] = "CC_OP_STATIC", 406 [CC_OP_NZ] = "CC_OP_NZ", 407 [CC_OP_ADDU] = "CC_OP_ADDU", 408 [CC_OP_SUBU] = "CC_OP_SUBU", 409 [CC_OP_LTGT_32] = "CC_OP_LTGT_32", 410 [CC_OP_LTGT_64] = "CC_OP_LTGT_64", 411 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", 412 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", 413 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", 414 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", 415 [CC_OP_ADD_64] = "CC_OP_ADD_64", 416 [CC_OP_SUB_64] = "CC_OP_SUB_64", 417 [CC_OP_ABS_64] = "CC_OP_ABS_64", 418 [CC_OP_NABS_64] = "CC_OP_NABS_64", 419 [CC_OP_ADD_32] = "CC_OP_ADD_32", 420 [CC_OP_SUB_32] = "CC_OP_SUB_32", 421 [CC_OP_ABS_32] = "CC_OP_ABS_32", 422 [CC_OP_NABS_32] = "CC_OP_NABS_32", 423 [CC_OP_COMP_32] = "CC_OP_COMP_32", 424 [CC_OP_COMP_64] = "CC_OP_COMP_64", 425 [CC_OP_TM_32] = "CC_OP_TM_32", 426 [CC_OP_TM_64] = "CC_OP_TM_64", 427 [CC_OP_NZ_F32] = "CC_OP_NZ_F32", 428 [CC_OP_NZ_F64] = "CC_OP_NZ_F64", 429 [CC_OP_NZ_F128] = "CC_OP_NZ_F128", 430 [CC_OP_ICM] = "CC_OP_ICM", 431 [CC_OP_SLA_32] = "CC_OP_SLA_32", 432 [CC_OP_SLA_64] = "CC_OP_SLA_64", 433 [CC_OP_FLOGR] = "CC_OP_FLOGR", 434 [CC_OP_LCBB] = "CC_OP_LCBB", 435 [CC_OP_VC] = "CC_OP_VC", 436 [CC_OP_MULS_32] = "CC_OP_MULS_32", 437 [CC_OP_MULS_64] = "CC_OP_MULS_64", 438 }; 439 440 return cc_names[cc_op]; 441 } 442