1 /* 2 * S/390 helpers 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * Copyright (c) 2011 Alexander Graf 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "cpu.h" 24 #include "internal.h" 25 #include "exec/gdbstub.h" 26 #include "qemu/timer.h" 27 #include "exec/exec-all.h" 28 #include "hw/s390x/ioinst.h" 29 #include "sysemu/hw_accel.h" 30 #ifndef CONFIG_USER_ONLY 31 #include "sysemu/sysemu.h" 32 #endif 33 34 //#define DEBUG_S390 35 //#define DEBUG_S390_STDOUT 36 37 #ifdef DEBUG_S390 38 #ifdef DEBUG_S390_STDOUT 39 #define DPRINTF(fmt, ...) \ 40 do { fprintf(stderr, fmt, ## __VA_ARGS__); \ 41 if (qemu_log_separate()) qemu_log(fmt, ##__VA_ARGS__); } while (0) 42 #else 43 #define DPRINTF(fmt, ...) \ 44 do { qemu_log(fmt, ## __VA_ARGS__); } while (0) 45 #endif 46 #else 47 #define DPRINTF(fmt, ...) \ 48 do { } while (0) 49 #endif 50 51 52 #ifndef CONFIG_USER_ONLY 53 void s390x_tod_timer(void *opaque) 54 { 55 cpu_inject_clock_comparator((S390CPU *) opaque); 56 } 57 58 void s390x_cpu_timer(void *opaque) 59 { 60 cpu_inject_cpu_timer((S390CPU *) opaque); 61 } 62 #endif 63 64 #ifndef CONFIG_USER_ONLY 65 66 hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr) 67 { 68 S390CPU *cpu = S390_CPU(cs); 69 CPUS390XState *env = &cpu->env; 70 target_ulong raddr; 71 int prot; 72 uint64_t asc = env->psw.mask & PSW_MASK_ASC; 73 74 /* 31-Bit mode */ 75 if (!(env->psw.mask & PSW_MASK_64)) { 76 vaddr &= 0x7fffffff; 77 } 78 79 if (mmu_translate(env, vaddr, MMU_INST_FETCH, asc, &raddr, &prot, false)) { 80 return -1; 81 } 82 return raddr; 83 } 84 85 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cs, vaddr vaddr) 86 { 87 hwaddr phys_addr; 88 target_ulong page; 89 90 page = vaddr & TARGET_PAGE_MASK; 91 phys_addr = cpu_get_phys_page_debug(cs, page); 92 phys_addr += (vaddr & ~TARGET_PAGE_MASK); 93 94 return phys_addr; 95 } 96 97 static inline bool is_special_wait_psw(uint64_t psw_addr) 98 { 99 /* signal quiesce */ 100 return psw_addr == 0xfffUL; 101 } 102 103 void s390_handle_wait(S390CPU *cpu) 104 { 105 if (s390_cpu_halt(cpu) == 0) { 106 #ifndef CONFIG_USER_ONLY 107 if (is_special_wait_psw(cpu->env.psw.addr)) { 108 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 109 } else { 110 qemu_system_guest_panicked(NULL); 111 } 112 #endif 113 } 114 } 115 116 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr) 117 { 118 uint64_t old_mask = env->psw.mask; 119 120 env->psw.addr = addr; 121 env->psw.mask = mask; 122 if (tcg_enabled()) { 123 env->cc_op = (mask >> 44) & 3; 124 } 125 126 if ((old_mask ^ mask) & PSW_MASK_PER) { 127 s390_cpu_recompute_watchpoints(CPU(s390_env_get_cpu(env))); 128 } 129 130 /* KVM will handle all WAITs and trigger a WAIT exit on disabled_wait */ 131 if (tcg_enabled() && (mask & PSW_MASK_WAIT)) { 132 s390_handle_wait(s390_env_get_cpu(env)); 133 } 134 } 135 136 uint64_t get_psw_mask(CPUS390XState *env) 137 { 138 uint64_t r = env->psw.mask; 139 140 if (tcg_enabled()) { 141 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, 142 env->cc_vr); 143 144 r &= ~PSW_MASK_CC; 145 assert(!(env->cc_op & ~3)); 146 r |= (uint64_t)env->cc_op << 44; 147 } 148 149 return r; 150 } 151 152 LowCore *cpu_map_lowcore(CPUS390XState *env) 153 { 154 S390CPU *cpu = s390_env_get_cpu(env); 155 LowCore *lowcore; 156 hwaddr len = sizeof(LowCore); 157 158 lowcore = cpu_physical_memory_map(env->psa, &len, 1); 159 160 if (len < sizeof(LowCore)) { 161 cpu_abort(CPU(cpu), "Could not map lowcore\n"); 162 } 163 164 return lowcore; 165 } 166 167 void cpu_unmap_lowcore(LowCore *lowcore) 168 { 169 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore)); 170 } 171 172 void do_restart_interrupt(CPUS390XState *env) 173 { 174 uint64_t mask, addr; 175 LowCore *lowcore; 176 177 lowcore = cpu_map_lowcore(env); 178 179 lowcore->restart_old_psw.mask = cpu_to_be64(get_psw_mask(env)); 180 lowcore->restart_old_psw.addr = cpu_to_be64(env->psw.addr); 181 mask = be64_to_cpu(lowcore->restart_new_psw.mask); 182 addr = be64_to_cpu(lowcore->restart_new_psw.addr); 183 184 cpu_unmap_lowcore(lowcore); 185 env->pending_int &= ~INTERRUPT_RESTART; 186 187 load_psw(env, mask, addr); 188 } 189 190 void s390_cpu_recompute_watchpoints(CPUState *cs) 191 { 192 const int wp_flags = BP_CPU | BP_MEM_WRITE | BP_STOP_BEFORE_ACCESS; 193 S390CPU *cpu = S390_CPU(cs); 194 CPUS390XState *env = &cpu->env; 195 196 /* We are called when the watchpoints have changed. First 197 remove them all. */ 198 cpu_watchpoint_remove_all(cs, BP_CPU); 199 200 /* Return if PER is not enabled */ 201 if (!(env->psw.mask & PSW_MASK_PER)) { 202 return; 203 } 204 205 /* Return if storage-alteration event is not enabled. */ 206 if (!(env->cregs[9] & PER_CR9_EVENT_STORE)) { 207 return; 208 } 209 210 if (env->cregs[10] == 0 && env->cregs[11] == -1LL) { 211 /* We can't create a watchoint spanning the whole memory range, so 212 split it in two parts. */ 213 cpu_watchpoint_insert(cs, 0, 1ULL << 63, wp_flags, NULL); 214 cpu_watchpoint_insert(cs, 1ULL << 63, 1ULL << 63, wp_flags, NULL); 215 } else if (env->cregs[10] > env->cregs[11]) { 216 /* The address range loops, create two watchpoints. */ 217 cpu_watchpoint_insert(cs, env->cregs[10], -env->cregs[10], 218 wp_flags, NULL); 219 cpu_watchpoint_insert(cs, 0, env->cregs[11] + 1, wp_flags, NULL); 220 221 } else { 222 /* Default case, create a single watchpoint. */ 223 cpu_watchpoint_insert(cs, env->cregs[10], 224 env->cregs[11] - env->cregs[10] + 1, 225 wp_flags, NULL); 226 } 227 } 228 229 struct sigp_save_area { 230 uint64_t fprs[16]; /* 0x0000 */ 231 uint64_t grs[16]; /* 0x0080 */ 232 PSW psw; /* 0x0100 */ 233 uint8_t pad_0x0110[0x0118 - 0x0110]; /* 0x0110 */ 234 uint32_t prefix; /* 0x0118 */ 235 uint32_t fpc; /* 0x011c */ 236 uint8_t pad_0x0120[0x0124 - 0x0120]; /* 0x0120 */ 237 uint32_t todpr; /* 0x0124 */ 238 uint64_t cputm; /* 0x0128 */ 239 uint64_t ckc; /* 0x0130 */ 240 uint8_t pad_0x0138[0x0140 - 0x0138]; /* 0x0138 */ 241 uint32_t ars[16]; /* 0x0140 */ 242 uint64_t crs[16]; /* 0x0384 */ 243 }; 244 QEMU_BUILD_BUG_ON(sizeof(struct sigp_save_area) != 512); 245 246 int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch) 247 { 248 static const uint8_t ar_id = 1; 249 struct sigp_save_area *sa; 250 hwaddr len = sizeof(*sa); 251 int i; 252 253 sa = cpu_physical_memory_map(addr, &len, 1); 254 if (!sa) { 255 return -EFAULT; 256 } 257 if (len != sizeof(*sa)) { 258 cpu_physical_memory_unmap(sa, len, 1, 0); 259 return -EFAULT; 260 } 261 262 if (store_arch) { 263 cpu_physical_memory_write(offsetof(LowCore, ar_access_id), &ar_id, 1); 264 } 265 for (i = 0; i < 16; ++i) { 266 sa->fprs[i] = cpu_to_be64(get_freg(&cpu->env, i)->ll); 267 } 268 for (i = 0; i < 16; ++i) { 269 sa->grs[i] = cpu_to_be64(cpu->env.regs[i]); 270 } 271 sa->psw.addr = cpu_to_be64(cpu->env.psw.addr); 272 sa->psw.mask = cpu_to_be64(get_psw_mask(&cpu->env)); 273 sa->prefix = cpu_to_be32(cpu->env.psa); 274 sa->fpc = cpu_to_be32(cpu->env.fpc); 275 sa->todpr = cpu_to_be32(cpu->env.todpr); 276 sa->cputm = cpu_to_be64(cpu->env.cputm); 277 sa->ckc = cpu_to_be64(cpu->env.ckc >> 8); 278 for (i = 0; i < 16; ++i) { 279 sa->ars[i] = cpu_to_be32(cpu->env.aregs[i]); 280 } 281 for (i = 0; i < 16; ++i) { 282 sa->crs[i] = cpu_to_be64(cpu->env.cregs[i]); 283 } 284 285 cpu_physical_memory_unmap(sa, len, 1, len); 286 287 return 0; 288 } 289 290 #define ADTL_GS_OFFSET 1024 /* offset of GS data in adtl save area */ 291 #define ADTL_GS_MIN_SIZE 2048 /* minimal size of adtl save area for GS */ 292 int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len) 293 { 294 hwaddr save = len; 295 void *mem; 296 297 mem = cpu_physical_memory_map(addr, &save, 1); 298 if (!mem) { 299 return -EFAULT; 300 } 301 if (save != len) { 302 cpu_physical_memory_unmap(mem, len, 1, 0); 303 return -EFAULT; 304 } 305 306 /* FIXME: as soon as TCG supports these features, convert cpu->be */ 307 if (s390_has_feat(S390_FEAT_VECTOR)) { 308 memcpy(mem, &cpu->env.vregs, 512); 309 } 310 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE) && len >= ADTL_GS_MIN_SIZE) { 311 memcpy(mem + ADTL_GS_OFFSET, &cpu->env.gscb, 32); 312 } 313 314 cpu_physical_memory_unmap(mem, len, 1, len); 315 316 return 0; 317 } 318 #endif /* CONFIG_USER_ONLY */ 319 320 void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 321 int flags) 322 { 323 S390CPU *cpu = S390_CPU(cs); 324 CPUS390XState *env = &cpu->env; 325 int i; 326 327 if (env->cc_op > 3) { 328 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %15s\n", 329 env->psw.mask, env->psw.addr, cc_name(env->cc_op)); 330 } else { 331 cpu_fprintf(f, "PSW=mask %016" PRIx64 " addr %016" PRIx64 " cc %02x\n", 332 env->psw.mask, env->psw.addr, env->cc_op); 333 } 334 335 for (i = 0; i < 16; i++) { 336 cpu_fprintf(f, "R%02d=%016" PRIx64, i, env->regs[i]); 337 if ((i % 4) == 3) { 338 cpu_fprintf(f, "\n"); 339 } else { 340 cpu_fprintf(f, " "); 341 } 342 } 343 344 for (i = 0; i < 16; i++) { 345 cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll); 346 if ((i % 4) == 3) { 347 cpu_fprintf(f, "\n"); 348 } else { 349 cpu_fprintf(f, " "); 350 } 351 } 352 353 for (i = 0; i < 32; i++) { 354 cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i, 355 env->vregs[i][0].ll, env->vregs[i][1].ll); 356 cpu_fprintf(f, (i % 2) ? "\n" : " "); 357 } 358 359 #ifndef CONFIG_USER_ONLY 360 for (i = 0; i < 16; i++) { 361 cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); 362 if ((i % 4) == 3) { 363 cpu_fprintf(f, "\n"); 364 } else { 365 cpu_fprintf(f, " "); 366 } 367 } 368 #endif 369 370 #ifdef DEBUG_INLINE_BRANCHES 371 for (i = 0; i < CC_OP_MAX; i++) { 372 cpu_fprintf(f, " %15s = %10ld\t%10ld\n", cc_name(i), 373 inline_branch_miss[i], inline_branch_hit[i]); 374 } 375 #endif 376 377 cpu_fprintf(f, "\n"); 378 } 379 380 const char *cc_name(enum cc_op cc_op) 381 { 382 static const char * const cc_names[] = { 383 [CC_OP_CONST0] = "CC_OP_CONST0", 384 [CC_OP_CONST1] = "CC_OP_CONST1", 385 [CC_OP_CONST2] = "CC_OP_CONST2", 386 [CC_OP_CONST3] = "CC_OP_CONST3", 387 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC", 388 [CC_OP_STATIC] = "CC_OP_STATIC", 389 [CC_OP_NZ] = "CC_OP_NZ", 390 [CC_OP_LTGT_32] = "CC_OP_LTGT_32", 391 [CC_OP_LTGT_64] = "CC_OP_LTGT_64", 392 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32", 393 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64", 394 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32", 395 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64", 396 [CC_OP_ADD_64] = "CC_OP_ADD_64", 397 [CC_OP_ADDU_64] = "CC_OP_ADDU_64", 398 [CC_OP_ADDC_64] = "CC_OP_ADDC_64", 399 [CC_OP_SUB_64] = "CC_OP_SUB_64", 400 [CC_OP_SUBU_64] = "CC_OP_SUBU_64", 401 [CC_OP_SUBB_64] = "CC_OP_SUBB_64", 402 [CC_OP_ABS_64] = "CC_OP_ABS_64", 403 [CC_OP_NABS_64] = "CC_OP_NABS_64", 404 [CC_OP_ADD_32] = "CC_OP_ADD_32", 405 [CC_OP_ADDU_32] = "CC_OP_ADDU_32", 406 [CC_OP_ADDC_32] = "CC_OP_ADDC_32", 407 [CC_OP_SUB_32] = "CC_OP_SUB_32", 408 [CC_OP_SUBU_32] = "CC_OP_SUBU_32", 409 [CC_OP_SUBB_32] = "CC_OP_SUBB_32", 410 [CC_OP_ABS_32] = "CC_OP_ABS_32", 411 [CC_OP_NABS_32] = "CC_OP_NABS_32", 412 [CC_OP_COMP_32] = "CC_OP_COMP_32", 413 [CC_OP_COMP_64] = "CC_OP_COMP_64", 414 [CC_OP_TM_32] = "CC_OP_TM_32", 415 [CC_OP_TM_64] = "CC_OP_TM_64", 416 [CC_OP_NZ_F32] = "CC_OP_NZ_F32", 417 [CC_OP_NZ_F64] = "CC_OP_NZ_F64", 418 [CC_OP_NZ_F128] = "CC_OP_NZ_F128", 419 [CC_OP_ICM] = "CC_OP_ICM", 420 [CC_OP_SLA_32] = "CC_OP_SLA_32", 421 [CC_OP_SLA_64] = "CC_OP_SLA_64", 422 [CC_OP_FLOGR] = "CC_OP_FLOGR", 423 }; 424 425 return cc_names[cc_op]; 426 } 427