1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 #include "qemu/cpu-float.h" 32 #include "qapi/qapi-types-machine-common.h" 33 34 #define ELF_MACHINE_UNAME "S390X" 35 36 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 37 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 38 39 #define TARGET_HAS_PRECISE_SMC 40 41 #define TARGET_INSN_START_EXTRA_WORDS 2 42 43 #define MMU_USER_IDX 0 44 45 #define S390_MAX_CPUS 248 46 47 #ifndef CONFIG_KVM 48 #define S390_ADAPTER_SUPPRESSIBLE 0x01 49 #else 50 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE 51 #endif 52 53 typedef struct PSW { 54 uint64_t mask; 55 uint64_t addr; 56 } PSW; 57 58 typedef struct CPUArchState { 59 uint64_t regs[16]; /* GP registers */ 60 /* 61 * The floating point registers are part of the vector registers. 62 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 63 */ 64 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 65 uint32_t aregs[16]; /* access registers */ 66 uint64_t gscb[4]; /* guarded storage control */ 67 uint64_t etoken; /* etoken */ 68 uint64_t etoken_extension; /* etoken extension */ 69 70 uint64_t diag318_info; 71 72 /* Fields up to this point are not cleared by initial CPU reset */ 73 struct {} start_initial_reset_fields; 74 75 uint32_t fpc; /* floating-point control register */ 76 uint32_t cc_op; 77 bool bpbc; /* branch prediction blocking */ 78 79 float_status fpu_status; /* passed to softfloat lib */ 80 81 PSW psw; 82 83 S390CrashReason crash_reason; 84 85 uint64_t cc_src; 86 uint64_t cc_dst; 87 uint64_t cc_vr; 88 89 uint64_t ex_value; 90 uint64_t ex_target; 91 92 uint64_t __excp_addr; 93 uint64_t psa; 94 95 uint32_t int_pgm_code; 96 uint32_t int_pgm_ilen; 97 98 uint32_t int_svc_code; 99 uint32_t int_svc_ilen; 100 101 uint64_t per_address; 102 uint16_t per_perc_atmid; 103 104 uint64_t cregs[16]; /* control registers */ 105 106 uint64_t ckc; 107 uint64_t cputm; 108 uint32_t todpr; 109 110 uint64_t pfault_token; 111 uint64_t pfault_compare; 112 uint64_t pfault_select; 113 114 uint64_t gbea; 115 uint64_t pp; 116 117 /* Fields up to this point are not cleared by normal CPU reset */ 118 struct {} start_normal_reset_fields; 119 uint8_t riccb[64]; /* runtime instrumentation control */ 120 121 int pending_int; 122 uint16_t external_call_addr; 123 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 124 125 #if !defined(CONFIG_USER_ONLY) 126 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 127 int tlb_fill_exc; /* exception number seen during tlb_fill */ 128 #endif 129 130 /* Fields up to this point are cleared by a CPU reset */ 131 struct {} end_reset_fields; 132 133 #if !defined(CONFIG_USER_ONLY) 134 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 135 int32_t socket_id; 136 int32_t book_id; 137 int32_t drawer_id; 138 bool dedicated; 139 CpuS390Entitlement entitlement; /* Used only for vertical polarization */ 140 uint64_t cpuid; 141 #endif 142 143 QEMUTimer *tod_timer; 144 145 QEMUTimer *cpu_timer; 146 147 /* 148 * The cpu state represents the logical state of a cpu. In contrast to other 149 * architectures, there is a difference between a halt and a stop on s390. 150 * If all cpus are either stopped (including check stop) or in the disabled 151 * wait state, the vm can be shut down. 152 * The acceptable cpu_state values are defined in the CpuInfoS390State 153 * enum. 154 */ 155 uint8_t cpu_state; 156 157 /* currently processed sigp order */ 158 uint8_t sigp_order; 159 160 } CPUS390XState; 161 162 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 163 { 164 return &cs->vregs[nr][0]; 165 } 166 167 /** 168 * S390CPU: 169 * @env: #CPUS390XState. 170 * 171 * An S/390 CPU. 172 */ 173 struct ArchCPU { 174 CPUState parent_obj; 175 176 CPUS390XState env; 177 S390CPUModel *model; 178 /* needed for live migration */ 179 void *irqstate; 180 uint32_t irqstate_saved_size; 181 }; 182 183 typedef enum cpu_reset_type { 184 S390_CPU_RESET_NORMAL, 185 S390_CPU_RESET_INITIAL, 186 S390_CPU_RESET_CLEAR, 187 } cpu_reset_type; 188 189 /** 190 * S390CPUClass: 191 * @parent_realize: The parent class' realize handler. 192 * @parent_reset: The parent class' reset handler. 193 * @load_normal: Performs a load normal. 194 * @cpu_reset: Performs a CPU reset. 195 * @initial_cpu_reset: Performs an initial CPU reset. 196 * 197 * An S/390 CPU model. 198 */ 199 struct S390CPUClass { 200 CPUClass parent_class; 201 202 const S390CPUDef *cpu_def; 203 bool kvm_required; 204 bool is_static; 205 bool is_migration_safe; 206 const char *desc; 207 208 DeviceRealize parent_realize; 209 DeviceReset parent_reset; 210 void (*load_normal)(CPUState *cpu); 211 void (*reset)(CPUState *cpu, cpu_reset_type type); 212 }; 213 214 #ifndef CONFIG_USER_ONLY 215 extern const VMStateDescription vmstate_s390_cpu; 216 #endif 217 218 /* distinguish between 24 bit and 31 bit addressing */ 219 #define HIGH_ORDER_BIT 0x80000000 220 221 /* Interrupt Codes */ 222 /* Program Interrupts */ 223 #define PGM_OPERATION 0x0001 224 #define PGM_PRIVILEGED 0x0002 225 #define PGM_EXECUTE 0x0003 226 #define PGM_PROTECTION 0x0004 227 #define PGM_ADDRESSING 0x0005 228 #define PGM_SPECIFICATION 0x0006 229 #define PGM_DATA 0x0007 230 #define PGM_FIXPT_OVERFLOW 0x0008 231 #define PGM_FIXPT_DIVIDE 0x0009 232 #define PGM_DEC_OVERFLOW 0x000a 233 #define PGM_DEC_DIVIDE 0x000b 234 #define PGM_HFP_EXP_OVERFLOW 0x000c 235 #define PGM_HFP_EXP_UNDERFLOW 0x000d 236 #define PGM_HFP_SIGNIFICANCE 0x000e 237 #define PGM_HFP_DIVIDE 0x000f 238 #define PGM_SEGMENT_TRANS 0x0010 239 #define PGM_PAGE_TRANS 0x0011 240 #define PGM_TRANS_SPEC 0x0012 241 #define PGM_SPECIAL_OP 0x0013 242 #define PGM_OPERAND 0x0015 243 #define PGM_TRACE_TABLE 0x0016 244 #define PGM_VECTOR_PROCESSING 0x001b 245 #define PGM_SPACE_SWITCH 0x001c 246 #define PGM_HFP_SQRT 0x001d 247 #define PGM_PC_TRANS_SPEC 0x001f 248 #define PGM_AFX_TRANS 0x0020 249 #define PGM_ASX_TRANS 0x0021 250 #define PGM_LX_TRANS 0x0022 251 #define PGM_EX_TRANS 0x0023 252 #define PGM_PRIM_AUTH 0x0024 253 #define PGM_SEC_AUTH 0x0025 254 #define PGM_ALET_SPEC 0x0028 255 #define PGM_ALEN_SPEC 0x0029 256 #define PGM_ALE_SEQ 0x002a 257 #define PGM_ASTE_VALID 0x002b 258 #define PGM_ASTE_SEQ 0x002c 259 #define PGM_EXT_AUTH 0x002d 260 #define PGM_STACK_FULL 0x0030 261 #define PGM_STACK_EMPTY 0x0031 262 #define PGM_STACK_SPEC 0x0032 263 #define PGM_STACK_TYPE 0x0033 264 #define PGM_STACK_OP 0x0034 265 #define PGM_ASCE_TYPE 0x0038 266 #define PGM_REG_FIRST_TRANS 0x0039 267 #define PGM_REG_SEC_TRANS 0x003a 268 #define PGM_REG_THIRD_TRANS 0x003b 269 #define PGM_MONITOR 0x0040 270 #define PGM_PER 0x0080 271 #define PGM_CRYPTO 0x0119 272 273 /* External Interrupts */ 274 #define EXT_INTERRUPT_KEY 0x0040 275 #define EXT_CLOCK_COMP 0x1004 276 #define EXT_CPU_TIMER 0x1005 277 #define EXT_MALFUNCTION 0x1200 278 #define EXT_EMERGENCY 0x1201 279 #define EXT_EXTERNAL_CALL 0x1202 280 #define EXT_ETR 0x1406 281 #define EXT_SERVICE 0x2401 282 #define EXT_VIRTIO 0x2603 283 284 /* PSW defines */ 285 #undef PSW_MASK_PER 286 #undef PSW_MASK_UNUSED_2 287 #undef PSW_MASK_UNUSED_3 288 #undef PSW_MASK_DAT 289 #undef PSW_MASK_IO 290 #undef PSW_MASK_EXT 291 #undef PSW_MASK_KEY 292 #undef PSW_SHIFT_KEY 293 #undef PSW_MASK_MCHECK 294 #undef PSW_MASK_WAIT 295 #undef PSW_MASK_PSTATE 296 #undef PSW_MASK_ASC 297 #undef PSW_SHIFT_ASC 298 #undef PSW_MASK_CC 299 #undef PSW_MASK_PM 300 #undef PSW_MASK_RI 301 #undef PSW_SHIFT_MASK_PM 302 #undef PSW_MASK_64 303 #undef PSW_MASK_32 304 #undef PSW_MASK_ESA_ADDR 305 306 #define PSW_MASK_PER 0x4000000000000000ULL 307 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 308 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 309 #define PSW_MASK_DAT 0x0400000000000000ULL 310 #define PSW_MASK_IO 0x0200000000000000ULL 311 #define PSW_MASK_EXT 0x0100000000000000ULL 312 #define PSW_MASK_KEY 0x00F0000000000000ULL 313 #define PSW_SHIFT_KEY 52 314 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 315 #define PSW_MASK_MCHECK 0x0004000000000000ULL 316 #define PSW_MASK_WAIT 0x0002000000000000ULL 317 #define PSW_MASK_PSTATE 0x0001000000000000ULL 318 #define PSW_MASK_ASC 0x0000C00000000000ULL 319 #define PSW_SHIFT_ASC 46 320 #define PSW_MASK_CC 0x0000300000000000ULL 321 #define PSW_MASK_PM 0x00000F0000000000ULL 322 #define PSW_SHIFT_MASK_PM 40 323 #define PSW_MASK_RI 0x0000008000000000ULL 324 #define PSW_MASK_64 0x0000000100000000ULL 325 #define PSW_MASK_32 0x0000000080000000ULL 326 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 327 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 328 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL 329 330 #undef PSW_ASC_PRIMARY 331 #undef PSW_ASC_ACCREG 332 #undef PSW_ASC_SECONDARY 333 #undef PSW_ASC_HOME 334 335 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 336 #define PSW_ASC_ACCREG 0x0000400000000000ULL 337 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 338 #define PSW_ASC_HOME 0x0000C00000000000ULL 339 340 /* the address space values shifted */ 341 #define AS_PRIMARY 0 342 #define AS_ACCREG 1 343 #define AS_SECONDARY 2 344 #define AS_HOME 3 345 346 /* tb flags */ 347 348 #define FLAG_MASK_PSW_SHIFT 31 349 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 350 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 351 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 352 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 353 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 354 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 355 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 356 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 357 358 /* we'll use some unused PSW positions to store CR flags in tb flags */ 359 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 360 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 361 362 /* Control register 0 bits */ 363 #define CR0_LOWPROT 0x0000000010000000ULL 364 #define CR0_SECONDARY 0x0000000004000000ULL 365 #define CR0_EDAT 0x0000000000800000ULL 366 #define CR0_AFP 0x0000000000040000ULL 367 #define CR0_VECTOR 0x0000000000020000ULL 368 #define CR0_IEP 0x0000000000100000ULL 369 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 370 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 371 #define CR0_CKC_SC 0x0000000000000800ULL 372 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 373 #define CR0_SERVICE_SC 0x0000000000000200ULL 374 375 /* Control register 14 bits */ 376 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 377 378 /* MMU */ 379 #define MMU_PRIMARY_IDX 0 380 #define MMU_SECONDARY_IDX 1 381 #define MMU_HOME_IDX 2 382 #define MMU_REAL_IDX 3 383 384 static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) 385 { 386 #ifdef CONFIG_USER_ONLY 387 return MMU_USER_IDX; 388 #else 389 if (!(env->psw.mask & PSW_MASK_DAT)) { 390 return MMU_REAL_IDX; 391 } 392 393 if (ifetch) { 394 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 395 return MMU_HOME_IDX; 396 } 397 return MMU_PRIMARY_IDX; 398 } 399 400 switch (env->psw.mask & PSW_MASK_ASC) { 401 case PSW_ASC_PRIMARY: 402 return MMU_PRIMARY_IDX; 403 case PSW_ASC_SECONDARY: 404 return MMU_SECONDARY_IDX; 405 case PSW_ASC_HOME: 406 return MMU_HOME_IDX; 407 case PSW_ASC_ACCREG: 408 /* Fallthrough: access register mode is not yet supported */ 409 default: 410 abort(); 411 } 412 #endif 413 } 414 415 #ifdef CONFIG_TCG 416 417 #include "tcg/tcg_s390x.h" 418 419 static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, 420 uint64_t *cs_base, uint32_t *flags) 421 { 422 if (env->psw.addr & 1) { 423 /* 424 * Instructions must be at even addresses. 425 * This needs to be checked before address translation. 426 */ 427 env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ 428 tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); 429 } 430 *pc = env->psw.addr; 431 *cs_base = env->ex_value; 432 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 433 if (env->cregs[0] & CR0_AFP) { 434 *flags |= FLAG_MASK_AFP; 435 } 436 if (env->cregs[0] & CR0_VECTOR) { 437 *flags |= FLAG_MASK_VECTOR; 438 } 439 } 440 441 #endif /* CONFIG_TCG */ 442 443 /* PER bits from control register 9 */ 444 #define PER_CR9_EVENT_BRANCH 0x80000000 445 #define PER_CR9_EVENT_IFETCH 0x40000000 446 #define PER_CR9_EVENT_STORE 0x20000000 447 #define PER_CR9_EVENT_STORE_REAL 0x08000000 448 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 449 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 450 #define PER_CR9_CONTROL_ALTERATION 0x00200000 451 452 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 453 #define PER_CODE_EVENT_BRANCH 0x8000 454 #define PER_CODE_EVENT_IFETCH 0x4000 455 #define PER_CODE_EVENT_STORE 0x2000 456 #define PER_CODE_EVENT_STORE_REAL 0x0800 457 #define PER_CODE_EVENT_NULLIFICATION 0x0100 458 459 #define EXCP_EXT 1 /* external interrupt */ 460 #define EXCP_SVC 2 /* supervisor call (syscall) */ 461 #define EXCP_PGM 3 /* program interruption */ 462 #define EXCP_RESTART 4 /* restart interrupt */ 463 #define EXCP_STOP 5 /* stop interrupt */ 464 #define EXCP_IO 7 /* I/O interrupt */ 465 #define EXCP_MCHK 8 /* machine check */ 466 467 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 468 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 469 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 470 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 471 #define INTERRUPT_RESTART (1 << 7) 472 #define INTERRUPT_STOP (1 << 8) 473 474 /* Program Status Word. */ 475 #define S390_PSWM_REGNUM 0 476 #define S390_PSWA_REGNUM 1 477 /* General Purpose Registers. */ 478 #define S390_R0_REGNUM 2 479 #define S390_R1_REGNUM 3 480 #define S390_R2_REGNUM 4 481 #define S390_R3_REGNUM 5 482 #define S390_R4_REGNUM 6 483 #define S390_R5_REGNUM 7 484 #define S390_R6_REGNUM 8 485 #define S390_R7_REGNUM 9 486 #define S390_R8_REGNUM 10 487 #define S390_R9_REGNUM 11 488 #define S390_R10_REGNUM 12 489 #define S390_R11_REGNUM 13 490 #define S390_R12_REGNUM 14 491 #define S390_R13_REGNUM 15 492 #define S390_R14_REGNUM 16 493 #define S390_R15_REGNUM 17 494 495 static inline void setcc(S390CPU *cpu, uint64_t cc) 496 { 497 CPUS390XState *env = &cpu->env; 498 499 env->psw.mask &= ~(3ull << 44); 500 env->psw.mask |= (cc & 3) << 44; 501 env->cc_op = cc; 502 } 503 504 /* STSI */ 505 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 506 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 507 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 508 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 509 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 510 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 511 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 512 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 513 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 514 515 /* Basic Machine Configuration */ 516 typedef struct SysIB_111 { 517 uint8_t res1[32]; 518 uint8_t manuf[16]; 519 uint8_t type[4]; 520 uint8_t res2[12]; 521 uint8_t model[16]; 522 uint8_t sequence[16]; 523 uint8_t plant[4]; 524 uint8_t res3[3996]; 525 } SysIB_111; 526 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 527 528 /* Basic Machine CPU */ 529 typedef struct SysIB_121 { 530 uint8_t res1[80]; 531 uint8_t sequence[16]; 532 uint8_t plant[4]; 533 uint8_t res2[2]; 534 uint16_t cpu_addr; 535 uint8_t res3[3992]; 536 } SysIB_121; 537 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 538 539 /* Basic Machine CPUs */ 540 typedef struct SysIB_122 { 541 uint8_t res1[32]; 542 uint32_t capability; 543 uint16_t total_cpus; 544 uint16_t conf_cpus; 545 uint16_t standby_cpus; 546 uint16_t reserved_cpus; 547 uint16_t adjustments[2026]; 548 } SysIB_122; 549 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 550 551 /* LPAR CPU */ 552 typedef struct SysIB_221 { 553 uint8_t res1[80]; 554 uint8_t sequence[16]; 555 uint8_t plant[4]; 556 uint16_t cpu_id; 557 uint16_t cpu_addr; 558 uint8_t res3[3992]; 559 } SysIB_221; 560 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 561 562 /* LPAR CPUs */ 563 typedef struct SysIB_222 { 564 uint8_t res1[32]; 565 uint16_t lpar_num; 566 uint8_t res2; 567 uint8_t lcpuc; 568 uint16_t total_cpus; 569 uint16_t conf_cpus; 570 uint16_t standby_cpus; 571 uint16_t reserved_cpus; 572 uint8_t name[8]; 573 uint32_t caf; 574 uint8_t res3[16]; 575 uint16_t dedicated_cpus; 576 uint16_t shared_cpus; 577 uint8_t res4[4020]; 578 } SysIB_222; 579 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 580 581 /* VM CPUs */ 582 typedef struct SysIB_322 { 583 uint8_t res1[31]; 584 uint8_t count; 585 struct { 586 uint8_t res2[4]; 587 uint16_t total_cpus; 588 uint16_t conf_cpus; 589 uint16_t standby_cpus; 590 uint16_t reserved_cpus; 591 uint8_t name[8]; 592 uint32_t caf; 593 uint8_t cpi[16]; 594 uint8_t res5[3]; 595 uint8_t ext_name_encoding; 596 uint32_t res3; 597 uint8_t uuid[16]; 598 } vm[8]; 599 uint8_t res4[1504]; 600 uint8_t ext_names[8][256]; 601 } SysIB_322; 602 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 603 604 /* 605 * Topology Magnitude fields (MAG) indicates the maximum number of 606 * topology list entries (TLE) at the corresponding nesting level. 607 */ 608 #define S390_TOPOLOGY_MAG 6 609 #define S390_TOPOLOGY_MAG6 0 610 #define S390_TOPOLOGY_MAG5 1 611 #define S390_TOPOLOGY_MAG4 2 612 #define S390_TOPOLOGY_MAG3 3 613 #define S390_TOPOLOGY_MAG2 4 614 #define S390_TOPOLOGY_MAG1 5 615 /* Configuration topology */ 616 typedef struct SysIB_151x { 617 uint8_t reserved0[2]; 618 uint16_t length; 619 uint8_t mag[S390_TOPOLOGY_MAG]; 620 uint8_t reserved1; 621 uint8_t mnest; 622 uint32_t reserved2; 623 char tle[]; 624 } SysIB_151x; 625 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16); 626 627 typedef union SysIB { 628 SysIB_111 sysib_111; 629 SysIB_121 sysib_121; 630 SysIB_122 sysib_122; 631 SysIB_221 sysib_221; 632 SysIB_222 sysib_222; 633 SysIB_322 sysib_322; 634 SysIB_151x sysib_151x; 635 } SysIB; 636 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 637 638 /* 639 * CPU Topology List provided by STSI with fc=15 provides a list 640 * of two different Topology List Entries (TLE) types to specify 641 * the topology hierarchy. 642 * 643 * - Container Topology List Entry 644 * Defines a container to contain other Topology List Entries 645 * of any type, nested containers or CPU. 646 * - CPU Topology List Entry 647 * Specifies the CPUs position, type, entitlement and polarization 648 * of the CPUs contained in the last container TLE. 649 * 650 * There can be theoretically up to five levels of containers, QEMU 651 * uses only three levels, the drawer's, book's and socket's level. 652 * 653 * A container with a nesting level (NL) greater than 1 can only 654 * contain another container of nesting level NL-1. 655 * 656 * A container of nesting level 1 (socket), contains as many CPU TLE 657 * as needed to describe the position and qualities of all CPUs inside 658 * the container. 659 * The qualities of a CPU are polarization, entitlement and type. 660 * 661 * The CPU TLE defines the position of the CPUs of identical qualities 662 * using a 64bits mask which first bit has its offset defined by 663 * the CPU address origin field of the CPU TLE like in: 664 * CPU address = origin * 64 + bit position within the mask 665 */ 666 /* Container type Topology List Entry */ 667 typedef struct SYSIBContainerListEntry { 668 uint8_t nl; 669 uint8_t reserved[6]; 670 uint8_t id; 671 } SYSIBContainerListEntry; 672 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8); 673 674 /* CPU type Topology List Entry */ 675 typedef struct SysIBCPUListEntry { 676 uint8_t nl; 677 uint8_t reserved0[3]; 678 #define SYSIB_TLE_POLARITY_MASK 0x03 679 #define SYSIB_TLE_DEDICATED 0x04 680 uint8_t flags; 681 uint8_t type; 682 uint16_t origin; 683 uint64_t mask; 684 } SysIBCPUListEntry; 685 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16); 686 687 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra); 688 void s390_cpu_topology_set_changed(bool changed); 689 690 /* MMU defines */ 691 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 692 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 693 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 694 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 695 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 696 #define ASCE_REAL_SPACE 0x20 /* real space control */ 697 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 698 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 699 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 700 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 701 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 702 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 703 704 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 705 #define REGION_ENTRY_P 0x0000000000000200ULL 706 #define REGION_ENTRY_TF 0x00000000000000c0ULL 707 #define REGION_ENTRY_I 0x0000000000000020ULL 708 #define REGION_ENTRY_TT 0x000000000000000cULL 709 #define REGION_ENTRY_TL 0x0000000000000003ULL 710 711 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 712 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 713 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 714 715 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 716 #define REGION3_ENTRY_AV 0x0000000000010000ULL 717 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 718 #define REGION3_ENTRY_F 0x0000000000000800ULL 719 #define REGION3_ENTRY_FC 0x0000000000000400ULL 720 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 721 #define REGION3_ENTRY_CR 0x0000000000000010ULL 722 723 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 724 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 725 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 726 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 727 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 728 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 729 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 730 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 731 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 732 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 733 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 734 735 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 736 737 #define PAGE_ENTRY_0 0x0000000000000800ULL 738 #define PAGE_ENTRY_I 0x0000000000000400ULL 739 #define PAGE_ENTRY_P 0x0000000000000200ULL 740 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 741 742 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 743 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 744 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 745 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 746 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 747 748 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 749 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 750 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 751 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 752 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 753 754 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 755 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 756 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 757 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 758 759 #define SK_C (0x1 << 1) 760 #define SK_R (0x1 << 2) 761 #define SK_F (0x1 << 3) 762 #define SK_ACC_MASK (0xf << 4) 763 764 /* SIGP order codes */ 765 #define SIGP_SENSE 0x01 766 #define SIGP_EXTERNAL_CALL 0x02 767 #define SIGP_EMERGENCY 0x03 768 #define SIGP_START 0x04 769 #define SIGP_STOP 0x05 770 #define SIGP_RESTART 0x06 771 #define SIGP_STOP_STORE_STATUS 0x09 772 #define SIGP_INITIAL_CPU_RESET 0x0b 773 #define SIGP_CPU_RESET 0x0c 774 #define SIGP_SET_PREFIX 0x0d 775 #define SIGP_STORE_STATUS_ADDR 0x0e 776 #define SIGP_SET_ARCH 0x12 777 #define SIGP_COND_EMERGENCY 0x13 778 #define SIGP_SENSE_RUNNING 0x15 779 #define SIGP_STORE_ADTL_STATUS 0x17 780 781 /* SIGP condition codes */ 782 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 783 #define SIGP_CC_STATUS_STORED 1 784 #define SIGP_CC_BUSY 2 785 #define SIGP_CC_NOT_OPERATIONAL 3 786 787 /* SIGP status bits */ 788 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 789 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 790 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 791 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 792 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 793 #define SIGP_STAT_STOPPED 0x00000040UL 794 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 795 #define SIGP_STAT_CHECK_STOP 0x00000010UL 796 #define SIGP_STAT_INOPERATIVE 0x00000004UL 797 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 798 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 799 800 /* SIGP order code mask corresponding to bit positions 56-63 */ 801 #define SIGP_ORDER_MASK 0x000000ff 802 803 /* machine check interruption code */ 804 805 /* subclasses */ 806 #define MCIC_SC_SD 0x8000000000000000ULL 807 #define MCIC_SC_PD 0x4000000000000000ULL 808 #define MCIC_SC_SR 0x2000000000000000ULL 809 #define MCIC_SC_CD 0x0800000000000000ULL 810 #define MCIC_SC_ED 0x0400000000000000ULL 811 #define MCIC_SC_DG 0x0100000000000000ULL 812 #define MCIC_SC_W 0x0080000000000000ULL 813 #define MCIC_SC_CP 0x0040000000000000ULL 814 #define MCIC_SC_SP 0x0020000000000000ULL 815 #define MCIC_SC_CK 0x0010000000000000ULL 816 817 /* subclass modifiers */ 818 #define MCIC_SCM_B 0x0002000000000000ULL 819 #define MCIC_SCM_DA 0x0000000020000000ULL 820 #define MCIC_SCM_AP 0x0000000000080000ULL 821 822 /* storage errors */ 823 #define MCIC_SE_SE 0x0000800000000000ULL 824 #define MCIC_SE_SC 0x0000400000000000ULL 825 #define MCIC_SE_KE 0x0000200000000000ULL 826 #define MCIC_SE_DS 0x0000100000000000ULL 827 #define MCIC_SE_IE 0x0000000080000000ULL 828 829 /* validity bits */ 830 #define MCIC_VB_WP 0x0000080000000000ULL 831 #define MCIC_VB_MS 0x0000040000000000ULL 832 #define MCIC_VB_PM 0x0000020000000000ULL 833 #define MCIC_VB_IA 0x0000010000000000ULL 834 #define MCIC_VB_FA 0x0000008000000000ULL 835 #define MCIC_VB_VR 0x0000004000000000ULL 836 #define MCIC_VB_EC 0x0000002000000000ULL 837 #define MCIC_VB_FP 0x0000001000000000ULL 838 #define MCIC_VB_GR 0x0000000800000000ULL 839 #define MCIC_VB_CR 0x0000000400000000ULL 840 #define MCIC_VB_ST 0x0000000100000000ULL 841 #define MCIC_VB_AR 0x0000000040000000ULL 842 #define MCIC_VB_GS 0x0000000008000000ULL 843 #define MCIC_VB_PR 0x0000000000200000ULL 844 #define MCIC_VB_FC 0x0000000000100000ULL 845 #define MCIC_VB_CT 0x0000000000020000ULL 846 #define MCIC_VB_CC 0x0000000000010000ULL 847 848 static inline uint64_t s390_build_validity_mcic(void) 849 { 850 uint64_t mcic; 851 852 /* 853 * Indicate all validity bits (no damage) only. Other bits have to be 854 * added by the caller. (storage errors, subclasses and subclass modifiers) 855 */ 856 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 857 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 858 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 859 if (s390_has_feat(S390_FEAT_VECTOR)) { 860 mcic |= MCIC_VB_VR; 861 } 862 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 863 mcic |= MCIC_VB_GS; 864 } 865 return mcic; 866 } 867 868 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 869 { 870 cpu_reset(cs); 871 } 872 873 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 874 { 875 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 876 877 scc->reset(cs, S390_CPU_RESET_NORMAL); 878 } 879 880 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 881 { 882 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 883 884 scc->reset(cs, S390_CPU_RESET_INITIAL); 885 } 886 887 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 888 { 889 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 890 891 scc->load_normal(cs); 892 } 893 894 895 /* cpu.c */ 896 void s390_crypto_reset(void); 897 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 898 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 899 void s390_cmma_reset(void); 900 void s390_enable_css_support(S390CPU *cpu); 901 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 902 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 903 int vq, bool assign); 904 #ifndef CONFIG_USER_ONLY 905 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 906 #else 907 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 908 { 909 return 0; 910 } 911 #endif /* CONFIG_USER_ONLY */ 912 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 913 { 914 return cpu->env.cpu_state; 915 } 916 917 918 /* cpu_models.c */ 919 void s390_cpu_list(void); 920 #define cpu_list s390_cpu_list 921 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 922 const S390FeatInit feat_init); 923 924 925 /* helper.c */ 926 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 927 928 /* interrupt.c */ 929 #define RA_IGNORED 0 930 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 931 /* service interrupts are floating therefore we must not pass an cpustate */ 932 void s390_sclp_extint(uint32_t parm); 933 934 /* mmu_helper.c */ 935 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 936 int len, bool is_write); 937 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 938 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 939 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 940 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 941 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 942 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 943 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 944 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 945 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 946 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 947 int len, bool is_write); 948 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 949 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 950 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 951 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 952 953 /* sigp.c */ 954 int s390_cpu_restart(S390CPU *cpu); 955 void s390_init_sigp(void); 956 957 /* helper.c */ 958 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); 959 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); 960 961 /* outside of target/s390x/ */ 962 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 963 964 #include "exec/cpu-all.h" 965 966 #endif 967