1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * Copyright IBM Corp. 2012, 2018 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #ifndef S390X_CPU_H 22 #define S390X_CPU_H 23 24 #include "qemu-common.h" 25 #include "cpu-qom.h" 26 #include "cpu_models.h" 27 #include "exec/cpu-defs.h" 28 29 #define ELF_MACHINE_UNAME "S390X" 30 31 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 32 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 33 34 #define TARGET_INSN_START_EXTRA_WORDS 1 35 36 #define MMU_MODE0_SUFFIX _primary 37 #define MMU_MODE1_SUFFIX _secondary 38 #define MMU_MODE2_SUFFIX _home 39 #define MMU_MODE3_SUFFIX _real 40 41 #define MMU_USER_IDX 0 42 43 #define S390_MAX_CPUS 248 44 45 typedef struct PSW { 46 uint64_t mask; 47 uint64_t addr; 48 } PSW; 49 50 struct CPUS390XState { 51 uint64_t regs[16]; /* GP registers */ 52 /* 53 * The floating point registers are part of the vector registers. 54 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 55 */ 56 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 57 uint32_t aregs[16]; /* access registers */ 58 uint8_t riccb[64]; /* runtime instrumentation control */ 59 uint64_t gscb[4]; /* guarded storage control */ 60 uint64_t etoken; /* etoken */ 61 uint64_t etoken_extension; /* etoken extension */ 62 63 /* Fields up to this point are not cleared by initial CPU reset */ 64 struct {} start_initial_reset_fields; 65 66 uint32_t fpc; /* floating-point control register */ 67 uint32_t cc_op; 68 bool bpbc; /* branch prediction blocking */ 69 70 float_status fpu_status; /* passed to softfloat lib */ 71 72 /* The low part of a 128-bit return, or remainder of a divide. */ 73 uint64_t retxl; 74 75 PSW psw; 76 77 S390CrashReason crash_reason; 78 79 uint64_t cc_src; 80 uint64_t cc_dst; 81 uint64_t cc_vr; 82 83 uint64_t ex_value; 84 85 uint64_t __excp_addr; 86 uint64_t psa; 87 88 uint32_t int_pgm_code; 89 uint32_t int_pgm_ilen; 90 91 uint32_t int_svc_code; 92 uint32_t int_svc_ilen; 93 94 uint64_t per_address; 95 uint16_t per_perc_atmid; 96 97 uint64_t cregs[16]; /* control registers */ 98 99 int pending_int; 100 uint16_t external_call_addr; 101 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 102 103 uint64_t ckc; 104 uint64_t cputm; 105 uint32_t todpr; 106 107 uint64_t pfault_token; 108 uint64_t pfault_compare; 109 uint64_t pfault_select; 110 111 uint64_t gbea; 112 uint64_t pp; 113 114 /* Fields up to this point are cleared by a CPU reset */ 115 struct {} end_reset_fields; 116 117 #if !defined(CONFIG_USER_ONLY) 118 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 119 uint64_t cpuid; 120 #endif 121 122 QEMUTimer *tod_timer; 123 124 QEMUTimer *cpu_timer; 125 126 /* 127 * The cpu state represents the logical state of a cpu. In contrast to other 128 * architectures, there is a difference between a halt and a stop on s390. 129 * If all cpus are either stopped (including check stop) or in the disabled 130 * wait state, the vm can be shut down. 131 * The acceptable cpu_state values are defined in the CpuInfoS390State 132 * enum. 133 */ 134 uint8_t cpu_state; 135 136 /* currently processed sigp order */ 137 uint8_t sigp_order; 138 139 }; 140 141 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 142 { 143 return &cs->vregs[nr][0]; 144 } 145 146 /** 147 * S390CPU: 148 * @env: #CPUS390XState. 149 * 150 * An S/390 CPU. 151 */ 152 struct S390CPU { 153 /*< private >*/ 154 CPUState parent_obj; 155 /*< public >*/ 156 157 CPUNegativeOffsetState neg; 158 CPUS390XState env; 159 S390CPUModel *model; 160 /* needed for live migration */ 161 void *irqstate; 162 uint32_t irqstate_saved_size; 163 }; 164 165 166 #ifndef CONFIG_USER_ONLY 167 extern const struct VMStateDescription vmstate_s390_cpu; 168 #endif 169 170 /* distinguish between 24 bit and 31 bit addressing */ 171 #define HIGH_ORDER_BIT 0x80000000 172 173 /* Interrupt Codes */ 174 /* Program Interrupts */ 175 #define PGM_OPERATION 0x0001 176 #define PGM_PRIVILEGED 0x0002 177 #define PGM_EXECUTE 0x0003 178 #define PGM_PROTECTION 0x0004 179 #define PGM_ADDRESSING 0x0005 180 #define PGM_SPECIFICATION 0x0006 181 #define PGM_DATA 0x0007 182 #define PGM_FIXPT_OVERFLOW 0x0008 183 #define PGM_FIXPT_DIVIDE 0x0009 184 #define PGM_DEC_OVERFLOW 0x000a 185 #define PGM_DEC_DIVIDE 0x000b 186 #define PGM_HFP_EXP_OVERFLOW 0x000c 187 #define PGM_HFP_EXP_UNDERFLOW 0x000d 188 #define PGM_HFP_SIGNIFICANCE 0x000e 189 #define PGM_HFP_DIVIDE 0x000f 190 #define PGM_SEGMENT_TRANS 0x0010 191 #define PGM_PAGE_TRANS 0x0011 192 #define PGM_TRANS_SPEC 0x0012 193 #define PGM_SPECIAL_OP 0x0013 194 #define PGM_OPERAND 0x0015 195 #define PGM_TRACE_TABLE 0x0016 196 #define PGM_VECTOR_PROCESSING 0x001b 197 #define PGM_SPACE_SWITCH 0x001c 198 #define PGM_HFP_SQRT 0x001d 199 #define PGM_PC_TRANS_SPEC 0x001f 200 #define PGM_AFX_TRANS 0x0020 201 #define PGM_ASX_TRANS 0x0021 202 #define PGM_LX_TRANS 0x0022 203 #define PGM_EX_TRANS 0x0023 204 #define PGM_PRIM_AUTH 0x0024 205 #define PGM_SEC_AUTH 0x0025 206 #define PGM_ALET_SPEC 0x0028 207 #define PGM_ALEN_SPEC 0x0029 208 #define PGM_ALE_SEQ 0x002a 209 #define PGM_ASTE_VALID 0x002b 210 #define PGM_ASTE_SEQ 0x002c 211 #define PGM_EXT_AUTH 0x002d 212 #define PGM_STACK_FULL 0x0030 213 #define PGM_STACK_EMPTY 0x0031 214 #define PGM_STACK_SPEC 0x0032 215 #define PGM_STACK_TYPE 0x0033 216 #define PGM_STACK_OP 0x0034 217 #define PGM_ASCE_TYPE 0x0038 218 #define PGM_REG_FIRST_TRANS 0x0039 219 #define PGM_REG_SEC_TRANS 0x003a 220 #define PGM_REG_THIRD_TRANS 0x003b 221 #define PGM_MONITOR 0x0040 222 #define PGM_PER 0x0080 223 #define PGM_CRYPTO 0x0119 224 225 /* External Interrupts */ 226 #define EXT_INTERRUPT_KEY 0x0040 227 #define EXT_CLOCK_COMP 0x1004 228 #define EXT_CPU_TIMER 0x1005 229 #define EXT_MALFUNCTION 0x1200 230 #define EXT_EMERGENCY 0x1201 231 #define EXT_EXTERNAL_CALL 0x1202 232 #define EXT_ETR 0x1406 233 #define EXT_SERVICE 0x2401 234 #define EXT_VIRTIO 0x2603 235 236 /* PSW defines */ 237 #undef PSW_MASK_PER 238 #undef PSW_MASK_UNUSED_2 239 #undef PSW_MASK_UNUSED_3 240 #undef PSW_MASK_DAT 241 #undef PSW_MASK_IO 242 #undef PSW_MASK_EXT 243 #undef PSW_MASK_KEY 244 #undef PSW_SHIFT_KEY 245 #undef PSW_MASK_MCHECK 246 #undef PSW_MASK_WAIT 247 #undef PSW_MASK_PSTATE 248 #undef PSW_MASK_ASC 249 #undef PSW_SHIFT_ASC 250 #undef PSW_MASK_CC 251 #undef PSW_MASK_PM 252 #undef PSW_SHIFT_MASK_PM 253 #undef PSW_MASK_64 254 #undef PSW_MASK_32 255 #undef PSW_MASK_ESA_ADDR 256 257 #define PSW_MASK_PER 0x4000000000000000ULL 258 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 259 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 260 #define PSW_MASK_DAT 0x0400000000000000ULL 261 #define PSW_MASK_IO 0x0200000000000000ULL 262 #define PSW_MASK_EXT 0x0100000000000000ULL 263 #define PSW_MASK_KEY 0x00F0000000000000ULL 264 #define PSW_SHIFT_KEY 52 265 #define PSW_MASK_MCHECK 0x0004000000000000ULL 266 #define PSW_MASK_WAIT 0x0002000000000000ULL 267 #define PSW_MASK_PSTATE 0x0001000000000000ULL 268 #define PSW_MASK_ASC 0x0000C00000000000ULL 269 #define PSW_SHIFT_ASC 46 270 #define PSW_MASK_CC 0x0000300000000000ULL 271 #define PSW_MASK_PM 0x00000F0000000000ULL 272 #define PSW_SHIFT_MASK_PM 40 273 #define PSW_MASK_64 0x0000000100000000ULL 274 #define PSW_MASK_32 0x0000000080000000ULL 275 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 276 277 #undef PSW_ASC_PRIMARY 278 #undef PSW_ASC_ACCREG 279 #undef PSW_ASC_SECONDARY 280 #undef PSW_ASC_HOME 281 282 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 283 #define PSW_ASC_ACCREG 0x0000400000000000ULL 284 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 285 #define PSW_ASC_HOME 0x0000C00000000000ULL 286 287 /* the address space values shifted */ 288 #define AS_PRIMARY 0 289 #define AS_ACCREG 1 290 #define AS_SECONDARY 2 291 #define AS_HOME 3 292 293 /* tb flags */ 294 295 #define FLAG_MASK_PSW_SHIFT 31 296 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 297 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 298 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 299 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 300 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 301 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 302 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 303 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 304 305 /* we'll use some unused PSW positions to store CR flags in tb flags */ 306 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 307 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 308 309 /* Control register 0 bits */ 310 #define CR0_LOWPROT 0x0000000010000000ULL 311 #define CR0_SECONDARY 0x0000000004000000ULL 312 #define CR0_EDAT 0x0000000000800000ULL 313 #define CR0_AFP 0x0000000000040000ULL 314 #define CR0_VECTOR 0x0000000000020000ULL 315 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 316 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 317 #define CR0_CKC_SC 0x0000000000000800ULL 318 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 319 #define CR0_SERVICE_SC 0x0000000000000200ULL 320 321 /* Control register 14 bits */ 322 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 323 324 /* MMU */ 325 #define MMU_PRIMARY_IDX 0 326 #define MMU_SECONDARY_IDX 1 327 #define MMU_HOME_IDX 2 328 #define MMU_REAL_IDX 3 329 330 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 331 { 332 if (!(env->psw.mask & PSW_MASK_DAT)) { 333 return MMU_REAL_IDX; 334 } 335 336 switch (env->psw.mask & PSW_MASK_ASC) { 337 case PSW_ASC_PRIMARY: 338 return MMU_PRIMARY_IDX; 339 case PSW_ASC_SECONDARY: 340 return MMU_SECONDARY_IDX; 341 case PSW_ASC_HOME: 342 return MMU_HOME_IDX; 343 case PSW_ASC_ACCREG: 344 /* Fallthrough: access register mode is not yet supported */ 345 default: 346 abort(); 347 } 348 } 349 350 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 351 target_ulong *cs_base, uint32_t *flags) 352 { 353 *pc = env->psw.addr; 354 *cs_base = env->ex_value; 355 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 356 if (env->cregs[0] & CR0_AFP) { 357 *flags |= FLAG_MASK_AFP; 358 } 359 if (env->cregs[0] & CR0_VECTOR) { 360 *flags |= FLAG_MASK_VECTOR; 361 } 362 } 363 364 /* PER bits from control register 9 */ 365 #define PER_CR9_EVENT_BRANCH 0x80000000 366 #define PER_CR9_EVENT_IFETCH 0x40000000 367 #define PER_CR9_EVENT_STORE 0x20000000 368 #define PER_CR9_EVENT_STORE_REAL 0x08000000 369 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 370 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 371 #define PER_CR9_CONTROL_ALTERATION 0x00200000 372 373 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 374 #define PER_CODE_EVENT_BRANCH 0x8000 375 #define PER_CODE_EVENT_IFETCH 0x4000 376 #define PER_CODE_EVENT_STORE 0x2000 377 #define PER_CODE_EVENT_STORE_REAL 0x0800 378 #define PER_CODE_EVENT_NULLIFICATION 0x0100 379 380 #define EXCP_EXT 1 /* external interrupt */ 381 #define EXCP_SVC 2 /* supervisor call (syscall) */ 382 #define EXCP_PGM 3 /* program interruption */ 383 #define EXCP_RESTART 4 /* restart interrupt */ 384 #define EXCP_STOP 5 /* stop interrupt */ 385 #define EXCP_IO 7 /* I/O interrupt */ 386 #define EXCP_MCHK 8 /* machine check */ 387 388 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 389 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 390 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 391 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 392 #define INTERRUPT_RESTART (1 << 7) 393 #define INTERRUPT_STOP (1 << 8) 394 395 /* Program Status Word. */ 396 #define S390_PSWM_REGNUM 0 397 #define S390_PSWA_REGNUM 1 398 /* General Purpose Registers. */ 399 #define S390_R0_REGNUM 2 400 #define S390_R1_REGNUM 3 401 #define S390_R2_REGNUM 4 402 #define S390_R3_REGNUM 5 403 #define S390_R4_REGNUM 6 404 #define S390_R5_REGNUM 7 405 #define S390_R6_REGNUM 8 406 #define S390_R7_REGNUM 9 407 #define S390_R8_REGNUM 10 408 #define S390_R9_REGNUM 11 409 #define S390_R10_REGNUM 12 410 #define S390_R11_REGNUM 13 411 #define S390_R12_REGNUM 14 412 #define S390_R13_REGNUM 15 413 #define S390_R14_REGNUM 16 414 #define S390_R15_REGNUM 17 415 /* Total Core Registers. */ 416 #define S390_NUM_CORE_REGS 18 417 418 static inline void setcc(S390CPU *cpu, uint64_t cc) 419 { 420 CPUS390XState *env = &cpu->env; 421 422 env->psw.mask &= ~(3ull << 44); 423 env->psw.mask |= (cc & 3) << 44; 424 env->cc_op = cc; 425 } 426 427 /* STSI */ 428 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 429 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 430 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 431 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 432 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 433 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 434 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 435 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 436 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 437 438 /* Basic Machine Configuration */ 439 typedef struct SysIB_111 { 440 uint8_t res1[32]; 441 uint8_t manuf[16]; 442 uint8_t type[4]; 443 uint8_t res2[12]; 444 uint8_t model[16]; 445 uint8_t sequence[16]; 446 uint8_t plant[4]; 447 uint8_t res3[3996]; 448 } SysIB_111; 449 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 450 451 /* Basic Machine CPU */ 452 typedef struct SysIB_121 { 453 uint8_t res1[80]; 454 uint8_t sequence[16]; 455 uint8_t plant[4]; 456 uint8_t res2[2]; 457 uint16_t cpu_addr; 458 uint8_t res3[3992]; 459 } SysIB_121; 460 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 461 462 /* Basic Machine CPUs */ 463 typedef struct SysIB_122 { 464 uint8_t res1[32]; 465 uint32_t capability; 466 uint16_t total_cpus; 467 uint16_t conf_cpus; 468 uint16_t standby_cpus; 469 uint16_t reserved_cpus; 470 uint16_t adjustments[2026]; 471 } SysIB_122; 472 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 473 474 /* LPAR CPU */ 475 typedef struct SysIB_221 { 476 uint8_t res1[80]; 477 uint8_t sequence[16]; 478 uint8_t plant[4]; 479 uint16_t cpu_id; 480 uint16_t cpu_addr; 481 uint8_t res3[3992]; 482 } SysIB_221; 483 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 484 485 /* LPAR CPUs */ 486 typedef struct SysIB_222 { 487 uint8_t res1[32]; 488 uint16_t lpar_num; 489 uint8_t res2; 490 uint8_t lcpuc; 491 uint16_t total_cpus; 492 uint16_t conf_cpus; 493 uint16_t standby_cpus; 494 uint16_t reserved_cpus; 495 uint8_t name[8]; 496 uint32_t caf; 497 uint8_t res3[16]; 498 uint16_t dedicated_cpus; 499 uint16_t shared_cpus; 500 uint8_t res4[4020]; 501 } SysIB_222; 502 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 503 504 /* VM CPUs */ 505 typedef struct SysIB_322 { 506 uint8_t res1[31]; 507 uint8_t count; 508 struct { 509 uint8_t res2[4]; 510 uint16_t total_cpus; 511 uint16_t conf_cpus; 512 uint16_t standby_cpus; 513 uint16_t reserved_cpus; 514 uint8_t name[8]; 515 uint32_t caf; 516 uint8_t cpi[16]; 517 uint8_t res5[3]; 518 uint8_t ext_name_encoding; 519 uint32_t res3; 520 uint8_t uuid[16]; 521 } vm[8]; 522 uint8_t res4[1504]; 523 uint8_t ext_names[8][256]; 524 } SysIB_322; 525 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 526 527 typedef union SysIB { 528 SysIB_111 sysib_111; 529 SysIB_121 sysib_121; 530 SysIB_122 sysib_122; 531 SysIB_221 sysib_221; 532 SysIB_222 sysib_222; 533 SysIB_322 sysib_322; 534 } SysIB; 535 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 536 537 /* MMU defines */ 538 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 539 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 540 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 541 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 542 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 543 #define ASCE_REAL_SPACE 0x20 /* real space control */ 544 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 545 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 546 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 547 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 548 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 549 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 550 551 #define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */ 552 #define REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 553 #define REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 554 #define REGION_ENTRY_INV 0x20 /* invalid region table entry */ 555 #define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 556 #define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 557 #define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 558 #define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 559 #define REGION_ENTRY_LENGTH 0x03 /* region third length */ 560 561 #define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */ 562 #define SEGMENT_ENTRY_FC 0x400 /* format control */ 563 #define SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 564 #define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 565 566 #define VADDR_PX 0xff000 /* page index bits */ 567 568 #define PAGE_RO 0x200 /* HW read-only bit */ 569 #define PAGE_INVALID 0x400 /* HW invalid bit */ 570 #define PAGE_RES0 0x800 /* bit must be zero */ 571 572 #define SK_C (0x1 << 1) 573 #define SK_R (0x1 << 2) 574 #define SK_F (0x1 << 3) 575 #define SK_ACC_MASK (0xf << 4) 576 577 /* SIGP order codes */ 578 #define SIGP_SENSE 0x01 579 #define SIGP_EXTERNAL_CALL 0x02 580 #define SIGP_EMERGENCY 0x03 581 #define SIGP_START 0x04 582 #define SIGP_STOP 0x05 583 #define SIGP_RESTART 0x06 584 #define SIGP_STOP_STORE_STATUS 0x09 585 #define SIGP_INITIAL_CPU_RESET 0x0b 586 #define SIGP_CPU_RESET 0x0c 587 #define SIGP_SET_PREFIX 0x0d 588 #define SIGP_STORE_STATUS_ADDR 0x0e 589 #define SIGP_SET_ARCH 0x12 590 #define SIGP_COND_EMERGENCY 0x13 591 #define SIGP_SENSE_RUNNING 0x15 592 #define SIGP_STORE_ADTL_STATUS 0x17 593 594 /* SIGP condition codes */ 595 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 596 #define SIGP_CC_STATUS_STORED 1 597 #define SIGP_CC_BUSY 2 598 #define SIGP_CC_NOT_OPERATIONAL 3 599 600 /* SIGP status bits */ 601 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 602 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 603 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 604 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 605 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 606 #define SIGP_STAT_STOPPED 0x00000040UL 607 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 608 #define SIGP_STAT_CHECK_STOP 0x00000010UL 609 #define SIGP_STAT_INOPERATIVE 0x00000004UL 610 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 611 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 612 613 /* SIGP SET ARCHITECTURE modes */ 614 #define SIGP_MODE_ESA_S390 0 615 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 616 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 617 618 /* SIGP order code mask corresponding to bit positions 56-63 */ 619 #define SIGP_ORDER_MASK 0x000000ff 620 621 /* machine check interruption code */ 622 623 /* subclasses */ 624 #define MCIC_SC_SD 0x8000000000000000ULL 625 #define MCIC_SC_PD 0x4000000000000000ULL 626 #define MCIC_SC_SR 0x2000000000000000ULL 627 #define MCIC_SC_CD 0x0800000000000000ULL 628 #define MCIC_SC_ED 0x0400000000000000ULL 629 #define MCIC_SC_DG 0x0100000000000000ULL 630 #define MCIC_SC_W 0x0080000000000000ULL 631 #define MCIC_SC_CP 0x0040000000000000ULL 632 #define MCIC_SC_SP 0x0020000000000000ULL 633 #define MCIC_SC_CK 0x0010000000000000ULL 634 635 /* subclass modifiers */ 636 #define MCIC_SCM_B 0x0002000000000000ULL 637 #define MCIC_SCM_DA 0x0000000020000000ULL 638 #define MCIC_SCM_AP 0x0000000000080000ULL 639 640 /* storage errors */ 641 #define MCIC_SE_SE 0x0000800000000000ULL 642 #define MCIC_SE_SC 0x0000400000000000ULL 643 #define MCIC_SE_KE 0x0000200000000000ULL 644 #define MCIC_SE_DS 0x0000100000000000ULL 645 #define MCIC_SE_IE 0x0000000080000000ULL 646 647 /* validity bits */ 648 #define MCIC_VB_WP 0x0000080000000000ULL 649 #define MCIC_VB_MS 0x0000040000000000ULL 650 #define MCIC_VB_PM 0x0000020000000000ULL 651 #define MCIC_VB_IA 0x0000010000000000ULL 652 #define MCIC_VB_FA 0x0000008000000000ULL 653 #define MCIC_VB_VR 0x0000004000000000ULL 654 #define MCIC_VB_EC 0x0000002000000000ULL 655 #define MCIC_VB_FP 0x0000001000000000ULL 656 #define MCIC_VB_GR 0x0000000800000000ULL 657 #define MCIC_VB_CR 0x0000000400000000ULL 658 #define MCIC_VB_ST 0x0000000100000000ULL 659 #define MCIC_VB_AR 0x0000000040000000ULL 660 #define MCIC_VB_GS 0x0000000008000000ULL 661 #define MCIC_VB_PR 0x0000000000200000ULL 662 #define MCIC_VB_FC 0x0000000000100000ULL 663 #define MCIC_VB_CT 0x0000000000020000ULL 664 #define MCIC_VB_CC 0x0000000000010000ULL 665 666 static inline uint64_t s390_build_validity_mcic(void) 667 { 668 uint64_t mcic; 669 670 /* 671 * Indicate all validity bits (no damage) only. Other bits have to be 672 * added by the caller. (storage errors, subclasses and subclass modifiers) 673 */ 674 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 675 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 676 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 677 if (s390_has_feat(S390_FEAT_VECTOR)) { 678 mcic |= MCIC_VB_VR; 679 } 680 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 681 mcic |= MCIC_VB_GS; 682 } 683 return mcic; 684 } 685 686 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 687 { 688 cpu_reset(cs); 689 } 690 691 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 692 { 693 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 694 695 scc->cpu_reset(cs); 696 } 697 698 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 699 { 700 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 701 702 scc->initial_cpu_reset(cs); 703 } 704 705 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 706 { 707 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 708 709 scc->load_normal(cs); 710 } 711 712 713 /* cpu.c */ 714 void s390_crypto_reset(void); 715 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 716 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 717 void s390_cmma_reset(void); 718 void s390_enable_css_support(S390CPU *cpu); 719 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 720 int vq, bool assign); 721 #ifndef CONFIG_USER_ONLY 722 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 723 #else 724 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 725 { 726 return 0; 727 } 728 #endif /* CONFIG_USER_ONLY */ 729 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 730 { 731 return cpu->env.cpu_state; 732 } 733 734 735 /* cpu_models.c */ 736 void s390_cpu_list(void); 737 #define cpu_list s390_cpu_list 738 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 739 const S390FeatInit feat_init); 740 741 742 /* helper.c */ 743 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 744 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 745 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 746 747 /* you can call this signal handler from your SIGBUS and SIGSEGV 748 signal handlers to inform the virtual CPU of exceptions. non zero 749 is returned if the signal was handled by the virtual CPU. */ 750 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 751 #define cpu_signal_handler cpu_s390x_signal_handler 752 753 754 /* interrupt.c */ 755 void s390_crw_mchk(void); 756 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 757 uint32_t io_int_parm, uint32_t io_int_word); 758 /* automatically detect the instruction length */ 759 #define ILEN_AUTO 0xff 760 #define RA_IGNORED 0 761 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, 762 uintptr_t ra); 763 /* service interrupts are floating therefore we must not pass an cpustate */ 764 void s390_sclp_extint(uint32_t parm); 765 766 /* mmu_helper.c */ 767 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 768 int len, bool is_write); 769 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 770 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 771 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 772 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 773 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 774 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 775 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 776 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 777 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 778 779 780 /* sigp.c */ 781 int s390_cpu_restart(S390CPU *cpu); 782 void s390_init_sigp(void); 783 784 785 /* outside of target/s390x/ */ 786 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 787 788 typedef CPUS390XState CPUArchState; 789 typedef S390CPU ArchCPU; 790 791 #include "exec/cpu-all.h" 792 793 #endif 794