1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * Contributions after 2012-10-29 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 * 19 * You should have received a copy of the GNU (Lesser) General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef S390X_CPU_H 24 #define S390X_CPU_H 25 26 #include "qemu-common.h" 27 #include "cpu-qom.h" 28 #include "cpu_models.h" 29 30 #define TARGET_LONG_BITS 64 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 #define CPUArchState struct CPUS390XState 35 36 #include "exec/cpu-defs.h" 37 #define TARGET_PAGE_BITS 12 38 39 #define TARGET_PHYS_ADDR_SPACE_BITS 64 40 #define TARGET_VIRT_ADDR_SPACE_BITS 64 41 42 #include "exec/cpu-all.h" 43 44 #include "fpu/softfloat.h" 45 46 #define NB_MMU_MODES 4 47 #define TARGET_INSN_START_EXTRA_WORDS 1 48 49 #define MMU_MODE0_SUFFIX _primary 50 #define MMU_MODE1_SUFFIX _secondary 51 #define MMU_MODE2_SUFFIX _home 52 #define MMU_MODE3_SUFFIX _real 53 54 #define MMU_USER_IDX 0 55 56 #define MAX_IO_QUEUE 16 57 58 #define S390_MAX_CPUS 248 59 60 typedef struct PSW { 61 uint64_t mask; 62 uint64_t addr; 63 } PSW; 64 65 typedef struct IOIntQueue { 66 uint16_t id; 67 uint16_t nr; 68 uint32_t parm; 69 uint32_t word; 70 } IOIntQueue; 71 72 struct CPUS390XState { 73 uint64_t regs[16]; /* GP registers */ 74 /* 75 * The floating point registers are part of the vector registers. 76 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 77 */ 78 CPU_DoubleU vregs[32][2]; /* vector registers */ 79 uint32_t aregs[16]; /* access registers */ 80 uint8_t riccb[64]; /* runtime instrumentation control */ 81 uint64_t gscb[4]; /* guarded storage control */ 82 83 /* Fields up to this point are not cleared by initial CPU reset */ 84 struct {} start_initial_reset_fields; 85 86 uint32_t fpc; /* floating-point control register */ 87 uint32_t cc_op; 88 bool bpbc; /* branch prediction blocking */ 89 90 float_status fpu_status; /* passed to softfloat lib */ 91 92 /* The low part of a 128-bit return, or remainder of a divide. */ 93 uint64_t retxl; 94 95 PSW psw; 96 97 uint64_t cc_src; 98 uint64_t cc_dst; 99 uint64_t cc_vr; 100 101 uint64_t ex_value; 102 103 uint64_t __excp_addr; 104 uint64_t psa; 105 106 uint32_t int_pgm_code; 107 uint32_t int_pgm_ilen; 108 109 uint32_t int_svc_code; 110 uint32_t int_svc_ilen; 111 112 uint64_t per_address; 113 uint16_t per_perc_atmid; 114 115 uint64_t cregs[16]; /* control registers */ 116 117 IOIntQueue io_queue[MAX_IO_QUEUE][8]; 118 119 int pending_int; 120 uint32_t service_param; 121 uint16_t external_call_addr; 122 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 123 int io_index[8]; 124 125 uint64_t ckc; 126 uint64_t cputm; 127 uint32_t todpr; 128 129 uint64_t pfault_token; 130 uint64_t pfault_compare; 131 uint64_t pfault_select; 132 133 uint64_t gbea; 134 uint64_t pp; 135 136 /* Fields up to this point are cleared by a CPU reset */ 137 struct {} end_reset_fields; 138 139 CPU_COMMON 140 141 #if !defined(CONFIG_USER_ONLY) 142 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 143 uint64_t cpuid; 144 #endif 145 146 uint64_t tod_offset; 147 uint64_t tod_basetime; 148 QEMUTimer *tod_timer; 149 150 QEMUTimer *cpu_timer; 151 152 /* 153 * The cpu state represents the logical state of a cpu. In contrast to other 154 * architectures, there is a difference between a halt and a stop on s390. 155 * If all cpus are either stopped (including check stop) or in the disabled 156 * wait state, the vm can be shut down. 157 */ 158 #define CPU_STATE_UNINITIALIZED 0x00 159 #define CPU_STATE_STOPPED 0x01 160 #define CPU_STATE_CHECK_STOP 0x02 161 #define CPU_STATE_OPERATING 0x03 162 #define CPU_STATE_LOAD 0x04 163 uint8_t cpu_state; 164 165 /* currently processed sigp order */ 166 uint8_t sigp_order; 167 168 }; 169 170 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) 171 { 172 return &cs->vregs[nr][0]; 173 } 174 175 /** 176 * S390CPU: 177 * @env: #CPUS390XState. 178 * 179 * An S/390 CPU. 180 */ 181 struct S390CPU { 182 /*< private >*/ 183 CPUState parent_obj; 184 /*< public >*/ 185 186 CPUS390XState env; 187 S390CPUModel *model; 188 /* needed for live migration */ 189 void *irqstate; 190 uint32_t irqstate_saved_size; 191 }; 192 193 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) 194 { 195 return container_of(env, S390CPU, env); 196 } 197 198 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) 199 200 #define ENV_OFFSET offsetof(S390CPU, env) 201 202 #ifndef CONFIG_USER_ONLY 203 extern const struct VMStateDescription vmstate_s390_cpu; 204 #endif 205 206 /* distinguish between 24 bit and 31 bit addressing */ 207 #define HIGH_ORDER_BIT 0x80000000 208 209 /* Interrupt Codes */ 210 /* Program Interrupts */ 211 #define PGM_OPERATION 0x0001 212 #define PGM_PRIVILEGED 0x0002 213 #define PGM_EXECUTE 0x0003 214 #define PGM_PROTECTION 0x0004 215 #define PGM_ADDRESSING 0x0005 216 #define PGM_SPECIFICATION 0x0006 217 #define PGM_DATA 0x0007 218 #define PGM_FIXPT_OVERFLOW 0x0008 219 #define PGM_FIXPT_DIVIDE 0x0009 220 #define PGM_DEC_OVERFLOW 0x000a 221 #define PGM_DEC_DIVIDE 0x000b 222 #define PGM_HFP_EXP_OVERFLOW 0x000c 223 #define PGM_HFP_EXP_UNDERFLOW 0x000d 224 #define PGM_HFP_SIGNIFICANCE 0x000e 225 #define PGM_HFP_DIVIDE 0x000f 226 #define PGM_SEGMENT_TRANS 0x0010 227 #define PGM_PAGE_TRANS 0x0011 228 #define PGM_TRANS_SPEC 0x0012 229 #define PGM_SPECIAL_OP 0x0013 230 #define PGM_OPERAND 0x0015 231 #define PGM_TRACE_TABLE 0x0016 232 #define PGM_SPACE_SWITCH 0x001c 233 #define PGM_HFP_SQRT 0x001d 234 #define PGM_PC_TRANS_SPEC 0x001f 235 #define PGM_AFX_TRANS 0x0020 236 #define PGM_ASX_TRANS 0x0021 237 #define PGM_LX_TRANS 0x0022 238 #define PGM_EX_TRANS 0x0023 239 #define PGM_PRIM_AUTH 0x0024 240 #define PGM_SEC_AUTH 0x0025 241 #define PGM_ALET_SPEC 0x0028 242 #define PGM_ALEN_SPEC 0x0029 243 #define PGM_ALE_SEQ 0x002a 244 #define PGM_ASTE_VALID 0x002b 245 #define PGM_ASTE_SEQ 0x002c 246 #define PGM_EXT_AUTH 0x002d 247 #define PGM_STACK_FULL 0x0030 248 #define PGM_STACK_EMPTY 0x0031 249 #define PGM_STACK_SPEC 0x0032 250 #define PGM_STACK_TYPE 0x0033 251 #define PGM_STACK_OP 0x0034 252 #define PGM_ASCE_TYPE 0x0038 253 #define PGM_REG_FIRST_TRANS 0x0039 254 #define PGM_REG_SEC_TRANS 0x003a 255 #define PGM_REG_THIRD_TRANS 0x003b 256 #define PGM_MONITOR 0x0040 257 #define PGM_PER 0x0080 258 #define PGM_CRYPTO 0x0119 259 260 /* External Interrupts */ 261 #define EXT_INTERRUPT_KEY 0x0040 262 #define EXT_CLOCK_COMP 0x1004 263 #define EXT_CPU_TIMER 0x1005 264 #define EXT_MALFUNCTION 0x1200 265 #define EXT_EMERGENCY 0x1201 266 #define EXT_EXTERNAL_CALL 0x1202 267 #define EXT_ETR 0x1406 268 #define EXT_SERVICE 0x2401 269 #define EXT_VIRTIO 0x2603 270 271 /* PSW defines */ 272 #undef PSW_MASK_PER 273 #undef PSW_MASK_DAT 274 #undef PSW_MASK_IO 275 #undef PSW_MASK_EXT 276 #undef PSW_MASK_KEY 277 #undef PSW_SHIFT_KEY 278 #undef PSW_MASK_MCHECK 279 #undef PSW_MASK_WAIT 280 #undef PSW_MASK_PSTATE 281 #undef PSW_MASK_ASC 282 #undef PSW_SHIFT_ASC 283 #undef PSW_MASK_CC 284 #undef PSW_MASK_PM 285 #undef PSW_SHIFT_MASK_PM 286 #undef PSW_MASK_64 287 #undef PSW_MASK_32 288 #undef PSW_MASK_ESA_ADDR 289 290 #define PSW_MASK_PER 0x4000000000000000ULL 291 #define PSW_MASK_DAT 0x0400000000000000ULL 292 #define PSW_MASK_IO 0x0200000000000000ULL 293 #define PSW_MASK_EXT 0x0100000000000000ULL 294 #define PSW_MASK_KEY 0x00F0000000000000ULL 295 #define PSW_SHIFT_KEY 52 296 #define PSW_MASK_MCHECK 0x0004000000000000ULL 297 #define PSW_MASK_WAIT 0x0002000000000000ULL 298 #define PSW_MASK_PSTATE 0x0001000000000000ULL 299 #define PSW_MASK_ASC 0x0000C00000000000ULL 300 #define PSW_SHIFT_ASC 46 301 #define PSW_MASK_CC 0x0000300000000000ULL 302 #define PSW_MASK_PM 0x00000F0000000000ULL 303 #define PSW_SHIFT_MASK_PM 40 304 #define PSW_MASK_64 0x0000000100000000ULL 305 #define PSW_MASK_32 0x0000000080000000ULL 306 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 307 308 #undef PSW_ASC_PRIMARY 309 #undef PSW_ASC_ACCREG 310 #undef PSW_ASC_SECONDARY 311 #undef PSW_ASC_HOME 312 313 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 314 #define PSW_ASC_ACCREG 0x0000400000000000ULL 315 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 316 #define PSW_ASC_HOME 0x0000C00000000000ULL 317 318 /* the address space values shifted */ 319 #define AS_PRIMARY 0 320 #define AS_ACCREG 1 321 #define AS_SECONDARY 2 322 #define AS_HOME 3 323 324 /* tb flags */ 325 326 #define FLAG_MASK_PSW_SHIFT 31 327 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 328 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 329 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 330 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 331 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 332 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \ 333 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 334 335 /* Control register 0 bits */ 336 #define CR0_LOWPROT 0x0000000010000000ULL 337 #define CR0_SECONDARY 0x0000000004000000ULL 338 #define CR0_EDAT 0x0000000000800000ULL 339 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 340 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 341 #define CR0_CKC_SC 0x0000000000000800ULL 342 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 343 #define CR0_SERVICE_SC 0x0000000000000200ULL 344 345 /* Control register 14 bits */ 346 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 347 348 /* MMU */ 349 #define MMU_PRIMARY_IDX 0 350 #define MMU_SECONDARY_IDX 1 351 #define MMU_HOME_IDX 2 352 #define MMU_REAL_IDX 3 353 354 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 355 { 356 switch (env->psw.mask & PSW_MASK_ASC) { 357 case PSW_ASC_PRIMARY: 358 return MMU_PRIMARY_IDX; 359 case PSW_ASC_SECONDARY: 360 return MMU_SECONDARY_IDX; 361 case PSW_ASC_HOME: 362 return MMU_HOME_IDX; 363 case PSW_ASC_ACCREG: 364 /* Fallthrough: access register mode is not yet supported */ 365 default: 366 abort(); 367 } 368 } 369 370 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 371 target_ulong *cs_base, uint32_t *flags) 372 { 373 *pc = env->psw.addr; 374 *cs_base = env->ex_value; 375 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 376 } 377 378 /* PER bits from control register 9 */ 379 #define PER_CR9_EVENT_BRANCH 0x80000000 380 #define PER_CR9_EVENT_IFETCH 0x40000000 381 #define PER_CR9_EVENT_STORE 0x20000000 382 #define PER_CR9_EVENT_STORE_REAL 0x08000000 383 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 384 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 385 #define PER_CR9_CONTROL_ALTERATION 0x00200000 386 387 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 388 #define PER_CODE_EVENT_BRANCH 0x8000 389 #define PER_CODE_EVENT_IFETCH 0x4000 390 #define PER_CODE_EVENT_STORE 0x2000 391 #define PER_CODE_EVENT_STORE_REAL 0x0800 392 #define PER_CODE_EVENT_NULLIFICATION 0x0100 393 394 #define EXCP_EXT 1 /* external interrupt */ 395 #define EXCP_SVC 2 /* supervisor call (syscall) */ 396 #define EXCP_PGM 3 /* program interruption */ 397 #define EXCP_RESTART 4 /* restart interrupt */ 398 #define EXCP_STOP 5 /* stop interrupt */ 399 #define EXCP_IO 7 /* I/O interrupt */ 400 #define EXCP_MCHK 8 /* machine check */ 401 402 #define INTERRUPT_IO (1 << 0) 403 #define INTERRUPT_MCHK (1 << 1) 404 #define INTERRUPT_EXT_SERVICE (1 << 2) 405 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 406 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 407 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 408 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 409 #define INTERRUPT_RESTART (1 << 7) 410 #define INTERRUPT_STOP (1 << 8) 411 412 /* Program Status Word. */ 413 #define S390_PSWM_REGNUM 0 414 #define S390_PSWA_REGNUM 1 415 /* General Purpose Registers. */ 416 #define S390_R0_REGNUM 2 417 #define S390_R1_REGNUM 3 418 #define S390_R2_REGNUM 4 419 #define S390_R3_REGNUM 5 420 #define S390_R4_REGNUM 6 421 #define S390_R5_REGNUM 7 422 #define S390_R6_REGNUM 8 423 #define S390_R7_REGNUM 9 424 #define S390_R8_REGNUM 10 425 #define S390_R9_REGNUM 11 426 #define S390_R10_REGNUM 12 427 #define S390_R11_REGNUM 13 428 #define S390_R12_REGNUM 14 429 #define S390_R13_REGNUM 15 430 #define S390_R14_REGNUM 16 431 #define S390_R15_REGNUM 17 432 /* Total Core Registers. */ 433 #define S390_NUM_CORE_REGS 18 434 435 static inline void setcc(S390CPU *cpu, uint64_t cc) 436 { 437 CPUS390XState *env = &cpu->env; 438 439 env->psw.mask &= ~(3ull << 44); 440 env->psw.mask |= (cc & 3) << 44; 441 env->cc_op = cc; 442 } 443 444 /* STSI */ 445 #define STSI_LEVEL_MASK 0x00000000f0000000ULL 446 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL 447 #define STSI_LEVEL_1 0x0000000010000000ULL 448 #define STSI_LEVEL_2 0x0000000020000000ULL 449 #define STSI_LEVEL_3 0x0000000030000000ULL 450 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 451 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 452 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 453 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 454 455 /* Basic Machine Configuration */ 456 struct sysib_111 { 457 uint32_t res1[8]; 458 uint8_t manuf[16]; 459 uint8_t type[4]; 460 uint8_t res2[12]; 461 uint8_t model[16]; 462 uint8_t sequence[16]; 463 uint8_t plant[4]; 464 uint8_t res3[156]; 465 }; 466 467 /* Basic Machine CPU */ 468 struct sysib_121 { 469 uint32_t res1[80]; 470 uint8_t sequence[16]; 471 uint8_t plant[4]; 472 uint8_t res2[2]; 473 uint16_t cpu_addr; 474 uint8_t res3[152]; 475 }; 476 477 /* Basic Machine CPUs */ 478 struct sysib_122 { 479 uint8_t res1[32]; 480 uint32_t capability; 481 uint16_t total_cpus; 482 uint16_t active_cpus; 483 uint16_t standby_cpus; 484 uint16_t reserved_cpus; 485 uint16_t adjustments[2026]; 486 }; 487 488 /* LPAR CPU */ 489 struct sysib_221 { 490 uint32_t res1[80]; 491 uint8_t sequence[16]; 492 uint8_t plant[4]; 493 uint16_t cpu_id; 494 uint16_t cpu_addr; 495 uint8_t res3[152]; 496 }; 497 498 /* LPAR CPUs */ 499 struct sysib_222 { 500 uint32_t res1[32]; 501 uint16_t lpar_num; 502 uint8_t res2; 503 uint8_t lcpuc; 504 uint16_t total_cpus; 505 uint16_t conf_cpus; 506 uint16_t standby_cpus; 507 uint16_t reserved_cpus; 508 uint8_t name[8]; 509 uint32_t caf; 510 uint8_t res3[16]; 511 uint16_t dedicated_cpus; 512 uint16_t shared_cpus; 513 uint8_t res4[180]; 514 }; 515 516 /* VM CPUs */ 517 struct sysib_322 { 518 uint8_t res1[31]; 519 uint8_t count; 520 struct { 521 uint8_t res2[4]; 522 uint16_t total_cpus; 523 uint16_t conf_cpus; 524 uint16_t standby_cpus; 525 uint16_t reserved_cpus; 526 uint8_t name[8]; 527 uint32_t caf; 528 uint8_t cpi[16]; 529 uint8_t res5[3]; 530 uint8_t ext_name_encoding; 531 uint32_t res3; 532 uint8_t uuid[16]; 533 } vm[8]; 534 uint8_t res4[1504]; 535 uint8_t ext_names[8][256]; 536 }; 537 538 /* MMU defines */ 539 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ 540 #define _ASCE_SUBSPACE 0x200 /* subspace group control */ 541 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 542 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 543 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 544 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 545 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 546 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 547 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 548 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 549 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 550 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 551 552 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ 553 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 554 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 555 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 556 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 557 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 558 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 559 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 560 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 561 562 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ 563 #define _SEGMENT_ENTRY_FC 0x400 /* format control */ 564 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 565 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 566 567 #define VADDR_PX 0xff000 /* page index bits */ 568 569 #define _PAGE_RO 0x200 /* HW read-only bit */ 570 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 571 #define _PAGE_RES0 0x800 /* bit must be zero */ 572 573 #define SK_C (0x1 << 1) 574 #define SK_R (0x1 << 2) 575 #define SK_F (0x1 << 3) 576 #define SK_ACC_MASK (0xf << 4) 577 578 /* SIGP order codes */ 579 #define SIGP_SENSE 0x01 580 #define SIGP_EXTERNAL_CALL 0x02 581 #define SIGP_EMERGENCY 0x03 582 #define SIGP_START 0x04 583 #define SIGP_STOP 0x05 584 #define SIGP_RESTART 0x06 585 #define SIGP_STOP_STORE_STATUS 0x09 586 #define SIGP_INITIAL_CPU_RESET 0x0b 587 #define SIGP_CPU_RESET 0x0c 588 #define SIGP_SET_PREFIX 0x0d 589 #define SIGP_STORE_STATUS_ADDR 0x0e 590 #define SIGP_SET_ARCH 0x12 591 #define SIGP_COND_EMERGENCY 0x13 592 #define SIGP_SENSE_RUNNING 0x15 593 #define SIGP_STORE_ADTL_STATUS 0x17 594 595 /* SIGP condition codes */ 596 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 597 #define SIGP_CC_STATUS_STORED 1 598 #define SIGP_CC_BUSY 2 599 #define SIGP_CC_NOT_OPERATIONAL 3 600 601 /* SIGP status bits */ 602 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 603 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 604 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 605 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 606 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 607 #define SIGP_STAT_STOPPED 0x00000040UL 608 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 609 #define SIGP_STAT_CHECK_STOP 0x00000010UL 610 #define SIGP_STAT_INOPERATIVE 0x00000004UL 611 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 612 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 613 614 /* SIGP SET ARCHITECTURE modes */ 615 #define SIGP_MODE_ESA_S390 0 616 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 617 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 618 619 /* SIGP order code mask corresponding to bit positions 56-63 */ 620 #define SIGP_ORDER_MASK 0x000000ff 621 622 /* from s390-virtio-ccw */ 623 #define MEM_SECTION_SIZE 0x10000000UL 624 #define MAX_AVAIL_SLOTS 32 625 626 /* machine check interruption code */ 627 628 /* subclasses */ 629 #define MCIC_SC_SD 0x8000000000000000ULL 630 #define MCIC_SC_PD 0x4000000000000000ULL 631 #define MCIC_SC_SR 0x2000000000000000ULL 632 #define MCIC_SC_CD 0x0800000000000000ULL 633 #define MCIC_SC_ED 0x0400000000000000ULL 634 #define MCIC_SC_DG 0x0100000000000000ULL 635 #define MCIC_SC_W 0x0080000000000000ULL 636 #define MCIC_SC_CP 0x0040000000000000ULL 637 #define MCIC_SC_SP 0x0020000000000000ULL 638 #define MCIC_SC_CK 0x0010000000000000ULL 639 640 /* subclass modifiers */ 641 #define MCIC_SCM_B 0x0002000000000000ULL 642 #define MCIC_SCM_DA 0x0000000020000000ULL 643 #define MCIC_SCM_AP 0x0000000000080000ULL 644 645 /* storage errors */ 646 #define MCIC_SE_SE 0x0000800000000000ULL 647 #define MCIC_SE_SC 0x0000400000000000ULL 648 #define MCIC_SE_KE 0x0000200000000000ULL 649 #define MCIC_SE_DS 0x0000100000000000ULL 650 #define MCIC_SE_IE 0x0000000080000000ULL 651 652 /* validity bits */ 653 #define MCIC_VB_WP 0x0000080000000000ULL 654 #define MCIC_VB_MS 0x0000040000000000ULL 655 #define MCIC_VB_PM 0x0000020000000000ULL 656 #define MCIC_VB_IA 0x0000010000000000ULL 657 #define MCIC_VB_FA 0x0000008000000000ULL 658 #define MCIC_VB_VR 0x0000004000000000ULL 659 #define MCIC_VB_EC 0x0000002000000000ULL 660 #define MCIC_VB_FP 0x0000001000000000ULL 661 #define MCIC_VB_GR 0x0000000800000000ULL 662 #define MCIC_VB_CR 0x0000000400000000ULL 663 #define MCIC_VB_ST 0x0000000100000000ULL 664 #define MCIC_VB_AR 0x0000000040000000ULL 665 #define MCIC_VB_GS 0x0000000008000000ULL 666 #define MCIC_VB_PR 0x0000000000200000ULL 667 #define MCIC_VB_FC 0x0000000000100000ULL 668 #define MCIC_VB_CT 0x0000000000020000ULL 669 #define MCIC_VB_CC 0x0000000000010000ULL 670 671 static inline uint64_t s390_build_validity_mcic(void) 672 { 673 uint64_t mcic; 674 675 /* 676 * Indicate all validity bits (no damage) only. Other bits have to be 677 * added by the caller. (storage errors, subclasses and subclass modifiers) 678 */ 679 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 680 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 681 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 682 if (s390_has_feat(S390_FEAT_VECTOR)) { 683 mcic |= MCIC_VB_VR; 684 } 685 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 686 mcic |= MCIC_VB_GS; 687 } 688 return mcic; 689 } 690 691 692 /* cpu.c */ 693 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low); 694 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low); 695 void s390_crypto_reset(void); 696 bool s390_get_squash_mcss(void); 697 int s390_get_memslot_count(void); 698 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 699 void s390_cmma_reset(void); 700 void s390_enable_css_support(S390CPU *cpu); 701 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 702 int vq, bool assign); 703 #ifndef CONFIG_USER_ONLY 704 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 705 #else 706 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 707 { 708 return 0; 709 } 710 #endif /* CONFIG_USER_ONLY */ 711 712 713 /* cpu_models.c */ 714 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); 715 #define cpu_list s390_cpu_list 716 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 717 const S390FeatInit feat_init); 718 719 720 /* helper.c */ 721 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model) 722 723 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 724 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 725 726 /* you can call this signal handler from your SIGBUS and SIGSEGV 727 signal handlers to inform the virtual CPU of exceptions. non zero 728 is returned if the signal was handled by the virtual CPU. */ 729 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 730 #define cpu_signal_handler cpu_s390x_signal_handler 731 732 733 /* interrupt.c */ 734 void s390_crw_mchk(void); 735 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 736 uint32_t io_int_parm, uint32_t io_int_word); 737 /* automatically detect the instruction length */ 738 #define ILEN_AUTO 0xff 739 #define RA_IGNORED 0 740 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, 741 uintptr_t ra); 742 /* service interrupts are floating therefore we must not pass an cpustate */ 743 void s390_sclp_extint(uint32_t parm); 744 /* FIXME: remove once we have proper floating interrupts in TCG */ 745 void cpu_inject_service(S390CPU *cpu, uint32_t param); 746 void cpu_inject_crw_mchk(S390CPU *cpu); 747 void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id, 748 uint16_t subchannel_number, uint32_t io_int_parm, 749 uint32_t io_int_word); 750 751 /* mmu_helper.c */ 752 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 753 int len, bool is_write); 754 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 755 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 756 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 757 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 758 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 759 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 760 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 761 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 762 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 763 764 765 /* sigp.c */ 766 int s390_cpu_restart(S390CPU *cpu); 767 void s390_init_sigp(void); 768 769 770 /* outside of target/s390x/ */ 771 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 772 773 #endif 774