1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 35 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 36 37 #define TARGET_INSN_START_EXTRA_WORDS 2 38 39 #define MMU_USER_IDX 0 40 41 #define S390_MAX_CPUS 248 42 43 typedef struct PSW { 44 uint64_t mask; 45 uint64_t addr; 46 } PSW; 47 48 struct CPUS390XState { 49 uint64_t regs[16]; /* GP registers */ 50 /* 51 * The floating point registers are part of the vector registers. 52 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 53 */ 54 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 55 uint32_t aregs[16]; /* access registers */ 56 uint64_t gscb[4]; /* guarded storage control */ 57 uint64_t etoken; /* etoken */ 58 uint64_t etoken_extension; /* etoken extension */ 59 60 /* Fields up to this point are not cleared by initial CPU reset */ 61 struct {} start_initial_reset_fields; 62 63 uint32_t fpc; /* floating-point control register */ 64 uint32_t cc_op; 65 bool bpbc; /* branch prediction blocking */ 66 67 float_status fpu_status; /* passed to softfloat lib */ 68 69 /* The low part of a 128-bit return, or remainder of a divide. */ 70 uint64_t retxl; 71 72 PSW psw; 73 74 S390CrashReason crash_reason; 75 76 uint64_t cc_src; 77 uint64_t cc_dst; 78 uint64_t cc_vr; 79 80 uint64_t ex_value; 81 82 uint64_t __excp_addr; 83 uint64_t psa; 84 85 uint32_t int_pgm_code; 86 uint32_t int_pgm_ilen; 87 88 uint32_t int_svc_code; 89 uint32_t int_svc_ilen; 90 91 uint64_t per_address; 92 uint16_t per_perc_atmid; 93 94 uint64_t cregs[16]; /* control registers */ 95 96 uint64_t ckc; 97 uint64_t cputm; 98 uint32_t todpr; 99 100 uint64_t pfault_token; 101 uint64_t pfault_compare; 102 uint64_t pfault_select; 103 104 uint64_t gbea; 105 uint64_t pp; 106 107 /* Fields up to this point are not cleared by normal CPU reset */ 108 struct {} start_normal_reset_fields; 109 uint8_t riccb[64]; /* runtime instrumentation control */ 110 111 int pending_int; 112 uint16_t external_call_addr; 113 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 114 115 /* Fields up to this point are cleared by a CPU reset */ 116 struct {} end_reset_fields; 117 118 #if !defined(CONFIG_USER_ONLY) 119 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 120 uint64_t cpuid; 121 #endif 122 123 QEMUTimer *tod_timer; 124 125 QEMUTimer *cpu_timer; 126 127 /* 128 * The cpu state represents the logical state of a cpu. In contrast to other 129 * architectures, there is a difference between a halt and a stop on s390. 130 * If all cpus are either stopped (including check stop) or in the disabled 131 * wait state, the vm can be shut down. 132 * The acceptable cpu_state values are defined in the CpuInfoS390State 133 * enum. 134 */ 135 uint8_t cpu_state; 136 137 /* currently processed sigp order */ 138 uint8_t sigp_order; 139 140 }; 141 142 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 143 { 144 return &cs->vregs[nr][0]; 145 } 146 147 /** 148 * S390CPU: 149 * @env: #CPUS390XState. 150 * 151 * An S/390 CPU. 152 */ 153 struct S390CPU { 154 /*< private >*/ 155 CPUState parent_obj; 156 /*< public >*/ 157 158 CPUNegativeOffsetState neg; 159 CPUS390XState env; 160 S390CPUModel *model; 161 /* needed for live migration */ 162 void *irqstate; 163 uint32_t irqstate_saved_size; 164 }; 165 166 167 #ifndef CONFIG_USER_ONLY 168 extern const VMStateDescription vmstate_s390_cpu; 169 #endif 170 171 /* distinguish between 24 bit and 31 bit addressing */ 172 #define HIGH_ORDER_BIT 0x80000000 173 174 /* Interrupt Codes */ 175 /* Program Interrupts */ 176 #define PGM_OPERATION 0x0001 177 #define PGM_PRIVILEGED 0x0002 178 #define PGM_EXECUTE 0x0003 179 #define PGM_PROTECTION 0x0004 180 #define PGM_ADDRESSING 0x0005 181 #define PGM_SPECIFICATION 0x0006 182 #define PGM_DATA 0x0007 183 #define PGM_FIXPT_OVERFLOW 0x0008 184 #define PGM_FIXPT_DIVIDE 0x0009 185 #define PGM_DEC_OVERFLOW 0x000a 186 #define PGM_DEC_DIVIDE 0x000b 187 #define PGM_HFP_EXP_OVERFLOW 0x000c 188 #define PGM_HFP_EXP_UNDERFLOW 0x000d 189 #define PGM_HFP_SIGNIFICANCE 0x000e 190 #define PGM_HFP_DIVIDE 0x000f 191 #define PGM_SEGMENT_TRANS 0x0010 192 #define PGM_PAGE_TRANS 0x0011 193 #define PGM_TRANS_SPEC 0x0012 194 #define PGM_SPECIAL_OP 0x0013 195 #define PGM_OPERAND 0x0015 196 #define PGM_TRACE_TABLE 0x0016 197 #define PGM_VECTOR_PROCESSING 0x001b 198 #define PGM_SPACE_SWITCH 0x001c 199 #define PGM_HFP_SQRT 0x001d 200 #define PGM_PC_TRANS_SPEC 0x001f 201 #define PGM_AFX_TRANS 0x0020 202 #define PGM_ASX_TRANS 0x0021 203 #define PGM_LX_TRANS 0x0022 204 #define PGM_EX_TRANS 0x0023 205 #define PGM_PRIM_AUTH 0x0024 206 #define PGM_SEC_AUTH 0x0025 207 #define PGM_ALET_SPEC 0x0028 208 #define PGM_ALEN_SPEC 0x0029 209 #define PGM_ALE_SEQ 0x002a 210 #define PGM_ASTE_VALID 0x002b 211 #define PGM_ASTE_SEQ 0x002c 212 #define PGM_EXT_AUTH 0x002d 213 #define PGM_STACK_FULL 0x0030 214 #define PGM_STACK_EMPTY 0x0031 215 #define PGM_STACK_SPEC 0x0032 216 #define PGM_STACK_TYPE 0x0033 217 #define PGM_STACK_OP 0x0034 218 #define PGM_ASCE_TYPE 0x0038 219 #define PGM_REG_FIRST_TRANS 0x0039 220 #define PGM_REG_SEC_TRANS 0x003a 221 #define PGM_REG_THIRD_TRANS 0x003b 222 #define PGM_MONITOR 0x0040 223 #define PGM_PER 0x0080 224 #define PGM_CRYPTO 0x0119 225 226 /* External Interrupts */ 227 #define EXT_INTERRUPT_KEY 0x0040 228 #define EXT_CLOCK_COMP 0x1004 229 #define EXT_CPU_TIMER 0x1005 230 #define EXT_MALFUNCTION 0x1200 231 #define EXT_EMERGENCY 0x1201 232 #define EXT_EXTERNAL_CALL 0x1202 233 #define EXT_ETR 0x1406 234 #define EXT_SERVICE 0x2401 235 #define EXT_VIRTIO 0x2603 236 237 /* PSW defines */ 238 #undef PSW_MASK_PER 239 #undef PSW_MASK_UNUSED_2 240 #undef PSW_MASK_UNUSED_3 241 #undef PSW_MASK_DAT 242 #undef PSW_MASK_IO 243 #undef PSW_MASK_EXT 244 #undef PSW_MASK_KEY 245 #undef PSW_SHIFT_KEY 246 #undef PSW_MASK_MCHECK 247 #undef PSW_MASK_WAIT 248 #undef PSW_MASK_PSTATE 249 #undef PSW_MASK_ASC 250 #undef PSW_SHIFT_ASC 251 #undef PSW_MASK_CC 252 #undef PSW_MASK_PM 253 #undef PSW_MASK_RI 254 #undef PSW_SHIFT_MASK_PM 255 #undef PSW_MASK_64 256 #undef PSW_MASK_32 257 #undef PSW_MASK_ESA_ADDR 258 259 #define PSW_MASK_PER 0x4000000000000000ULL 260 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 261 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 262 #define PSW_MASK_DAT 0x0400000000000000ULL 263 #define PSW_MASK_IO 0x0200000000000000ULL 264 #define PSW_MASK_EXT 0x0100000000000000ULL 265 #define PSW_MASK_KEY 0x00F0000000000000ULL 266 #define PSW_SHIFT_KEY 52 267 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 268 #define PSW_MASK_MCHECK 0x0004000000000000ULL 269 #define PSW_MASK_WAIT 0x0002000000000000ULL 270 #define PSW_MASK_PSTATE 0x0001000000000000ULL 271 #define PSW_MASK_ASC 0x0000C00000000000ULL 272 #define PSW_SHIFT_ASC 46 273 #define PSW_MASK_CC 0x0000300000000000ULL 274 #define PSW_MASK_PM 0x00000F0000000000ULL 275 #define PSW_SHIFT_MASK_PM 40 276 #define PSW_MASK_RI 0x0000008000000000ULL 277 #define PSW_MASK_64 0x0000000100000000ULL 278 #define PSW_MASK_32 0x0000000080000000ULL 279 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 280 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 281 282 #undef PSW_ASC_PRIMARY 283 #undef PSW_ASC_ACCREG 284 #undef PSW_ASC_SECONDARY 285 #undef PSW_ASC_HOME 286 287 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 288 #define PSW_ASC_ACCREG 0x0000400000000000ULL 289 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 290 #define PSW_ASC_HOME 0x0000C00000000000ULL 291 292 /* the address space values shifted */ 293 #define AS_PRIMARY 0 294 #define AS_ACCREG 1 295 #define AS_SECONDARY 2 296 #define AS_HOME 3 297 298 /* tb flags */ 299 300 #define FLAG_MASK_PSW_SHIFT 31 301 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 302 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 303 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 304 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 305 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 306 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 307 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 308 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 309 310 /* we'll use some unused PSW positions to store CR flags in tb flags */ 311 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 312 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 313 314 /* Control register 0 bits */ 315 #define CR0_LOWPROT 0x0000000010000000ULL 316 #define CR0_SECONDARY 0x0000000004000000ULL 317 #define CR0_EDAT 0x0000000000800000ULL 318 #define CR0_AFP 0x0000000000040000ULL 319 #define CR0_VECTOR 0x0000000000020000ULL 320 #define CR0_IEP 0x0000000000100000ULL 321 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 322 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 323 #define CR0_CKC_SC 0x0000000000000800ULL 324 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 325 #define CR0_SERVICE_SC 0x0000000000000200ULL 326 327 /* Control register 14 bits */ 328 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 329 330 /* MMU */ 331 #define MMU_PRIMARY_IDX 0 332 #define MMU_SECONDARY_IDX 1 333 #define MMU_HOME_IDX 2 334 #define MMU_REAL_IDX 3 335 336 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 337 { 338 #ifdef CONFIG_USER_ONLY 339 return MMU_USER_IDX; 340 #else 341 if (!(env->psw.mask & PSW_MASK_DAT)) { 342 return MMU_REAL_IDX; 343 } 344 345 if (ifetch) { 346 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 347 return MMU_HOME_IDX; 348 } 349 return MMU_PRIMARY_IDX; 350 } 351 352 switch (env->psw.mask & PSW_MASK_ASC) { 353 case PSW_ASC_PRIMARY: 354 return MMU_PRIMARY_IDX; 355 case PSW_ASC_SECONDARY: 356 return MMU_SECONDARY_IDX; 357 case PSW_ASC_HOME: 358 return MMU_HOME_IDX; 359 case PSW_ASC_ACCREG: 360 /* Fallthrough: access register mode is not yet supported */ 361 default: 362 abort(); 363 } 364 #endif 365 } 366 367 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 368 target_ulong *cs_base, uint32_t *flags) 369 { 370 *pc = env->psw.addr; 371 *cs_base = env->ex_value; 372 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 373 if (env->cregs[0] & CR0_AFP) { 374 *flags |= FLAG_MASK_AFP; 375 } 376 if (env->cregs[0] & CR0_VECTOR) { 377 *flags |= FLAG_MASK_VECTOR; 378 } 379 } 380 381 /* PER bits from control register 9 */ 382 #define PER_CR9_EVENT_BRANCH 0x80000000 383 #define PER_CR9_EVENT_IFETCH 0x40000000 384 #define PER_CR9_EVENT_STORE 0x20000000 385 #define PER_CR9_EVENT_STORE_REAL 0x08000000 386 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 387 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 388 #define PER_CR9_CONTROL_ALTERATION 0x00200000 389 390 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 391 #define PER_CODE_EVENT_BRANCH 0x8000 392 #define PER_CODE_EVENT_IFETCH 0x4000 393 #define PER_CODE_EVENT_STORE 0x2000 394 #define PER_CODE_EVENT_STORE_REAL 0x0800 395 #define PER_CODE_EVENT_NULLIFICATION 0x0100 396 397 #define EXCP_EXT 1 /* external interrupt */ 398 #define EXCP_SVC 2 /* supervisor call (syscall) */ 399 #define EXCP_PGM 3 /* program interruption */ 400 #define EXCP_RESTART 4 /* restart interrupt */ 401 #define EXCP_STOP 5 /* stop interrupt */ 402 #define EXCP_IO 7 /* I/O interrupt */ 403 #define EXCP_MCHK 8 /* machine check */ 404 405 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 406 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 407 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 408 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 409 #define INTERRUPT_RESTART (1 << 7) 410 #define INTERRUPT_STOP (1 << 8) 411 412 /* Program Status Word. */ 413 #define S390_PSWM_REGNUM 0 414 #define S390_PSWA_REGNUM 1 415 /* General Purpose Registers. */ 416 #define S390_R0_REGNUM 2 417 #define S390_R1_REGNUM 3 418 #define S390_R2_REGNUM 4 419 #define S390_R3_REGNUM 5 420 #define S390_R4_REGNUM 6 421 #define S390_R5_REGNUM 7 422 #define S390_R6_REGNUM 8 423 #define S390_R7_REGNUM 9 424 #define S390_R8_REGNUM 10 425 #define S390_R9_REGNUM 11 426 #define S390_R10_REGNUM 12 427 #define S390_R11_REGNUM 13 428 #define S390_R12_REGNUM 14 429 #define S390_R13_REGNUM 15 430 #define S390_R14_REGNUM 16 431 #define S390_R15_REGNUM 17 432 /* Total Core Registers. */ 433 #define S390_NUM_CORE_REGS 18 434 435 static inline void setcc(S390CPU *cpu, uint64_t cc) 436 { 437 CPUS390XState *env = &cpu->env; 438 439 env->psw.mask &= ~(3ull << 44); 440 env->psw.mask |= (cc & 3) << 44; 441 env->cc_op = cc; 442 } 443 444 /* STSI */ 445 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 446 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 447 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 448 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 449 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 450 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 451 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 452 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 453 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 454 455 /* Basic Machine Configuration */ 456 typedef struct SysIB_111 { 457 uint8_t res1[32]; 458 uint8_t manuf[16]; 459 uint8_t type[4]; 460 uint8_t res2[12]; 461 uint8_t model[16]; 462 uint8_t sequence[16]; 463 uint8_t plant[4]; 464 uint8_t res3[3996]; 465 } SysIB_111; 466 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 467 468 /* Basic Machine CPU */ 469 typedef struct SysIB_121 { 470 uint8_t res1[80]; 471 uint8_t sequence[16]; 472 uint8_t plant[4]; 473 uint8_t res2[2]; 474 uint16_t cpu_addr; 475 uint8_t res3[3992]; 476 } SysIB_121; 477 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 478 479 /* Basic Machine CPUs */ 480 typedef struct SysIB_122 { 481 uint8_t res1[32]; 482 uint32_t capability; 483 uint16_t total_cpus; 484 uint16_t conf_cpus; 485 uint16_t standby_cpus; 486 uint16_t reserved_cpus; 487 uint16_t adjustments[2026]; 488 } SysIB_122; 489 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 490 491 /* LPAR CPU */ 492 typedef struct SysIB_221 { 493 uint8_t res1[80]; 494 uint8_t sequence[16]; 495 uint8_t plant[4]; 496 uint16_t cpu_id; 497 uint16_t cpu_addr; 498 uint8_t res3[3992]; 499 } SysIB_221; 500 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 501 502 /* LPAR CPUs */ 503 typedef struct SysIB_222 { 504 uint8_t res1[32]; 505 uint16_t lpar_num; 506 uint8_t res2; 507 uint8_t lcpuc; 508 uint16_t total_cpus; 509 uint16_t conf_cpus; 510 uint16_t standby_cpus; 511 uint16_t reserved_cpus; 512 uint8_t name[8]; 513 uint32_t caf; 514 uint8_t res3[16]; 515 uint16_t dedicated_cpus; 516 uint16_t shared_cpus; 517 uint8_t res4[4020]; 518 } SysIB_222; 519 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 520 521 /* VM CPUs */ 522 typedef struct SysIB_322 { 523 uint8_t res1[31]; 524 uint8_t count; 525 struct { 526 uint8_t res2[4]; 527 uint16_t total_cpus; 528 uint16_t conf_cpus; 529 uint16_t standby_cpus; 530 uint16_t reserved_cpus; 531 uint8_t name[8]; 532 uint32_t caf; 533 uint8_t cpi[16]; 534 uint8_t res5[3]; 535 uint8_t ext_name_encoding; 536 uint32_t res3; 537 uint8_t uuid[16]; 538 } vm[8]; 539 uint8_t res4[1504]; 540 uint8_t ext_names[8][256]; 541 } SysIB_322; 542 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 543 544 typedef union SysIB { 545 SysIB_111 sysib_111; 546 SysIB_121 sysib_121; 547 SysIB_122 sysib_122; 548 SysIB_221 sysib_221; 549 SysIB_222 sysib_222; 550 SysIB_322 sysib_322; 551 } SysIB; 552 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 553 554 /* MMU defines */ 555 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 556 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 557 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 558 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 559 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 560 #define ASCE_REAL_SPACE 0x20 /* real space control */ 561 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 562 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 563 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 564 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 565 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 566 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 567 568 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 569 #define REGION_ENTRY_P 0x0000000000000200ULL 570 #define REGION_ENTRY_TF 0x00000000000000c0ULL 571 #define REGION_ENTRY_I 0x0000000000000020ULL 572 #define REGION_ENTRY_TT 0x000000000000000cULL 573 #define REGION_ENTRY_TL 0x0000000000000003ULL 574 575 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 576 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 577 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 578 579 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 580 #define REGION3_ENTRY_AV 0x0000000000010000ULL 581 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 582 #define REGION3_ENTRY_F 0x0000000000000800ULL 583 #define REGION3_ENTRY_FC 0x0000000000000400ULL 584 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 585 #define REGION3_ENTRY_CR 0x0000000000000010ULL 586 587 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 588 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 589 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 590 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 591 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 592 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 593 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 594 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 595 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 596 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 597 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 598 599 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 600 601 #define PAGE_ENTRY_0 0x0000000000000800ULL 602 #define PAGE_ENTRY_I 0x0000000000000400ULL 603 #define PAGE_ENTRY_P 0x0000000000000200ULL 604 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 605 606 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 607 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 608 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 609 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 610 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 611 612 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 613 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 614 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 615 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 616 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 617 618 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 619 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 620 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 621 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 622 623 #define SK_C (0x1 << 1) 624 #define SK_R (0x1 << 2) 625 #define SK_F (0x1 << 3) 626 #define SK_ACC_MASK (0xf << 4) 627 628 /* SIGP order codes */ 629 #define SIGP_SENSE 0x01 630 #define SIGP_EXTERNAL_CALL 0x02 631 #define SIGP_EMERGENCY 0x03 632 #define SIGP_START 0x04 633 #define SIGP_STOP 0x05 634 #define SIGP_RESTART 0x06 635 #define SIGP_STOP_STORE_STATUS 0x09 636 #define SIGP_INITIAL_CPU_RESET 0x0b 637 #define SIGP_CPU_RESET 0x0c 638 #define SIGP_SET_PREFIX 0x0d 639 #define SIGP_STORE_STATUS_ADDR 0x0e 640 #define SIGP_SET_ARCH 0x12 641 #define SIGP_COND_EMERGENCY 0x13 642 #define SIGP_SENSE_RUNNING 0x15 643 #define SIGP_STORE_ADTL_STATUS 0x17 644 645 /* SIGP condition codes */ 646 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 647 #define SIGP_CC_STATUS_STORED 1 648 #define SIGP_CC_BUSY 2 649 #define SIGP_CC_NOT_OPERATIONAL 3 650 651 /* SIGP status bits */ 652 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 653 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 654 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 655 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 656 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 657 #define SIGP_STAT_STOPPED 0x00000040UL 658 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 659 #define SIGP_STAT_CHECK_STOP 0x00000010UL 660 #define SIGP_STAT_INOPERATIVE 0x00000004UL 661 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 662 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 663 664 /* SIGP SET ARCHITECTURE modes */ 665 #define SIGP_MODE_ESA_S390 0 666 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 667 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 668 669 /* SIGP order code mask corresponding to bit positions 56-63 */ 670 #define SIGP_ORDER_MASK 0x000000ff 671 672 /* machine check interruption code */ 673 674 /* subclasses */ 675 #define MCIC_SC_SD 0x8000000000000000ULL 676 #define MCIC_SC_PD 0x4000000000000000ULL 677 #define MCIC_SC_SR 0x2000000000000000ULL 678 #define MCIC_SC_CD 0x0800000000000000ULL 679 #define MCIC_SC_ED 0x0400000000000000ULL 680 #define MCIC_SC_DG 0x0100000000000000ULL 681 #define MCIC_SC_W 0x0080000000000000ULL 682 #define MCIC_SC_CP 0x0040000000000000ULL 683 #define MCIC_SC_SP 0x0020000000000000ULL 684 #define MCIC_SC_CK 0x0010000000000000ULL 685 686 /* subclass modifiers */ 687 #define MCIC_SCM_B 0x0002000000000000ULL 688 #define MCIC_SCM_DA 0x0000000020000000ULL 689 #define MCIC_SCM_AP 0x0000000000080000ULL 690 691 /* storage errors */ 692 #define MCIC_SE_SE 0x0000800000000000ULL 693 #define MCIC_SE_SC 0x0000400000000000ULL 694 #define MCIC_SE_KE 0x0000200000000000ULL 695 #define MCIC_SE_DS 0x0000100000000000ULL 696 #define MCIC_SE_IE 0x0000000080000000ULL 697 698 /* validity bits */ 699 #define MCIC_VB_WP 0x0000080000000000ULL 700 #define MCIC_VB_MS 0x0000040000000000ULL 701 #define MCIC_VB_PM 0x0000020000000000ULL 702 #define MCIC_VB_IA 0x0000010000000000ULL 703 #define MCIC_VB_FA 0x0000008000000000ULL 704 #define MCIC_VB_VR 0x0000004000000000ULL 705 #define MCIC_VB_EC 0x0000002000000000ULL 706 #define MCIC_VB_FP 0x0000001000000000ULL 707 #define MCIC_VB_GR 0x0000000800000000ULL 708 #define MCIC_VB_CR 0x0000000400000000ULL 709 #define MCIC_VB_ST 0x0000000100000000ULL 710 #define MCIC_VB_AR 0x0000000040000000ULL 711 #define MCIC_VB_GS 0x0000000008000000ULL 712 #define MCIC_VB_PR 0x0000000000200000ULL 713 #define MCIC_VB_FC 0x0000000000100000ULL 714 #define MCIC_VB_CT 0x0000000000020000ULL 715 #define MCIC_VB_CC 0x0000000000010000ULL 716 717 static inline uint64_t s390_build_validity_mcic(void) 718 { 719 uint64_t mcic; 720 721 /* 722 * Indicate all validity bits (no damage) only. Other bits have to be 723 * added by the caller. (storage errors, subclasses and subclass modifiers) 724 */ 725 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 726 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 727 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 728 if (s390_has_feat(S390_FEAT_VECTOR)) { 729 mcic |= MCIC_VB_VR; 730 } 731 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 732 mcic |= MCIC_VB_GS; 733 } 734 return mcic; 735 } 736 737 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 738 { 739 cpu_reset(cs); 740 } 741 742 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 743 { 744 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 745 746 scc->reset(cs, S390_CPU_RESET_NORMAL); 747 } 748 749 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 750 { 751 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 752 753 scc->reset(cs, S390_CPU_RESET_INITIAL); 754 } 755 756 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 757 { 758 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 759 760 scc->load_normal(cs); 761 } 762 763 764 /* cpu.c */ 765 void s390_crypto_reset(void); 766 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 767 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 768 void s390_cmma_reset(void); 769 void s390_enable_css_support(S390CPU *cpu); 770 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 771 int vq, bool assign); 772 #ifndef CONFIG_USER_ONLY 773 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 774 #else 775 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 776 { 777 return 0; 778 } 779 #endif /* CONFIG_USER_ONLY */ 780 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 781 { 782 return cpu->env.cpu_state; 783 } 784 785 786 /* cpu_models.c */ 787 void s390_cpu_list(void); 788 #define cpu_list s390_cpu_list 789 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 790 const S390FeatInit feat_init); 791 792 793 /* helper.c */ 794 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 795 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 796 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 797 798 /* you can call this signal handler from your SIGBUS and SIGSEGV 799 signal handlers to inform the virtual CPU of exceptions. non zero 800 is returned if the signal was handled by the virtual CPU. */ 801 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 802 #define cpu_signal_handler cpu_s390x_signal_handler 803 804 805 /* interrupt.c */ 806 void s390_crw_mchk(void); 807 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 808 uint32_t io_int_parm, uint32_t io_int_word); 809 #define RA_IGNORED 0 810 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 811 /* service interrupts are floating therefore we must not pass an cpustate */ 812 void s390_sclp_extint(uint32_t parm); 813 814 /* mmu_helper.c */ 815 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 816 int len, bool is_write); 817 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 818 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 819 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 820 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 821 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 822 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 823 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 824 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 825 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 826 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 827 int len, bool is_write); 828 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 829 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 830 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 831 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 832 833 /* sigp.c */ 834 int s390_cpu_restart(S390CPU *cpu); 835 void s390_init_sigp(void); 836 837 838 /* outside of target/s390x/ */ 839 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 840 841 typedef CPUS390XState CPUArchState; 842 typedef S390CPU ArchCPU; 843 844 #include "exec/cpu-all.h" 845 846 #endif 847