1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 #include "qemu/cpu-float.h" 32 #include "tcg/tcg_s390x.h" 33 34 #define ELF_MACHINE_UNAME "S390X" 35 36 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 37 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 38 39 #define TARGET_HAS_PRECISE_SMC 40 41 #define TARGET_INSN_START_EXTRA_WORDS 2 42 43 #define MMU_USER_IDX 0 44 45 #define S390_MAX_CPUS 248 46 47 #ifndef CONFIG_KVM 48 #define S390_ADAPTER_SUPPRESSIBLE 0x01 49 #else 50 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE 51 #endif 52 53 typedef struct PSW { 54 uint64_t mask; 55 uint64_t addr; 56 } PSW; 57 58 struct CPUArchState { 59 uint64_t regs[16]; /* GP registers */ 60 /* 61 * The floating point registers are part of the vector registers. 62 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 63 */ 64 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 65 uint32_t aregs[16]; /* access registers */ 66 uint64_t gscb[4]; /* guarded storage control */ 67 uint64_t etoken; /* etoken */ 68 uint64_t etoken_extension; /* etoken extension */ 69 70 uint64_t diag318_info; 71 72 /* Fields up to this point are not cleared by initial CPU reset */ 73 struct {} start_initial_reset_fields; 74 75 uint32_t fpc; /* floating-point control register */ 76 uint32_t cc_op; 77 bool bpbc; /* branch prediction blocking */ 78 79 float_status fpu_status; /* passed to softfloat lib */ 80 81 PSW psw; 82 83 S390CrashReason crash_reason; 84 85 uint64_t cc_src; 86 uint64_t cc_dst; 87 uint64_t cc_vr; 88 89 uint64_t ex_value; 90 uint64_t ex_target; 91 92 uint64_t __excp_addr; 93 uint64_t psa; 94 95 uint32_t int_pgm_code; 96 uint32_t int_pgm_ilen; 97 98 uint32_t int_svc_code; 99 uint32_t int_svc_ilen; 100 101 uint64_t per_address; 102 uint16_t per_perc_atmid; 103 104 uint64_t cregs[16]; /* control registers */ 105 106 uint64_t ckc; 107 uint64_t cputm; 108 uint32_t todpr; 109 110 uint64_t pfault_token; 111 uint64_t pfault_compare; 112 uint64_t pfault_select; 113 114 uint64_t gbea; 115 uint64_t pp; 116 117 /* Fields up to this point are not cleared by normal CPU reset */ 118 struct {} start_normal_reset_fields; 119 uint8_t riccb[64]; /* runtime instrumentation control */ 120 121 int pending_int; 122 uint16_t external_call_addr; 123 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 124 125 #if !defined(CONFIG_USER_ONLY) 126 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 127 int tlb_fill_exc; /* exception number seen during tlb_fill */ 128 #endif 129 130 /* Fields up to this point are cleared by a CPU reset */ 131 struct {} end_reset_fields; 132 133 #if !defined(CONFIG_USER_ONLY) 134 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 135 uint64_t cpuid; 136 #endif 137 138 QEMUTimer *tod_timer; 139 140 QEMUTimer *cpu_timer; 141 142 /* 143 * The cpu state represents the logical state of a cpu. In contrast to other 144 * architectures, there is a difference between a halt and a stop on s390. 145 * If all cpus are either stopped (including check stop) or in the disabled 146 * wait state, the vm can be shut down. 147 * The acceptable cpu_state values are defined in the CpuInfoS390State 148 * enum. 149 */ 150 uint8_t cpu_state; 151 152 /* currently processed sigp order */ 153 uint8_t sigp_order; 154 155 }; 156 157 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 158 { 159 return &cs->vregs[nr][0]; 160 } 161 162 /** 163 * S390CPU: 164 * @env: #CPUS390XState. 165 * 166 * An S/390 CPU. 167 */ 168 struct ArchCPU { 169 /*< private >*/ 170 CPUState parent_obj; 171 /*< public >*/ 172 173 CPUS390XState env; 174 S390CPUModel *model; 175 /* needed for live migration */ 176 void *irqstate; 177 uint32_t irqstate_saved_size; 178 }; 179 180 181 #ifndef CONFIG_USER_ONLY 182 extern const VMStateDescription vmstate_s390_cpu; 183 #endif 184 185 /* distinguish between 24 bit and 31 bit addressing */ 186 #define HIGH_ORDER_BIT 0x80000000 187 188 /* Interrupt Codes */ 189 /* Program Interrupts */ 190 #define PGM_OPERATION 0x0001 191 #define PGM_PRIVILEGED 0x0002 192 #define PGM_EXECUTE 0x0003 193 #define PGM_PROTECTION 0x0004 194 #define PGM_ADDRESSING 0x0005 195 #define PGM_SPECIFICATION 0x0006 196 #define PGM_DATA 0x0007 197 #define PGM_FIXPT_OVERFLOW 0x0008 198 #define PGM_FIXPT_DIVIDE 0x0009 199 #define PGM_DEC_OVERFLOW 0x000a 200 #define PGM_DEC_DIVIDE 0x000b 201 #define PGM_HFP_EXP_OVERFLOW 0x000c 202 #define PGM_HFP_EXP_UNDERFLOW 0x000d 203 #define PGM_HFP_SIGNIFICANCE 0x000e 204 #define PGM_HFP_DIVIDE 0x000f 205 #define PGM_SEGMENT_TRANS 0x0010 206 #define PGM_PAGE_TRANS 0x0011 207 #define PGM_TRANS_SPEC 0x0012 208 #define PGM_SPECIAL_OP 0x0013 209 #define PGM_OPERAND 0x0015 210 #define PGM_TRACE_TABLE 0x0016 211 #define PGM_VECTOR_PROCESSING 0x001b 212 #define PGM_SPACE_SWITCH 0x001c 213 #define PGM_HFP_SQRT 0x001d 214 #define PGM_PC_TRANS_SPEC 0x001f 215 #define PGM_AFX_TRANS 0x0020 216 #define PGM_ASX_TRANS 0x0021 217 #define PGM_LX_TRANS 0x0022 218 #define PGM_EX_TRANS 0x0023 219 #define PGM_PRIM_AUTH 0x0024 220 #define PGM_SEC_AUTH 0x0025 221 #define PGM_ALET_SPEC 0x0028 222 #define PGM_ALEN_SPEC 0x0029 223 #define PGM_ALE_SEQ 0x002a 224 #define PGM_ASTE_VALID 0x002b 225 #define PGM_ASTE_SEQ 0x002c 226 #define PGM_EXT_AUTH 0x002d 227 #define PGM_STACK_FULL 0x0030 228 #define PGM_STACK_EMPTY 0x0031 229 #define PGM_STACK_SPEC 0x0032 230 #define PGM_STACK_TYPE 0x0033 231 #define PGM_STACK_OP 0x0034 232 #define PGM_ASCE_TYPE 0x0038 233 #define PGM_REG_FIRST_TRANS 0x0039 234 #define PGM_REG_SEC_TRANS 0x003a 235 #define PGM_REG_THIRD_TRANS 0x003b 236 #define PGM_MONITOR 0x0040 237 #define PGM_PER 0x0080 238 #define PGM_CRYPTO 0x0119 239 240 /* External Interrupts */ 241 #define EXT_INTERRUPT_KEY 0x0040 242 #define EXT_CLOCK_COMP 0x1004 243 #define EXT_CPU_TIMER 0x1005 244 #define EXT_MALFUNCTION 0x1200 245 #define EXT_EMERGENCY 0x1201 246 #define EXT_EXTERNAL_CALL 0x1202 247 #define EXT_ETR 0x1406 248 #define EXT_SERVICE 0x2401 249 #define EXT_VIRTIO 0x2603 250 251 /* PSW defines */ 252 #undef PSW_MASK_PER 253 #undef PSW_MASK_UNUSED_2 254 #undef PSW_MASK_UNUSED_3 255 #undef PSW_MASK_DAT 256 #undef PSW_MASK_IO 257 #undef PSW_MASK_EXT 258 #undef PSW_MASK_KEY 259 #undef PSW_SHIFT_KEY 260 #undef PSW_MASK_MCHECK 261 #undef PSW_MASK_WAIT 262 #undef PSW_MASK_PSTATE 263 #undef PSW_MASK_ASC 264 #undef PSW_SHIFT_ASC 265 #undef PSW_MASK_CC 266 #undef PSW_MASK_PM 267 #undef PSW_MASK_RI 268 #undef PSW_SHIFT_MASK_PM 269 #undef PSW_MASK_64 270 #undef PSW_MASK_32 271 #undef PSW_MASK_ESA_ADDR 272 273 #define PSW_MASK_PER 0x4000000000000000ULL 274 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 275 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 276 #define PSW_MASK_DAT 0x0400000000000000ULL 277 #define PSW_MASK_IO 0x0200000000000000ULL 278 #define PSW_MASK_EXT 0x0100000000000000ULL 279 #define PSW_MASK_KEY 0x00F0000000000000ULL 280 #define PSW_SHIFT_KEY 52 281 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 282 #define PSW_MASK_MCHECK 0x0004000000000000ULL 283 #define PSW_MASK_WAIT 0x0002000000000000ULL 284 #define PSW_MASK_PSTATE 0x0001000000000000ULL 285 #define PSW_MASK_ASC 0x0000C00000000000ULL 286 #define PSW_SHIFT_ASC 46 287 #define PSW_MASK_CC 0x0000300000000000ULL 288 #define PSW_MASK_PM 0x00000F0000000000ULL 289 #define PSW_SHIFT_MASK_PM 40 290 #define PSW_MASK_RI 0x0000008000000000ULL 291 #define PSW_MASK_64 0x0000000100000000ULL 292 #define PSW_MASK_32 0x0000000080000000ULL 293 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 294 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 295 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL 296 297 #undef PSW_ASC_PRIMARY 298 #undef PSW_ASC_ACCREG 299 #undef PSW_ASC_SECONDARY 300 #undef PSW_ASC_HOME 301 302 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 303 #define PSW_ASC_ACCREG 0x0000400000000000ULL 304 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 305 #define PSW_ASC_HOME 0x0000C00000000000ULL 306 307 /* the address space values shifted */ 308 #define AS_PRIMARY 0 309 #define AS_ACCREG 1 310 #define AS_SECONDARY 2 311 #define AS_HOME 3 312 313 /* tb flags */ 314 315 #define FLAG_MASK_PSW_SHIFT 31 316 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 317 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 318 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 319 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 320 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 321 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 322 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 323 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 324 325 /* we'll use some unused PSW positions to store CR flags in tb flags */ 326 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 327 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 328 329 /* Control register 0 bits */ 330 #define CR0_LOWPROT 0x0000000010000000ULL 331 #define CR0_SECONDARY 0x0000000004000000ULL 332 #define CR0_EDAT 0x0000000000800000ULL 333 #define CR0_AFP 0x0000000000040000ULL 334 #define CR0_VECTOR 0x0000000000020000ULL 335 #define CR0_IEP 0x0000000000100000ULL 336 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 337 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 338 #define CR0_CKC_SC 0x0000000000000800ULL 339 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 340 #define CR0_SERVICE_SC 0x0000000000000200ULL 341 342 /* Control register 14 bits */ 343 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 344 345 /* MMU */ 346 #define MMU_PRIMARY_IDX 0 347 #define MMU_SECONDARY_IDX 1 348 #define MMU_HOME_IDX 2 349 #define MMU_REAL_IDX 3 350 351 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 352 { 353 #ifdef CONFIG_USER_ONLY 354 return MMU_USER_IDX; 355 #else 356 if (!(env->psw.mask & PSW_MASK_DAT)) { 357 return MMU_REAL_IDX; 358 } 359 360 if (ifetch) { 361 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 362 return MMU_HOME_IDX; 363 } 364 return MMU_PRIMARY_IDX; 365 } 366 367 switch (env->psw.mask & PSW_MASK_ASC) { 368 case PSW_ASC_PRIMARY: 369 return MMU_PRIMARY_IDX; 370 case PSW_ASC_SECONDARY: 371 return MMU_SECONDARY_IDX; 372 case PSW_ASC_HOME: 373 return MMU_HOME_IDX; 374 case PSW_ASC_ACCREG: 375 /* Fallthrough: access register mode is not yet supported */ 376 default: 377 abort(); 378 } 379 #endif 380 } 381 382 static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, 383 uint64_t *cs_base, uint32_t *flags) 384 { 385 if (env->psw.addr & 1) { 386 /* 387 * Instructions must be at even addresses. 388 * This needs to be checked before address translation. 389 */ 390 env->int_pgm_ilen = 2; /* see s390_cpu_tlb_fill() */ 391 tcg_s390_program_interrupt(env, PGM_SPECIFICATION, 0); 392 } 393 *pc = env->psw.addr; 394 *cs_base = env->ex_value; 395 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 396 if (env->cregs[0] & CR0_AFP) { 397 *flags |= FLAG_MASK_AFP; 398 } 399 if (env->cregs[0] & CR0_VECTOR) { 400 *flags |= FLAG_MASK_VECTOR; 401 } 402 } 403 404 /* PER bits from control register 9 */ 405 #define PER_CR9_EVENT_BRANCH 0x80000000 406 #define PER_CR9_EVENT_IFETCH 0x40000000 407 #define PER_CR9_EVENT_STORE 0x20000000 408 #define PER_CR9_EVENT_STORE_REAL 0x08000000 409 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 410 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 411 #define PER_CR9_CONTROL_ALTERATION 0x00200000 412 413 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 414 #define PER_CODE_EVENT_BRANCH 0x8000 415 #define PER_CODE_EVENT_IFETCH 0x4000 416 #define PER_CODE_EVENT_STORE 0x2000 417 #define PER_CODE_EVENT_STORE_REAL 0x0800 418 #define PER_CODE_EVENT_NULLIFICATION 0x0100 419 420 #define EXCP_EXT 1 /* external interrupt */ 421 #define EXCP_SVC 2 /* supervisor call (syscall) */ 422 #define EXCP_PGM 3 /* program interruption */ 423 #define EXCP_RESTART 4 /* restart interrupt */ 424 #define EXCP_STOP 5 /* stop interrupt */ 425 #define EXCP_IO 7 /* I/O interrupt */ 426 #define EXCP_MCHK 8 /* machine check */ 427 428 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 429 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 430 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 431 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 432 #define INTERRUPT_RESTART (1 << 7) 433 #define INTERRUPT_STOP (1 << 8) 434 435 /* Program Status Word. */ 436 #define S390_PSWM_REGNUM 0 437 #define S390_PSWA_REGNUM 1 438 /* General Purpose Registers. */ 439 #define S390_R0_REGNUM 2 440 #define S390_R1_REGNUM 3 441 #define S390_R2_REGNUM 4 442 #define S390_R3_REGNUM 5 443 #define S390_R4_REGNUM 6 444 #define S390_R5_REGNUM 7 445 #define S390_R6_REGNUM 8 446 #define S390_R7_REGNUM 9 447 #define S390_R8_REGNUM 10 448 #define S390_R9_REGNUM 11 449 #define S390_R10_REGNUM 12 450 #define S390_R11_REGNUM 13 451 #define S390_R12_REGNUM 14 452 #define S390_R13_REGNUM 15 453 #define S390_R14_REGNUM 16 454 #define S390_R15_REGNUM 17 455 /* Total Core Registers. */ 456 #define S390_NUM_CORE_REGS 18 457 458 static inline void setcc(S390CPU *cpu, uint64_t cc) 459 { 460 CPUS390XState *env = &cpu->env; 461 462 env->psw.mask &= ~(3ull << 44); 463 env->psw.mask |= (cc & 3) << 44; 464 env->cc_op = cc; 465 } 466 467 /* STSI */ 468 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 469 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 470 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 471 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 472 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 473 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 474 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 475 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 476 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 477 478 /* Basic Machine Configuration */ 479 typedef struct SysIB_111 { 480 uint8_t res1[32]; 481 uint8_t manuf[16]; 482 uint8_t type[4]; 483 uint8_t res2[12]; 484 uint8_t model[16]; 485 uint8_t sequence[16]; 486 uint8_t plant[4]; 487 uint8_t res3[3996]; 488 } SysIB_111; 489 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 490 491 /* Basic Machine CPU */ 492 typedef struct SysIB_121 { 493 uint8_t res1[80]; 494 uint8_t sequence[16]; 495 uint8_t plant[4]; 496 uint8_t res2[2]; 497 uint16_t cpu_addr; 498 uint8_t res3[3992]; 499 } SysIB_121; 500 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 501 502 /* Basic Machine CPUs */ 503 typedef struct SysIB_122 { 504 uint8_t res1[32]; 505 uint32_t capability; 506 uint16_t total_cpus; 507 uint16_t conf_cpus; 508 uint16_t standby_cpus; 509 uint16_t reserved_cpus; 510 uint16_t adjustments[2026]; 511 } SysIB_122; 512 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 513 514 /* LPAR CPU */ 515 typedef struct SysIB_221 { 516 uint8_t res1[80]; 517 uint8_t sequence[16]; 518 uint8_t plant[4]; 519 uint16_t cpu_id; 520 uint16_t cpu_addr; 521 uint8_t res3[3992]; 522 } SysIB_221; 523 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 524 525 /* LPAR CPUs */ 526 typedef struct SysIB_222 { 527 uint8_t res1[32]; 528 uint16_t lpar_num; 529 uint8_t res2; 530 uint8_t lcpuc; 531 uint16_t total_cpus; 532 uint16_t conf_cpus; 533 uint16_t standby_cpus; 534 uint16_t reserved_cpus; 535 uint8_t name[8]; 536 uint32_t caf; 537 uint8_t res3[16]; 538 uint16_t dedicated_cpus; 539 uint16_t shared_cpus; 540 uint8_t res4[4020]; 541 } SysIB_222; 542 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 543 544 /* VM CPUs */ 545 typedef struct SysIB_322 { 546 uint8_t res1[31]; 547 uint8_t count; 548 struct { 549 uint8_t res2[4]; 550 uint16_t total_cpus; 551 uint16_t conf_cpus; 552 uint16_t standby_cpus; 553 uint16_t reserved_cpus; 554 uint8_t name[8]; 555 uint32_t caf; 556 uint8_t cpi[16]; 557 uint8_t res5[3]; 558 uint8_t ext_name_encoding; 559 uint32_t res3; 560 uint8_t uuid[16]; 561 } vm[8]; 562 uint8_t res4[1504]; 563 uint8_t ext_names[8][256]; 564 } SysIB_322; 565 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 566 567 typedef union SysIB { 568 SysIB_111 sysib_111; 569 SysIB_121 sysib_121; 570 SysIB_122 sysib_122; 571 SysIB_221 sysib_221; 572 SysIB_222 sysib_222; 573 SysIB_322 sysib_322; 574 } SysIB; 575 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 576 577 /* MMU defines */ 578 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 579 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 580 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 581 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 582 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 583 #define ASCE_REAL_SPACE 0x20 /* real space control */ 584 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 585 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 586 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 587 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 588 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 589 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 590 591 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 592 #define REGION_ENTRY_P 0x0000000000000200ULL 593 #define REGION_ENTRY_TF 0x00000000000000c0ULL 594 #define REGION_ENTRY_I 0x0000000000000020ULL 595 #define REGION_ENTRY_TT 0x000000000000000cULL 596 #define REGION_ENTRY_TL 0x0000000000000003ULL 597 598 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 599 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 600 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 601 602 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 603 #define REGION3_ENTRY_AV 0x0000000000010000ULL 604 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 605 #define REGION3_ENTRY_F 0x0000000000000800ULL 606 #define REGION3_ENTRY_FC 0x0000000000000400ULL 607 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 608 #define REGION3_ENTRY_CR 0x0000000000000010ULL 609 610 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 611 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 612 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 613 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 614 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 615 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 616 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 617 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 618 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 619 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 620 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 621 622 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 623 624 #define PAGE_ENTRY_0 0x0000000000000800ULL 625 #define PAGE_ENTRY_I 0x0000000000000400ULL 626 #define PAGE_ENTRY_P 0x0000000000000200ULL 627 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 628 629 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 630 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 631 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 632 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 633 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 634 635 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 636 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 637 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 638 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 639 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 640 641 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 642 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 643 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 644 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 645 646 #define SK_C (0x1 << 1) 647 #define SK_R (0x1 << 2) 648 #define SK_F (0x1 << 3) 649 #define SK_ACC_MASK (0xf << 4) 650 651 /* SIGP order codes */ 652 #define SIGP_SENSE 0x01 653 #define SIGP_EXTERNAL_CALL 0x02 654 #define SIGP_EMERGENCY 0x03 655 #define SIGP_START 0x04 656 #define SIGP_STOP 0x05 657 #define SIGP_RESTART 0x06 658 #define SIGP_STOP_STORE_STATUS 0x09 659 #define SIGP_INITIAL_CPU_RESET 0x0b 660 #define SIGP_CPU_RESET 0x0c 661 #define SIGP_SET_PREFIX 0x0d 662 #define SIGP_STORE_STATUS_ADDR 0x0e 663 #define SIGP_SET_ARCH 0x12 664 #define SIGP_COND_EMERGENCY 0x13 665 #define SIGP_SENSE_RUNNING 0x15 666 #define SIGP_STORE_ADTL_STATUS 0x17 667 668 /* SIGP condition codes */ 669 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 670 #define SIGP_CC_STATUS_STORED 1 671 #define SIGP_CC_BUSY 2 672 #define SIGP_CC_NOT_OPERATIONAL 3 673 674 /* SIGP status bits */ 675 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 676 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 677 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 678 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 679 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 680 #define SIGP_STAT_STOPPED 0x00000040UL 681 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 682 #define SIGP_STAT_CHECK_STOP 0x00000010UL 683 #define SIGP_STAT_INOPERATIVE 0x00000004UL 684 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 685 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 686 687 /* SIGP order code mask corresponding to bit positions 56-63 */ 688 #define SIGP_ORDER_MASK 0x000000ff 689 690 /* machine check interruption code */ 691 692 /* subclasses */ 693 #define MCIC_SC_SD 0x8000000000000000ULL 694 #define MCIC_SC_PD 0x4000000000000000ULL 695 #define MCIC_SC_SR 0x2000000000000000ULL 696 #define MCIC_SC_CD 0x0800000000000000ULL 697 #define MCIC_SC_ED 0x0400000000000000ULL 698 #define MCIC_SC_DG 0x0100000000000000ULL 699 #define MCIC_SC_W 0x0080000000000000ULL 700 #define MCIC_SC_CP 0x0040000000000000ULL 701 #define MCIC_SC_SP 0x0020000000000000ULL 702 #define MCIC_SC_CK 0x0010000000000000ULL 703 704 /* subclass modifiers */ 705 #define MCIC_SCM_B 0x0002000000000000ULL 706 #define MCIC_SCM_DA 0x0000000020000000ULL 707 #define MCIC_SCM_AP 0x0000000000080000ULL 708 709 /* storage errors */ 710 #define MCIC_SE_SE 0x0000800000000000ULL 711 #define MCIC_SE_SC 0x0000400000000000ULL 712 #define MCIC_SE_KE 0x0000200000000000ULL 713 #define MCIC_SE_DS 0x0000100000000000ULL 714 #define MCIC_SE_IE 0x0000000080000000ULL 715 716 /* validity bits */ 717 #define MCIC_VB_WP 0x0000080000000000ULL 718 #define MCIC_VB_MS 0x0000040000000000ULL 719 #define MCIC_VB_PM 0x0000020000000000ULL 720 #define MCIC_VB_IA 0x0000010000000000ULL 721 #define MCIC_VB_FA 0x0000008000000000ULL 722 #define MCIC_VB_VR 0x0000004000000000ULL 723 #define MCIC_VB_EC 0x0000002000000000ULL 724 #define MCIC_VB_FP 0x0000001000000000ULL 725 #define MCIC_VB_GR 0x0000000800000000ULL 726 #define MCIC_VB_CR 0x0000000400000000ULL 727 #define MCIC_VB_ST 0x0000000100000000ULL 728 #define MCIC_VB_AR 0x0000000040000000ULL 729 #define MCIC_VB_GS 0x0000000008000000ULL 730 #define MCIC_VB_PR 0x0000000000200000ULL 731 #define MCIC_VB_FC 0x0000000000100000ULL 732 #define MCIC_VB_CT 0x0000000000020000ULL 733 #define MCIC_VB_CC 0x0000000000010000ULL 734 735 static inline uint64_t s390_build_validity_mcic(void) 736 { 737 uint64_t mcic; 738 739 /* 740 * Indicate all validity bits (no damage) only. Other bits have to be 741 * added by the caller. (storage errors, subclasses and subclass modifiers) 742 */ 743 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 744 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 745 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 746 if (s390_has_feat(S390_FEAT_VECTOR)) { 747 mcic |= MCIC_VB_VR; 748 } 749 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 750 mcic |= MCIC_VB_GS; 751 } 752 return mcic; 753 } 754 755 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 756 { 757 cpu_reset(cs); 758 } 759 760 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 761 { 762 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 763 764 scc->reset(cs, S390_CPU_RESET_NORMAL); 765 } 766 767 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 768 { 769 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 770 771 scc->reset(cs, S390_CPU_RESET_INITIAL); 772 } 773 774 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 775 { 776 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 777 778 scc->load_normal(cs); 779 } 780 781 782 /* cpu.c */ 783 void s390_crypto_reset(void); 784 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 785 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 786 void s390_cmma_reset(void); 787 void s390_enable_css_support(S390CPU *cpu); 788 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 789 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 790 int vq, bool assign); 791 #ifndef CONFIG_USER_ONLY 792 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 793 #else 794 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 795 { 796 return 0; 797 } 798 #endif /* CONFIG_USER_ONLY */ 799 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 800 { 801 return cpu->env.cpu_state; 802 } 803 804 805 /* cpu_models.c */ 806 void s390_cpu_list(void); 807 #define cpu_list s390_cpu_list 808 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 809 const S390FeatInit feat_init); 810 811 812 /* helper.c */ 813 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 814 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 815 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 816 817 /* interrupt.c */ 818 #define RA_IGNORED 0 819 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 820 /* service interrupts are floating therefore we must not pass an cpustate */ 821 void s390_sclp_extint(uint32_t parm); 822 823 /* mmu_helper.c */ 824 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 825 int len, bool is_write); 826 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 827 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 828 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 829 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 830 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 831 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 832 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 833 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 834 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 835 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 836 int len, bool is_write); 837 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 838 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 839 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 840 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 841 842 /* sigp.c */ 843 int s390_cpu_restart(S390CPU *cpu); 844 void s390_init_sigp(void); 845 846 /* helper.c */ 847 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); 848 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); 849 850 /* outside of target/s390x/ */ 851 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 852 853 #include "exec/cpu-all.h" 854 855 #endif 856