1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * Copyright IBM Corp. 2012, 2018 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * Contributions after 2012-10-29 are licensed under the terms of the 18 * GNU GPL, version 2 or (at your option) any later version. 19 * 20 * You should have received a copy of the GNU (Lesser) General Public 21 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef S390X_CPU_H 25 #define S390X_CPU_H 26 27 #include "qemu-common.h" 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 31 #define TARGET_LONG_BITS 64 32 33 #define ELF_MACHINE_UNAME "S390X" 34 35 #define CPUArchState struct CPUS390XState 36 37 #include "exec/cpu-defs.h" 38 39 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 40 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 41 42 #define TARGET_PAGE_BITS 12 43 44 #define TARGET_PHYS_ADDR_SPACE_BITS 64 45 #define TARGET_VIRT_ADDR_SPACE_BITS 64 46 47 #include "exec/cpu-all.h" 48 49 #define NB_MMU_MODES 4 50 #define TARGET_INSN_START_EXTRA_WORDS 1 51 52 #define MMU_MODE0_SUFFIX _primary 53 #define MMU_MODE1_SUFFIX _secondary 54 #define MMU_MODE2_SUFFIX _home 55 #define MMU_MODE3_SUFFIX _real 56 57 #define MMU_USER_IDX 0 58 59 #define S390_MAX_CPUS 248 60 61 typedef struct PSW { 62 uint64_t mask; 63 uint64_t addr; 64 } PSW; 65 66 struct CPUS390XState { 67 uint64_t regs[16]; /* GP registers */ 68 /* 69 * The floating point registers are part of the vector registers. 70 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 71 */ 72 CPU_DoubleU vregs[32][2]; /* vector registers */ 73 uint32_t aregs[16]; /* access registers */ 74 uint8_t riccb[64]; /* runtime instrumentation control */ 75 uint64_t gscb[4]; /* guarded storage control */ 76 uint64_t etoken; /* etoken */ 77 uint64_t etoken_extension; /* etoken extension */ 78 79 /* Fields up to this point are not cleared by initial CPU reset */ 80 struct {} start_initial_reset_fields; 81 82 uint32_t fpc; /* floating-point control register */ 83 uint32_t cc_op; 84 bool bpbc; /* branch prediction blocking */ 85 86 float_status fpu_status; /* passed to softfloat lib */ 87 88 /* The low part of a 128-bit return, or remainder of a divide. */ 89 uint64_t retxl; 90 91 PSW psw; 92 93 S390CrashReason crash_reason; 94 95 uint64_t cc_src; 96 uint64_t cc_dst; 97 uint64_t cc_vr; 98 99 uint64_t ex_value; 100 101 uint64_t __excp_addr; 102 uint64_t psa; 103 104 uint32_t int_pgm_code; 105 uint32_t int_pgm_ilen; 106 107 uint32_t int_svc_code; 108 uint32_t int_svc_ilen; 109 110 uint64_t per_address; 111 uint16_t per_perc_atmid; 112 113 uint64_t cregs[16]; /* control registers */ 114 115 int pending_int; 116 uint16_t external_call_addr; 117 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 118 119 uint64_t ckc; 120 uint64_t cputm; 121 uint32_t todpr; 122 123 uint64_t pfault_token; 124 uint64_t pfault_compare; 125 uint64_t pfault_select; 126 127 uint64_t gbea; 128 uint64_t pp; 129 130 /* Fields up to this point are cleared by a CPU reset */ 131 struct {} end_reset_fields; 132 133 CPU_COMMON 134 135 #if !defined(CONFIG_USER_ONLY) 136 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 137 uint64_t cpuid; 138 #endif 139 140 QEMUTimer *tod_timer; 141 142 QEMUTimer *cpu_timer; 143 144 /* 145 * The cpu state represents the logical state of a cpu. In contrast to other 146 * architectures, there is a difference between a halt and a stop on s390. 147 * If all cpus are either stopped (including check stop) or in the disabled 148 * wait state, the vm can be shut down. 149 * The acceptable cpu_state values are defined in the CpuInfoS390State 150 * enum. 151 */ 152 uint8_t cpu_state; 153 154 /* currently processed sigp order */ 155 uint8_t sigp_order; 156 157 }; 158 159 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) 160 { 161 return &cs->vregs[nr][0]; 162 } 163 164 /** 165 * S390CPU: 166 * @env: #CPUS390XState. 167 * 168 * An S/390 CPU. 169 */ 170 struct S390CPU { 171 /*< private >*/ 172 CPUState parent_obj; 173 /*< public >*/ 174 175 CPUS390XState env; 176 S390CPUModel *model; 177 /* needed for live migration */ 178 void *irqstate; 179 uint32_t irqstate_saved_size; 180 }; 181 182 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) 183 { 184 return container_of(env, S390CPU, env); 185 } 186 187 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) 188 189 #define ENV_OFFSET offsetof(S390CPU, env) 190 191 #ifndef CONFIG_USER_ONLY 192 extern const struct VMStateDescription vmstate_s390_cpu; 193 #endif 194 195 /* distinguish between 24 bit and 31 bit addressing */ 196 #define HIGH_ORDER_BIT 0x80000000 197 198 /* Interrupt Codes */ 199 /* Program Interrupts */ 200 #define PGM_OPERATION 0x0001 201 #define PGM_PRIVILEGED 0x0002 202 #define PGM_EXECUTE 0x0003 203 #define PGM_PROTECTION 0x0004 204 #define PGM_ADDRESSING 0x0005 205 #define PGM_SPECIFICATION 0x0006 206 #define PGM_DATA 0x0007 207 #define PGM_FIXPT_OVERFLOW 0x0008 208 #define PGM_FIXPT_DIVIDE 0x0009 209 #define PGM_DEC_OVERFLOW 0x000a 210 #define PGM_DEC_DIVIDE 0x000b 211 #define PGM_HFP_EXP_OVERFLOW 0x000c 212 #define PGM_HFP_EXP_UNDERFLOW 0x000d 213 #define PGM_HFP_SIGNIFICANCE 0x000e 214 #define PGM_HFP_DIVIDE 0x000f 215 #define PGM_SEGMENT_TRANS 0x0010 216 #define PGM_PAGE_TRANS 0x0011 217 #define PGM_TRANS_SPEC 0x0012 218 #define PGM_SPECIAL_OP 0x0013 219 #define PGM_OPERAND 0x0015 220 #define PGM_TRACE_TABLE 0x0016 221 #define PGM_SPACE_SWITCH 0x001c 222 #define PGM_HFP_SQRT 0x001d 223 #define PGM_PC_TRANS_SPEC 0x001f 224 #define PGM_AFX_TRANS 0x0020 225 #define PGM_ASX_TRANS 0x0021 226 #define PGM_LX_TRANS 0x0022 227 #define PGM_EX_TRANS 0x0023 228 #define PGM_PRIM_AUTH 0x0024 229 #define PGM_SEC_AUTH 0x0025 230 #define PGM_ALET_SPEC 0x0028 231 #define PGM_ALEN_SPEC 0x0029 232 #define PGM_ALE_SEQ 0x002a 233 #define PGM_ASTE_VALID 0x002b 234 #define PGM_ASTE_SEQ 0x002c 235 #define PGM_EXT_AUTH 0x002d 236 #define PGM_STACK_FULL 0x0030 237 #define PGM_STACK_EMPTY 0x0031 238 #define PGM_STACK_SPEC 0x0032 239 #define PGM_STACK_TYPE 0x0033 240 #define PGM_STACK_OP 0x0034 241 #define PGM_ASCE_TYPE 0x0038 242 #define PGM_REG_FIRST_TRANS 0x0039 243 #define PGM_REG_SEC_TRANS 0x003a 244 #define PGM_REG_THIRD_TRANS 0x003b 245 #define PGM_MONITOR 0x0040 246 #define PGM_PER 0x0080 247 #define PGM_CRYPTO 0x0119 248 249 /* External Interrupts */ 250 #define EXT_INTERRUPT_KEY 0x0040 251 #define EXT_CLOCK_COMP 0x1004 252 #define EXT_CPU_TIMER 0x1005 253 #define EXT_MALFUNCTION 0x1200 254 #define EXT_EMERGENCY 0x1201 255 #define EXT_EXTERNAL_CALL 0x1202 256 #define EXT_ETR 0x1406 257 #define EXT_SERVICE 0x2401 258 #define EXT_VIRTIO 0x2603 259 260 /* PSW defines */ 261 #undef PSW_MASK_PER 262 #undef PSW_MASK_UNUSED_2 263 #undef PSW_MASK_DAT 264 #undef PSW_MASK_IO 265 #undef PSW_MASK_EXT 266 #undef PSW_MASK_KEY 267 #undef PSW_SHIFT_KEY 268 #undef PSW_MASK_MCHECK 269 #undef PSW_MASK_WAIT 270 #undef PSW_MASK_PSTATE 271 #undef PSW_MASK_ASC 272 #undef PSW_SHIFT_ASC 273 #undef PSW_MASK_CC 274 #undef PSW_MASK_PM 275 #undef PSW_SHIFT_MASK_PM 276 #undef PSW_MASK_64 277 #undef PSW_MASK_32 278 #undef PSW_MASK_ESA_ADDR 279 280 #define PSW_MASK_PER 0x4000000000000000ULL 281 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 282 #define PSW_MASK_DAT 0x0400000000000000ULL 283 #define PSW_MASK_IO 0x0200000000000000ULL 284 #define PSW_MASK_EXT 0x0100000000000000ULL 285 #define PSW_MASK_KEY 0x00F0000000000000ULL 286 #define PSW_SHIFT_KEY 52 287 #define PSW_MASK_MCHECK 0x0004000000000000ULL 288 #define PSW_MASK_WAIT 0x0002000000000000ULL 289 #define PSW_MASK_PSTATE 0x0001000000000000ULL 290 #define PSW_MASK_ASC 0x0000C00000000000ULL 291 #define PSW_SHIFT_ASC 46 292 #define PSW_MASK_CC 0x0000300000000000ULL 293 #define PSW_MASK_PM 0x00000F0000000000ULL 294 #define PSW_SHIFT_MASK_PM 40 295 #define PSW_MASK_64 0x0000000100000000ULL 296 #define PSW_MASK_32 0x0000000080000000ULL 297 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 298 299 #undef PSW_ASC_PRIMARY 300 #undef PSW_ASC_ACCREG 301 #undef PSW_ASC_SECONDARY 302 #undef PSW_ASC_HOME 303 304 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 305 #define PSW_ASC_ACCREG 0x0000400000000000ULL 306 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 307 #define PSW_ASC_HOME 0x0000C00000000000ULL 308 309 /* the address space values shifted */ 310 #define AS_PRIMARY 0 311 #define AS_ACCREG 1 312 #define AS_SECONDARY 2 313 #define AS_HOME 3 314 315 /* tb flags */ 316 317 #define FLAG_MASK_PSW_SHIFT 31 318 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 319 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 320 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 321 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 322 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 323 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 324 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 325 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 326 327 /* we'll use some unused PSW positions to store CR flags in tb flags */ 328 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 329 330 /* Control register 0 bits */ 331 #define CR0_LOWPROT 0x0000000010000000ULL 332 #define CR0_SECONDARY 0x0000000004000000ULL 333 #define CR0_EDAT 0x0000000000800000ULL 334 #define CR0_AFP 0x0000000000040000ULL 335 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 336 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 337 #define CR0_CKC_SC 0x0000000000000800ULL 338 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 339 #define CR0_SERVICE_SC 0x0000000000000200ULL 340 341 /* Control register 14 bits */ 342 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 343 344 /* MMU */ 345 #define MMU_PRIMARY_IDX 0 346 #define MMU_SECONDARY_IDX 1 347 #define MMU_HOME_IDX 2 348 #define MMU_REAL_IDX 3 349 350 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 351 { 352 if (!(env->psw.mask & PSW_MASK_DAT)) { 353 return MMU_REAL_IDX; 354 } 355 356 switch (env->psw.mask & PSW_MASK_ASC) { 357 case PSW_ASC_PRIMARY: 358 return MMU_PRIMARY_IDX; 359 case PSW_ASC_SECONDARY: 360 return MMU_SECONDARY_IDX; 361 case PSW_ASC_HOME: 362 return MMU_HOME_IDX; 363 case PSW_ASC_ACCREG: 364 /* Fallthrough: access register mode is not yet supported */ 365 default: 366 abort(); 367 } 368 } 369 370 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 371 target_ulong *cs_base, uint32_t *flags) 372 { 373 *pc = env->psw.addr; 374 *cs_base = env->ex_value; 375 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 376 if (env->cregs[0] & CR0_AFP) { 377 *flags |= FLAG_MASK_AFP; 378 } 379 } 380 381 /* PER bits from control register 9 */ 382 #define PER_CR9_EVENT_BRANCH 0x80000000 383 #define PER_CR9_EVENT_IFETCH 0x40000000 384 #define PER_CR9_EVENT_STORE 0x20000000 385 #define PER_CR9_EVENT_STORE_REAL 0x08000000 386 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 387 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 388 #define PER_CR9_CONTROL_ALTERATION 0x00200000 389 390 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 391 #define PER_CODE_EVENT_BRANCH 0x8000 392 #define PER_CODE_EVENT_IFETCH 0x4000 393 #define PER_CODE_EVENT_STORE 0x2000 394 #define PER_CODE_EVENT_STORE_REAL 0x0800 395 #define PER_CODE_EVENT_NULLIFICATION 0x0100 396 397 #define EXCP_EXT 1 /* external interrupt */ 398 #define EXCP_SVC 2 /* supervisor call (syscall) */ 399 #define EXCP_PGM 3 /* program interruption */ 400 #define EXCP_RESTART 4 /* restart interrupt */ 401 #define EXCP_STOP 5 /* stop interrupt */ 402 #define EXCP_IO 7 /* I/O interrupt */ 403 #define EXCP_MCHK 8 /* machine check */ 404 405 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 406 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 407 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 408 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 409 #define INTERRUPT_RESTART (1 << 7) 410 #define INTERRUPT_STOP (1 << 8) 411 412 /* Program Status Word. */ 413 #define S390_PSWM_REGNUM 0 414 #define S390_PSWA_REGNUM 1 415 /* General Purpose Registers. */ 416 #define S390_R0_REGNUM 2 417 #define S390_R1_REGNUM 3 418 #define S390_R2_REGNUM 4 419 #define S390_R3_REGNUM 5 420 #define S390_R4_REGNUM 6 421 #define S390_R5_REGNUM 7 422 #define S390_R6_REGNUM 8 423 #define S390_R7_REGNUM 9 424 #define S390_R8_REGNUM 10 425 #define S390_R9_REGNUM 11 426 #define S390_R10_REGNUM 12 427 #define S390_R11_REGNUM 13 428 #define S390_R12_REGNUM 14 429 #define S390_R13_REGNUM 15 430 #define S390_R14_REGNUM 16 431 #define S390_R15_REGNUM 17 432 /* Total Core Registers. */ 433 #define S390_NUM_CORE_REGS 18 434 435 static inline void setcc(S390CPU *cpu, uint64_t cc) 436 { 437 CPUS390XState *env = &cpu->env; 438 439 env->psw.mask &= ~(3ull << 44); 440 env->psw.mask |= (cc & 3) << 44; 441 env->cc_op = cc; 442 } 443 444 /* STSI */ 445 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 446 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 447 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 448 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 449 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 450 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 451 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 452 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 453 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 454 455 /* Basic Machine Configuration */ 456 typedef struct SysIB_111 { 457 uint8_t res1[32]; 458 uint8_t manuf[16]; 459 uint8_t type[4]; 460 uint8_t res2[12]; 461 uint8_t model[16]; 462 uint8_t sequence[16]; 463 uint8_t plant[4]; 464 uint8_t res3[3996]; 465 } SysIB_111; 466 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 467 468 /* Basic Machine CPU */ 469 typedef struct SysIB_121 { 470 uint8_t res1[80]; 471 uint8_t sequence[16]; 472 uint8_t plant[4]; 473 uint8_t res2[2]; 474 uint16_t cpu_addr; 475 uint8_t res3[3992]; 476 } SysIB_121; 477 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 478 479 /* Basic Machine CPUs */ 480 typedef struct SysIB_122 { 481 uint8_t res1[32]; 482 uint32_t capability; 483 uint16_t total_cpus; 484 uint16_t conf_cpus; 485 uint16_t standby_cpus; 486 uint16_t reserved_cpus; 487 uint16_t adjustments[2026]; 488 } SysIB_122; 489 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 490 491 /* LPAR CPU */ 492 typedef struct SysIB_221 { 493 uint8_t res1[80]; 494 uint8_t sequence[16]; 495 uint8_t plant[4]; 496 uint16_t cpu_id; 497 uint16_t cpu_addr; 498 uint8_t res3[3992]; 499 } SysIB_221; 500 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 501 502 /* LPAR CPUs */ 503 typedef struct SysIB_222 { 504 uint8_t res1[32]; 505 uint16_t lpar_num; 506 uint8_t res2; 507 uint8_t lcpuc; 508 uint16_t total_cpus; 509 uint16_t conf_cpus; 510 uint16_t standby_cpus; 511 uint16_t reserved_cpus; 512 uint8_t name[8]; 513 uint32_t caf; 514 uint8_t res3[16]; 515 uint16_t dedicated_cpus; 516 uint16_t shared_cpus; 517 uint8_t res4[4020]; 518 } SysIB_222; 519 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 520 521 /* VM CPUs */ 522 typedef struct SysIB_322 { 523 uint8_t res1[31]; 524 uint8_t count; 525 struct { 526 uint8_t res2[4]; 527 uint16_t total_cpus; 528 uint16_t conf_cpus; 529 uint16_t standby_cpus; 530 uint16_t reserved_cpus; 531 uint8_t name[8]; 532 uint32_t caf; 533 uint8_t cpi[16]; 534 uint8_t res5[3]; 535 uint8_t ext_name_encoding; 536 uint32_t res3; 537 uint8_t uuid[16]; 538 } vm[8]; 539 uint8_t res4[1504]; 540 uint8_t ext_names[8][256]; 541 } SysIB_322; 542 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 543 544 typedef union SysIB { 545 SysIB_111 sysib_111; 546 SysIB_121 sysib_121; 547 SysIB_122 sysib_122; 548 SysIB_221 sysib_221; 549 SysIB_222 sysib_222; 550 SysIB_322 sysib_322; 551 } SysIB; 552 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 553 554 /* MMU defines */ 555 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 556 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 557 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 558 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 559 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 560 #define ASCE_REAL_SPACE 0x20 /* real space control */ 561 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 562 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 563 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 564 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 565 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 566 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 567 568 #define REGION_ENTRY_ORIGIN (~0xfffULL) /* region/segment table origin */ 569 #define REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 570 #define REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 571 #define REGION_ENTRY_INV 0x20 /* invalid region table entry */ 572 #define REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 573 #define REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 574 #define REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 575 #define REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 576 #define REGION_ENTRY_LENGTH 0x03 /* region third length */ 577 578 #define SEGMENT_ENTRY_ORIGIN (~0x7ffULL) /* segment table origin */ 579 #define SEGMENT_ENTRY_FC 0x400 /* format control */ 580 #define SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 581 #define SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 582 583 #define VADDR_PX 0xff000 /* page index bits */ 584 585 #define PAGE_RO 0x200 /* HW read-only bit */ 586 #define PAGE_INVALID 0x400 /* HW invalid bit */ 587 #define PAGE_RES0 0x800 /* bit must be zero */ 588 589 #define SK_C (0x1 << 1) 590 #define SK_R (0x1 << 2) 591 #define SK_F (0x1 << 3) 592 #define SK_ACC_MASK (0xf << 4) 593 594 /* SIGP order codes */ 595 #define SIGP_SENSE 0x01 596 #define SIGP_EXTERNAL_CALL 0x02 597 #define SIGP_EMERGENCY 0x03 598 #define SIGP_START 0x04 599 #define SIGP_STOP 0x05 600 #define SIGP_RESTART 0x06 601 #define SIGP_STOP_STORE_STATUS 0x09 602 #define SIGP_INITIAL_CPU_RESET 0x0b 603 #define SIGP_CPU_RESET 0x0c 604 #define SIGP_SET_PREFIX 0x0d 605 #define SIGP_STORE_STATUS_ADDR 0x0e 606 #define SIGP_SET_ARCH 0x12 607 #define SIGP_COND_EMERGENCY 0x13 608 #define SIGP_SENSE_RUNNING 0x15 609 #define SIGP_STORE_ADTL_STATUS 0x17 610 611 /* SIGP condition codes */ 612 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 613 #define SIGP_CC_STATUS_STORED 1 614 #define SIGP_CC_BUSY 2 615 #define SIGP_CC_NOT_OPERATIONAL 3 616 617 /* SIGP status bits */ 618 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 619 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 620 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 621 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 622 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 623 #define SIGP_STAT_STOPPED 0x00000040UL 624 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 625 #define SIGP_STAT_CHECK_STOP 0x00000010UL 626 #define SIGP_STAT_INOPERATIVE 0x00000004UL 627 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 628 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 629 630 /* SIGP SET ARCHITECTURE modes */ 631 #define SIGP_MODE_ESA_S390 0 632 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 633 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 634 635 /* SIGP order code mask corresponding to bit positions 56-63 */ 636 #define SIGP_ORDER_MASK 0x000000ff 637 638 /* machine check interruption code */ 639 640 /* subclasses */ 641 #define MCIC_SC_SD 0x8000000000000000ULL 642 #define MCIC_SC_PD 0x4000000000000000ULL 643 #define MCIC_SC_SR 0x2000000000000000ULL 644 #define MCIC_SC_CD 0x0800000000000000ULL 645 #define MCIC_SC_ED 0x0400000000000000ULL 646 #define MCIC_SC_DG 0x0100000000000000ULL 647 #define MCIC_SC_W 0x0080000000000000ULL 648 #define MCIC_SC_CP 0x0040000000000000ULL 649 #define MCIC_SC_SP 0x0020000000000000ULL 650 #define MCIC_SC_CK 0x0010000000000000ULL 651 652 /* subclass modifiers */ 653 #define MCIC_SCM_B 0x0002000000000000ULL 654 #define MCIC_SCM_DA 0x0000000020000000ULL 655 #define MCIC_SCM_AP 0x0000000000080000ULL 656 657 /* storage errors */ 658 #define MCIC_SE_SE 0x0000800000000000ULL 659 #define MCIC_SE_SC 0x0000400000000000ULL 660 #define MCIC_SE_KE 0x0000200000000000ULL 661 #define MCIC_SE_DS 0x0000100000000000ULL 662 #define MCIC_SE_IE 0x0000000080000000ULL 663 664 /* validity bits */ 665 #define MCIC_VB_WP 0x0000080000000000ULL 666 #define MCIC_VB_MS 0x0000040000000000ULL 667 #define MCIC_VB_PM 0x0000020000000000ULL 668 #define MCIC_VB_IA 0x0000010000000000ULL 669 #define MCIC_VB_FA 0x0000008000000000ULL 670 #define MCIC_VB_VR 0x0000004000000000ULL 671 #define MCIC_VB_EC 0x0000002000000000ULL 672 #define MCIC_VB_FP 0x0000001000000000ULL 673 #define MCIC_VB_GR 0x0000000800000000ULL 674 #define MCIC_VB_CR 0x0000000400000000ULL 675 #define MCIC_VB_ST 0x0000000100000000ULL 676 #define MCIC_VB_AR 0x0000000040000000ULL 677 #define MCIC_VB_GS 0x0000000008000000ULL 678 #define MCIC_VB_PR 0x0000000000200000ULL 679 #define MCIC_VB_FC 0x0000000000100000ULL 680 #define MCIC_VB_CT 0x0000000000020000ULL 681 #define MCIC_VB_CC 0x0000000000010000ULL 682 683 static inline uint64_t s390_build_validity_mcic(void) 684 { 685 uint64_t mcic; 686 687 /* 688 * Indicate all validity bits (no damage) only. Other bits have to be 689 * added by the caller. (storage errors, subclasses and subclass modifiers) 690 */ 691 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 692 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 693 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 694 if (s390_has_feat(S390_FEAT_VECTOR)) { 695 mcic |= MCIC_VB_VR; 696 } 697 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 698 mcic |= MCIC_VB_GS; 699 } 700 return mcic; 701 } 702 703 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 704 { 705 cpu_reset(cs); 706 } 707 708 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 709 { 710 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 711 712 scc->cpu_reset(cs); 713 } 714 715 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 716 { 717 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 718 719 scc->initial_cpu_reset(cs); 720 } 721 722 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 723 { 724 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 725 726 scc->load_normal(cs); 727 } 728 729 730 /* cpu.c */ 731 void s390_crypto_reset(void); 732 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 733 void s390_cmma_reset(void); 734 void s390_enable_css_support(S390CPU *cpu); 735 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 736 int vq, bool assign); 737 #ifndef CONFIG_USER_ONLY 738 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 739 #else 740 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 741 { 742 return 0; 743 } 744 #endif /* CONFIG_USER_ONLY */ 745 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 746 { 747 return cpu->env.cpu_state; 748 } 749 750 751 /* cpu_models.c */ 752 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); 753 #define cpu_list s390_cpu_list 754 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 755 const S390FeatInit feat_init); 756 757 758 /* helper.c */ 759 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 760 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 761 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 762 763 /* you can call this signal handler from your SIGBUS and SIGSEGV 764 signal handlers to inform the virtual CPU of exceptions. non zero 765 is returned if the signal was handled by the virtual CPU. */ 766 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 767 #define cpu_signal_handler cpu_s390x_signal_handler 768 769 770 /* interrupt.c */ 771 void s390_crw_mchk(void); 772 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 773 uint32_t io_int_parm, uint32_t io_int_word); 774 /* automatically detect the instruction length */ 775 #define ILEN_AUTO 0xff 776 #define RA_IGNORED 0 777 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, 778 uintptr_t ra); 779 /* service interrupts are floating therefore we must not pass an cpustate */ 780 void s390_sclp_extint(uint32_t parm); 781 782 /* mmu_helper.c */ 783 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 784 int len, bool is_write); 785 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 786 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 787 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 788 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 789 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 790 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 791 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 792 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 793 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 794 795 796 /* sigp.c */ 797 int s390_cpu_restart(S390CPU *cpu); 798 void s390_init_sigp(void); 799 800 801 /* outside of target/s390x/ */ 802 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 803 804 #endif 805