1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * Contributions after 2012-10-29 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 * 19 * You should have received a copy of the GNU (Lesser) General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef S390X_CPU_H 24 #define S390X_CPU_H 25 26 #include "qemu-common.h" 27 #include "cpu-qom.h" 28 29 #define TARGET_LONG_BITS 64 30 31 #define ELF_MACHINE_UNAME "S390X" 32 33 #define CPUArchState struct CPUS390XState 34 35 #include "exec/cpu-defs.h" 36 #define TARGET_PAGE_BITS 12 37 38 #define TARGET_PHYS_ADDR_SPACE_BITS 64 39 #define TARGET_VIRT_ADDR_SPACE_BITS 64 40 41 #include "exec/cpu-all.h" 42 43 #include "fpu/softfloat.h" 44 45 #define NB_MMU_MODES 3 46 #define TARGET_INSN_START_EXTRA_WORDS 1 47 48 #define MMU_MODE0_SUFFIX _primary 49 #define MMU_MODE1_SUFFIX _secondary 50 #define MMU_MODE2_SUFFIX _home 51 52 #define MMU_USER_IDX 0 53 54 #define MAX_EXT_QUEUE 16 55 #define MAX_IO_QUEUE 16 56 #define MAX_MCHK_QUEUE 16 57 58 #define PSW_MCHK_MASK 0x0004000000000000 59 #define PSW_IO_MASK 0x0200000000000000 60 61 typedef struct PSW { 62 uint64_t mask; 63 uint64_t addr; 64 } PSW; 65 66 typedef struct ExtQueue { 67 uint32_t code; 68 uint32_t param; 69 uint32_t param64; 70 } ExtQueue; 71 72 typedef struct IOIntQueue { 73 uint16_t id; 74 uint16_t nr; 75 uint32_t parm; 76 uint32_t word; 77 } IOIntQueue; 78 79 typedef struct MchkQueue { 80 uint16_t type; 81 } MchkQueue; 82 83 typedef struct CPUS390XState { 84 uint64_t regs[16]; /* GP registers */ 85 /* 86 * The floating point registers are part of the vector registers. 87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 88 */ 89 CPU_DoubleU vregs[32][2]; /* vector registers */ 90 uint32_t aregs[16]; /* access registers */ 91 uint8_t riccb[64]; /* runtime instrumentation control */ 92 uint64_t gscb[4]; /* guarded storage control */ 93 94 /* Fields up to this point are not cleared by initial CPU reset */ 95 struct {} start_initial_reset_fields; 96 97 uint32_t fpc; /* floating-point control register */ 98 uint32_t cc_op; 99 100 float_status fpu_status; /* passed to softfloat lib */ 101 102 /* The low part of a 128-bit return, or remainder of a divide. */ 103 uint64_t retxl; 104 105 PSW psw; 106 107 uint64_t cc_src; 108 uint64_t cc_dst; 109 uint64_t cc_vr; 110 111 uint64_t ex_value; 112 113 uint64_t __excp_addr; 114 uint64_t psa; 115 116 uint32_t int_pgm_code; 117 uint32_t int_pgm_ilen; 118 119 uint32_t int_svc_code; 120 uint32_t int_svc_ilen; 121 122 uint64_t per_address; 123 uint16_t per_perc_atmid; 124 125 uint64_t cregs[16]; /* control registers */ 126 127 ExtQueue ext_queue[MAX_EXT_QUEUE]; 128 IOIntQueue io_queue[MAX_IO_QUEUE][8]; 129 MchkQueue mchk_queue[MAX_MCHK_QUEUE]; 130 131 int pending_int; 132 int ext_index; 133 int io_index[8]; 134 int mchk_index; 135 136 uint64_t ckc; 137 uint64_t cputm; 138 uint32_t todpr; 139 140 uint64_t pfault_token; 141 uint64_t pfault_compare; 142 uint64_t pfault_select; 143 144 uint64_t gbea; 145 uint64_t pp; 146 147 /* Fields up to this point are cleared by a CPU reset */ 148 struct {} end_reset_fields; 149 150 CPU_COMMON 151 152 uint32_t cpu_num; 153 uint64_t cpuid; 154 155 uint64_t tod_offset; 156 uint64_t tod_basetime; 157 QEMUTimer *tod_timer; 158 159 QEMUTimer *cpu_timer; 160 161 /* 162 * The cpu state represents the logical state of a cpu. In contrast to other 163 * architectures, there is a difference between a halt and a stop on s390. 164 * If all cpus are either stopped (including check stop) or in the disabled 165 * wait state, the vm can be shut down. 166 */ 167 #define CPU_STATE_UNINITIALIZED 0x00 168 #define CPU_STATE_STOPPED 0x01 169 #define CPU_STATE_CHECK_STOP 0x02 170 #define CPU_STATE_OPERATING 0x03 171 #define CPU_STATE_LOAD 0x04 172 uint8_t cpu_state; 173 174 /* currently processed sigp order */ 175 uint8_t sigp_order; 176 177 } CPUS390XState; 178 179 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) 180 { 181 return &cs->vregs[nr][0]; 182 } 183 184 /** 185 * S390CPU: 186 * @env: #CPUS390XState. 187 * 188 * An S/390 CPU. 189 */ 190 struct S390CPU { 191 /*< private >*/ 192 CPUState parent_obj; 193 /*< public >*/ 194 195 CPUS390XState env; 196 int64_t id; 197 S390CPUModel *model; 198 /* needed for live migration */ 199 void *irqstate; 200 uint32_t irqstate_saved_size; 201 }; 202 203 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) 204 { 205 return container_of(env, S390CPU, env); 206 } 207 208 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) 209 210 #define ENV_OFFSET offsetof(S390CPU, env) 211 212 #ifndef CONFIG_USER_ONLY 213 extern const struct VMStateDescription vmstate_s390_cpu; 214 #endif 215 216 /* distinguish between 24 bit and 31 bit addressing */ 217 #define HIGH_ORDER_BIT 0x80000000 218 219 /* Interrupt Codes */ 220 /* Program Interrupts */ 221 #define PGM_OPERATION 0x0001 222 #define PGM_PRIVILEGED 0x0002 223 #define PGM_EXECUTE 0x0003 224 #define PGM_PROTECTION 0x0004 225 #define PGM_ADDRESSING 0x0005 226 #define PGM_SPECIFICATION 0x0006 227 #define PGM_DATA 0x0007 228 #define PGM_FIXPT_OVERFLOW 0x0008 229 #define PGM_FIXPT_DIVIDE 0x0009 230 #define PGM_DEC_OVERFLOW 0x000a 231 #define PGM_DEC_DIVIDE 0x000b 232 #define PGM_HFP_EXP_OVERFLOW 0x000c 233 #define PGM_HFP_EXP_UNDERFLOW 0x000d 234 #define PGM_HFP_SIGNIFICANCE 0x000e 235 #define PGM_HFP_DIVIDE 0x000f 236 #define PGM_SEGMENT_TRANS 0x0010 237 #define PGM_PAGE_TRANS 0x0011 238 #define PGM_TRANS_SPEC 0x0012 239 #define PGM_SPECIAL_OP 0x0013 240 #define PGM_OPERAND 0x0015 241 #define PGM_TRACE_TABLE 0x0016 242 #define PGM_SPACE_SWITCH 0x001c 243 #define PGM_HFP_SQRT 0x001d 244 #define PGM_PC_TRANS_SPEC 0x001f 245 #define PGM_AFX_TRANS 0x0020 246 #define PGM_ASX_TRANS 0x0021 247 #define PGM_LX_TRANS 0x0022 248 #define PGM_EX_TRANS 0x0023 249 #define PGM_PRIM_AUTH 0x0024 250 #define PGM_SEC_AUTH 0x0025 251 #define PGM_ALET_SPEC 0x0028 252 #define PGM_ALEN_SPEC 0x0029 253 #define PGM_ALE_SEQ 0x002a 254 #define PGM_ASTE_VALID 0x002b 255 #define PGM_ASTE_SEQ 0x002c 256 #define PGM_EXT_AUTH 0x002d 257 #define PGM_STACK_FULL 0x0030 258 #define PGM_STACK_EMPTY 0x0031 259 #define PGM_STACK_SPEC 0x0032 260 #define PGM_STACK_TYPE 0x0033 261 #define PGM_STACK_OP 0x0034 262 #define PGM_ASCE_TYPE 0x0038 263 #define PGM_REG_FIRST_TRANS 0x0039 264 #define PGM_REG_SEC_TRANS 0x003a 265 #define PGM_REG_THIRD_TRANS 0x003b 266 #define PGM_MONITOR 0x0040 267 #define PGM_PER 0x0080 268 #define PGM_CRYPTO 0x0119 269 270 /* External Interrupts */ 271 #define EXT_INTERRUPT_KEY 0x0040 272 #define EXT_CLOCK_COMP 0x1004 273 #define EXT_CPU_TIMER 0x1005 274 #define EXT_MALFUNCTION 0x1200 275 #define EXT_EMERGENCY 0x1201 276 #define EXT_EXTERNAL_CALL 0x1202 277 #define EXT_ETR 0x1406 278 #define EXT_SERVICE 0x2401 279 #define EXT_VIRTIO 0x2603 280 281 /* PSW defines */ 282 #undef PSW_MASK_PER 283 #undef PSW_MASK_DAT 284 #undef PSW_MASK_IO 285 #undef PSW_MASK_EXT 286 #undef PSW_MASK_KEY 287 #undef PSW_SHIFT_KEY 288 #undef PSW_MASK_MCHECK 289 #undef PSW_MASK_WAIT 290 #undef PSW_MASK_PSTATE 291 #undef PSW_MASK_ASC 292 #undef PSW_SHIFT_ASC 293 #undef PSW_MASK_CC 294 #undef PSW_MASK_PM 295 #undef PSW_MASK_64 296 #undef PSW_MASK_32 297 #undef PSW_MASK_ESA_ADDR 298 299 #define PSW_MASK_PER 0x4000000000000000ULL 300 #define PSW_MASK_DAT 0x0400000000000000ULL 301 #define PSW_MASK_IO 0x0200000000000000ULL 302 #define PSW_MASK_EXT 0x0100000000000000ULL 303 #define PSW_MASK_KEY 0x00F0000000000000ULL 304 #define PSW_SHIFT_KEY 52 305 #define PSW_MASK_MCHECK 0x0004000000000000ULL 306 #define PSW_MASK_WAIT 0x0002000000000000ULL 307 #define PSW_MASK_PSTATE 0x0001000000000000ULL 308 #define PSW_MASK_ASC 0x0000C00000000000ULL 309 #define PSW_SHIFT_ASC 46 310 #define PSW_MASK_CC 0x0000300000000000ULL 311 #define PSW_MASK_PM 0x00000F0000000000ULL 312 #define PSW_MASK_64 0x0000000100000000ULL 313 #define PSW_MASK_32 0x0000000080000000ULL 314 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 315 316 #undef PSW_ASC_PRIMARY 317 #undef PSW_ASC_ACCREG 318 #undef PSW_ASC_SECONDARY 319 #undef PSW_ASC_HOME 320 321 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 322 #define PSW_ASC_ACCREG 0x0000400000000000ULL 323 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 324 #define PSW_ASC_HOME 0x0000C00000000000ULL 325 326 /* the address space values shifted */ 327 #define AS_PRIMARY 0 328 #define AS_ACCREG 1 329 #define AS_SECONDARY 2 330 #define AS_HOME 3 331 332 /* tb flags */ 333 334 #define FLAG_MASK_PSW_SHIFT 31 335 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 336 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 337 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 338 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 339 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 340 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \ 341 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 342 343 /* Control register 0 bits */ 344 #define CR0_LOWPROT 0x0000000010000000ULL 345 #define CR0_SECONDARY 0x0000000004000000ULL 346 #define CR0_EDAT 0x0000000000800000ULL 347 348 /* MMU */ 349 #define MMU_PRIMARY_IDX 0 350 #define MMU_SECONDARY_IDX 1 351 #define MMU_HOME_IDX 2 352 353 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 354 { 355 switch (env->psw.mask & PSW_MASK_ASC) { 356 case PSW_ASC_PRIMARY: 357 return MMU_PRIMARY_IDX; 358 case PSW_ASC_SECONDARY: 359 return MMU_SECONDARY_IDX; 360 case PSW_ASC_HOME: 361 return MMU_HOME_IDX; 362 case PSW_ASC_ACCREG: 363 /* Fallthrough: access register mode is not yet supported */ 364 default: 365 abort(); 366 } 367 } 368 369 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 370 target_ulong *cs_base, uint32_t *flags) 371 { 372 *pc = env->psw.addr; 373 *cs_base = env->ex_value; 374 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 375 } 376 377 /* PER bits from control register 9 */ 378 #define PER_CR9_EVENT_BRANCH 0x80000000 379 #define PER_CR9_EVENT_IFETCH 0x40000000 380 #define PER_CR9_EVENT_STORE 0x20000000 381 #define PER_CR9_EVENT_STORE_REAL 0x08000000 382 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 383 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 384 #define PER_CR9_CONTROL_ALTERATION 0x00200000 385 386 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 387 #define PER_CODE_EVENT_BRANCH 0x8000 388 #define PER_CODE_EVENT_IFETCH 0x4000 389 #define PER_CODE_EVENT_STORE 0x2000 390 #define PER_CODE_EVENT_STORE_REAL 0x0800 391 #define PER_CODE_EVENT_NULLIFICATION 0x0100 392 393 #define EXCP_EXT 1 /* external interrupt */ 394 #define EXCP_SVC 2 /* supervisor call (syscall) */ 395 #define EXCP_PGM 3 /* program interruption */ 396 #define EXCP_IO 7 /* I/O interrupt */ 397 #define EXCP_MCHK 8 /* machine check */ 398 399 #define INTERRUPT_EXT (1 << 0) 400 #define INTERRUPT_TOD (1 << 1) 401 #define INTERRUPT_CPUTIMER (1 << 2) 402 #define INTERRUPT_IO (1 << 3) 403 #define INTERRUPT_MCHK (1 << 4) 404 405 /* Program Status Word. */ 406 #define S390_PSWM_REGNUM 0 407 #define S390_PSWA_REGNUM 1 408 /* General Purpose Registers. */ 409 #define S390_R0_REGNUM 2 410 #define S390_R1_REGNUM 3 411 #define S390_R2_REGNUM 4 412 #define S390_R3_REGNUM 5 413 #define S390_R4_REGNUM 6 414 #define S390_R5_REGNUM 7 415 #define S390_R6_REGNUM 8 416 #define S390_R7_REGNUM 9 417 #define S390_R8_REGNUM 10 418 #define S390_R9_REGNUM 11 419 #define S390_R10_REGNUM 12 420 #define S390_R11_REGNUM 13 421 #define S390_R12_REGNUM 14 422 #define S390_R13_REGNUM 15 423 #define S390_R14_REGNUM 16 424 #define S390_R15_REGNUM 17 425 /* Total Core Registers. */ 426 #define S390_NUM_CORE_REGS 18 427 428 static inline void setcc(S390CPU *cpu, uint64_t cc) 429 { 430 CPUS390XState *env = &cpu->env; 431 432 env->psw.mask &= ~(3ull << 44); 433 env->psw.mask |= (cc & 3) << 44; 434 env->cc_op = cc; 435 } 436 437 /* STSI */ 438 #define STSI_LEVEL_MASK 0x00000000f0000000ULL 439 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL 440 #define STSI_LEVEL_1 0x0000000010000000ULL 441 #define STSI_LEVEL_2 0x0000000020000000ULL 442 #define STSI_LEVEL_3 0x0000000030000000ULL 443 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 444 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 445 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 446 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 447 448 /* Basic Machine Configuration */ 449 struct sysib_111 { 450 uint32_t res1[8]; 451 uint8_t manuf[16]; 452 uint8_t type[4]; 453 uint8_t res2[12]; 454 uint8_t model[16]; 455 uint8_t sequence[16]; 456 uint8_t plant[4]; 457 uint8_t res3[156]; 458 }; 459 460 /* Basic Machine CPU */ 461 struct sysib_121 { 462 uint32_t res1[80]; 463 uint8_t sequence[16]; 464 uint8_t plant[4]; 465 uint8_t res2[2]; 466 uint16_t cpu_addr; 467 uint8_t res3[152]; 468 }; 469 470 /* Basic Machine CPUs */ 471 struct sysib_122 { 472 uint8_t res1[32]; 473 uint32_t capability; 474 uint16_t total_cpus; 475 uint16_t active_cpus; 476 uint16_t standby_cpus; 477 uint16_t reserved_cpus; 478 uint16_t adjustments[2026]; 479 }; 480 481 /* LPAR CPU */ 482 struct sysib_221 { 483 uint32_t res1[80]; 484 uint8_t sequence[16]; 485 uint8_t plant[4]; 486 uint16_t cpu_id; 487 uint16_t cpu_addr; 488 uint8_t res3[152]; 489 }; 490 491 /* LPAR CPUs */ 492 struct sysib_222 { 493 uint32_t res1[32]; 494 uint16_t lpar_num; 495 uint8_t res2; 496 uint8_t lcpuc; 497 uint16_t total_cpus; 498 uint16_t conf_cpus; 499 uint16_t standby_cpus; 500 uint16_t reserved_cpus; 501 uint8_t name[8]; 502 uint32_t caf; 503 uint8_t res3[16]; 504 uint16_t dedicated_cpus; 505 uint16_t shared_cpus; 506 uint8_t res4[180]; 507 }; 508 509 /* VM CPUs */ 510 struct sysib_322 { 511 uint8_t res1[31]; 512 uint8_t count; 513 struct { 514 uint8_t res2[4]; 515 uint16_t total_cpus; 516 uint16_t conf_cpus; 517 uint16_t standby_cpus; 518 uint16_t reserved_cpus; 519 uint8_t name[8]; 520 uint32_t caf; 521 uint8_t cpi[16]; 522 uint8_t res5[3]; 523 uint8_t ext_name_encoding; 524 uint32_t res3; 525 uint8_t uuid[16]; 526 } vm[8]; 527 uint8_t res4[1504]; 528 uint8_t ext_names[8][256]; 529 }; 530 531 /* MMU defines */ 532 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ 533 #define _ASCE_SUBSPACE 0x200 /* subspace group control */ 534 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 535 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 536 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 537 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 538 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 539 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 540 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 541 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 542 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 543 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 544 545 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ 546 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 547 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 548 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 549 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 550 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 551 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 552 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 553 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 554 555 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ 556 #define _SEGMENT_ENTRY_FC 0x400 /* format control */ 557 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 558 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 559 560 #define VADDR_PX 0xff000 /* page index bits */ 561 562 #define _PAGE_RO 0x200 /* HW read-only bit */ 563 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 564 #define _PAGE_RES0 0x800 /* bit must be zero */ 565 566 #define SK_C (0x1 << 1) 567 #define SK_R (0x1 << 2) 568 #define SK_F (0x1 << 3) 569 #define SK_ACC_MASK (0xf << 4) 570 571 /* SIGP order codes */ 572 #define SIGP_SENSE 0x01 573 #define SIGP_EXTERNAL_CALL 0x02 574 #define SIGP_EMERGENCY 0x03 575 #define SIGP_START 0x04 576 #define SIGP_STOP 0x05 577 #define SIGP_RESTART 0x06 578 #define SIGP_STOP_STORE_STATUS 0x09 579 #define SIGP_INITIAL_CPU_RESET 0x0b 580 #define SIGP_CPU_RESET 0x0c 581 #define SIGP_SET_PREFIX 0x0d 582 #define SIGP_STORE_STATUS_ADDR 0x0e 583 #define SIGP_SET_ARCH 0x12 584 #define SIGP_STORE_ADTL_STATUS 0x17 585 586 /* SIGP condition codes */ 587 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 588 #define SIGP_CC_STATUS_STORED 1 589 #define SIGP_CC_BUSY 2 590 #define SIGP_CC_NOT_OPERATIONAL 3 591 592 /* SIGP status bits */ 593 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 594 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 595 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 596 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 597 #define SIGP_STAT_STOPPED 0x00000040UL 598 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 599 #define SIGP_STAT_CHECK_STOP 0x00000010UL 600 #define SIGP_STAT_INOPERATIVE 0x00000004UL 601 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 602 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 603 604 /* SIGP SET ARCHITECTURE modes */ 605 #define SIGP_MODE_ESA_S390 0 606 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 607 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 608 609 /* SIGP order code mask corresponding to bit positions 56-63 */ 610 #define SIGP_ORDER_MASK 0x000000ff 611 612 /* from s390-virtio-ccw */ 613 #define MEM_SECTION_SIZE 0x10000000UL 614 #define MAX_AVAIL_SLOTS 32 615 616 /* machine check interruption code */ 617 618 /* subclasses */ 619 #define MCIC_SC_SD 0x8000000000000000ULL 620 #define MCIC_SC_PD 0x4000000000000000ULL 621 #define MCIC_SC_SR 0x2000000000000000ULL 622 #define MCIC_SC_CD 0x0800000000000000ULL 623 #define MCIC_SC_ED 0x0400000000000000ULL 624 #define MCIC_SC_DG 0x0100000000000000ULL 625 #define MCIC_SC_W 0x0080000000000000ULL 626 #define MCIC_SC_CP 0x0040000000000000ULL 627 #define MCIC_SC_SP 0x0020000000000000ULL 628 #define MCIC_SC_CK 0x0010000000000000ULL 629 630 /* subclass modifiers */ 631 #define MCIC_SCM_B 0x0002000000000000ULL 632 #define MCIC_SCM_DA 0x0000000020000000ULL 633 #define MCIC_SCM_AP 0x0000000000080000ULL 634 635 /* storage errors */ 636 #define MCIC_SE_SE 0x0000800000000000ULL 637 #define MCIC_SE_SC 0x0000400000000000ULL 638 #define MCIC_SE_KE 0x0000200000000000ULL 639 #define MCIC_SE_DS 0x0000100000000000ULL 640 #define MCIC_SE_IE 0x0000000080000000ULL 641 642 /* validity bits */ 643 #define MCIC_VB_WP 0x0000080000000000ULL 644 #define MCIC_VB_MS 0x0000040000000000ULL 645 #define MCIC_VB_PM 0x0000020000000000ULL 646 #define MCIC_VB_IA 0x0000010000000000ULL 647 #define MCIC_VB_FA 0x0000008000000000ULL 648 #define MCIC_VB_VR 0x0000004000000000ULL 649 #define MCIC_VB_EC 0x0000002000000000ULL 650 #define MCIC_VB_FP 0x0000001000000000ULL 651 #define MCIC_VB_GR 0x0000000800000000ULL 652 #define MCIC_VB_CR 0x0000000400000000ULL 653 #define MCIC_VB_ST 0x0000000100000000ULL 654 #define MCIC_VB_AR 0x0000000040000000ULL 655 #define MCIC_VB_GS 0x0000000008000000ULL 656 #define MCIC_VB_PR 0x0000000000200000ULL 657 #define MCIC_VB_FC 0x0000000000100000ULL 658 #define MCIC_VB_CT 0x0000000000020000ULL 659 #define MCIC_VB_CC 0x0000000000010000ULL 660 661 662 /* cpu.c */ 663 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low); 664 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low); 665 void s390_crypto_reset(void); 666 bool s390_get_squash_mcss(void); 667 int s390_get_memslot_count(void); 668 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 669 void s390_cmma_reset(void); 670 int s390_cpu_restart(S390CPU *cpu); 671 void s390_enable_css_support(S390CPU *cpu); 672 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 673 int vq, bool assign); 674 #ifndef CONFIG_USER_ONLY 675 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 676 #else 677 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 678 { 679 return 0; 680 } 681 #endif /* CONFIG_USER_ONLY */ 682 683 684 /* cpu_models.c */ 685 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); 686 #define cpu_list s390_cpu_list 687 const char *s390_default_cpu_model_name(void); 688 689 690 /* helper.c */ 691 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model) 692 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp); 693 /* you can call this signal handler from your SIGBUS and SIGSEGV 694 signal handlers to inform the virtual CPU of exceptions. non zero 695 is returned if the signal was handled by the virtual CPU. */ 696 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 697 #define cpu_signal_handler cpu_s390x_signal_handler 698 699 700 /* interrupt.c */ 701 void s390_crw_mchk(void); 702 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 703 uint32_t io_int_parm, uint32_t io_int_word); 704 /* automatically detect the instruction length */ 705 #define ILEN_AUTO 0xff 706 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen); 707 /* service interrupts are floating therefore we must not pass an cpustate */ 708 void s390_sclp_extint(uint32_t parm); 709 710 711 /* mmu_helper.c */ 712 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 713 int len, bool is_write); 714 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 715 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 716 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 717 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 718 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 719 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 720 721 722 /* outside of target/s390x/ */ 723 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 724 extern void subsystem_reset(void); 725 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code); 726 int s390_virtio_hypercall(CPUS390XState *env); 727 728 #endif 729