1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 #include "exec/cpu-interrupt.h" 32 #include "qemu/cpu-float.h" 33 #include "qapi/qapi-types-machine-common.h" 34 35 #define ELF_MACHINE_UNAME "S390X" 36 37 #define TARGET_HAS_PRECISE_SMC 38 39 #define TARGET_INSN_START_EXTRA_WORDS 2 40 41 #define MMU_USER_IDX 0 42 43 #define S390_MAX_CPUS 248 44 45 #ifndef CONFIG_KVM 46 #define S390_ADAPTER_SUPPRESSIBLE 0x01 47 #else 48 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE 49 #endif 50 51 typedef struct PSW { 52 uint64_t mask; 53 uint64_t addr; 54 } PSW; 55 56 typedef struct CPUArchState { 57 uint64_t regs[16]; /* GP registers */ 58 /* 59 * The floating point registers are part of the vector registers. 60 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 61 */ 62 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 63 uint32_t aregs[16]; /* access registers */ 64 uint64_t gscb[4]; /* guarded storage control */ 65 uint64_t etoken; /* etoken */ 66 uint64_t etoken_extension; /* etoken extension */ 67 68 uint64_t diag318_info; 69 70 /* Fields up to this point are not cleared by initial CPU reset */ 71 struct {} start_initial_reset_fields; 72 73 uint32_t fpc; /* floating-point control register */ 74 uint32_t cc_op; 75 bool bpbc; /* branch prediction blocking */ 76 77 float_status fpu_status; /* passed to softfloat lib */ 78 79 PSW psw; 80 81 S390CrashReason crash_reason; 82 83 uint64_t cc_src; 84 uint64_t cc_dst; 85 uint64_t cc_vr; 86 87 uint64_t ex_value; 88 uint64_t ex_target; 89 90 uint64_t __excp_addr; 91 uint64_t psa; 92 93 uint32_t int_pgm_code; 94 uint32_t int_pgm_ilen; 95 96 uint32_t int_svc_code; 97 uint32_t int_svc_ilen; 98 99 uint64_t per_address; 100 uint16_t per_perc_atmid; 101 102 uint64_t cregs[16]; /* control registers */ 103 104 uint64_t ckc; 105 uint64_t cputm; 106 uint32_t todpr; 107 108 uint64_t pfault_token; 109 uint64_t pfault_compare; 110 uint64_t pfault_select; 111 112 uint64_t gbea; 113 uint64_t pp; 114 115 /* Fields up to this point are not cleared by normal CPU reset */ 116 struct {} start_normal_reset_fields; 117 uint8_t riccb[64]; /* runtime instrumentation control */ 118 119 int pending_int; 120 uint16_t external_call_addr; 121 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 122 123 #if !defined(CONFIG_USER_ONLY) 124 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 125 int tlb_fill_exc; /* exception number seen during tlb_fill */ 126 #endif 127 128 /* Fields up to this point are cleared by a CPU reset */ 129 struct {} end_reset_fields; 130 131 #if !defined(CONFIG_USER_ONLY) 132 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 133 int32_t socket_id; 134 int32_t book_id; 135 int32_t drawer_id; 136 bool dedicated; 137 S390CpuEntitlement entitlement; /* Used only for vertical polarization */ 138 uint64_t cpuid; 139 #endif 140 141 QEMUTimer *tod_timer; 142 143 QEMUTimer *cpu_timer; 144 145 /* 146 * The cpu state represents the logical state of a cpu. In contrast to other 147 * architectures, there is a difference between a halt and a stop on s390. 148 * If all cpus are either stopped (including check stop) or in the disabled 149 * wait state, the vm can be shut down. 150 * The acceptable cpu_state values are defined in the CpuInfoS390State 151 * enum. 152 */ 153 uint8_t cpu_state; 154 155 /* currently processed sigp order */ 156 uint8_t sigp_order; 157 158 } CPUS390XState; 159 160 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 161 { 162 return &cs->vregs[nr][0]; 163 } 164 165 /** 166 * S390CPU: 167 * @env: #CPUS390XState. 168 * 169 * An S/390 CPU. 170 */ 171 struct ArchCPU { 172 CPUState parent_obj; 173 174 CPUS390XState env; 175 S390CPUModel *model; 176 /* needed for live migration */ 177 void *irqstate; 178 uint32_t irqstate_saved_size; 179 }; 180 181 /** 182 * S390CPUClass: 183 * @parent_realize: The parent class' realize handler. 184 * @parent_phases: The parent class' reset phase handlers. 185 * @load_normal: Performs a load normal. 186 * 187 * An S/390 CPU model. 188 */ 189 struct S390CPUClass { 190 CPUClass parent_class; 191 192 const S390CPUDef *cpu_def; 193 bool kvm_required; 194 bool is_static; 195 bool is_migration_safe; 196 const char *desc; 197 198 DeviceRealize parent_realize; 199 ResettablePhases parent_phases; 200 void (*load_normal)(CPUState *cpu); 201 }; 202 203 #ifndef CONFIG_USER_ONLY 204 extern const VMStateDescription vmstate_s390_cpu; 205 #endif 206 207 /* distinguish between 24 bit and 31 bit addressing */ 208 #define HIGH_ORDER_BIT 0x80000000 209 210 /* Interrupt Codes */ 211 /* Program Interrupts */ 212 #define PGM_OPERATION 0x0001 213 #define PGM_PRIVILEGED 0x0002 214 #define PGM_EXECUTE 0x0003 215 #define PGM_PROTECTION 0x0004 216 #define PGM_ADDRESSING 0x0005 217 #define PGM_SPECIFICATION 0x0006 218 #define PGM_DATA 0x0007 219 #define PGM_FIXPT_OVERFLOW 0x0008 220 #define PGM_FIXPT_DIVIDE 0x0009 221 #define PGM_DEC_OVERFLOW 0x000a 222 #define PGM_DEC_DIVIDE 0x000b 223 #define PGM_HFP_EXP_OVERFLOW 0x000c 224 #define PGM_HFP_EXP_UNDERFLOW 0x000d 225 #define PGM_HFP_SIGNIFICANCE 0x000e 226 #define PGM_HFP_DIVIDE 0x000f 227 #define PGM_SEGMENT_TRANS 0x0010 228 #define PGM_PAGE_TRANS 0x0011 229 #define PGM_TRANS_SPEC 0x0012 230 #define PGM_SPECIAL_OP 0x0013 231 #define PGM_OPERAND 0x0015 232 #define PGM_TRACE_TABLE 0x0016 233 #define PGM_VECTOR_PROCESSING 0x001b 234 #define PGM_SPACE_SWITCH 0x001c 235 #define PGM_HFP_SQRT 0x001d 236 #define PGM_PC_TRANS_SPEC 0x001f 237 #define PGM_AFX_TRANS 0x0020 238 #define PGM_ASX_TRANS 0x0021 239 #define PGM_LX_TRANS 0x0022 240 #define PGM_EX_TRANS 0x0023 241 #define PGM_PRIM_AUTH 0x0024 242 #define PGM_SEC_AUTH 0x0025 243 #define PGM_ALET_SPEC 0x0028 244 #define PGM_ALEN_SPEC 0x0029 245 #define PGM_ALE_SEQ 0x002a 246 #define PGM_ASTE_VALID 0x002b 247 #define PGM_ASTE_SEQ 0x002c 248 #define PGM_EXT_AUTH 0x002d 249 #define PGM_STACK_FULL 0x0030 250 #define PGM_STACK_EMPTY 0x0031 251 #define PGM_STACK_SPEC 0x0032 252 #define PGM_STACK_TYPE 0x0033 253 #define PGM_STACK_OP 0x0034 254 #define PGM_ASCE_TYPE 0x0038 255 #define PGM_REG_FIRST_TRANS 0x0039 256 #define PGM_REG_SEC_TRANS 0x003a 257 #define PGM_REG_THIRD_TRANS 0x003b 258 #define PGM_MONITOR 0x0040 259 #define PGM_PER 0x0080 260 #define PGM_CRYPTO 0x0119 261 262 /* External Interrupts */ 263 #define EXT_INTERRUPT_KEY 0x0040 264 #define EXT_CLOCK_COMP 0x1004 265 #define EXT_CPU_TIMER 0x1005 266 #define EXT_MALFUNCTION 0x1200 267 #define EXT_EMERGENCY 0x1201 268 #define EXT_EXTERNAL_CALL 0x1202 269 #define EXT_ETR 0x1406 270 #define EXT_SERVICE 0x2401 271 #define EXT_VIRTIO 0x2603 272 273 /* PSW defines */ 274 #undef PSW_MASK_PER 275 #undef PSW_MASK_UNUSED_2 276 #undef PSW_MASK_UNUSED_3 277 #undef PSW_MASK_DAT 278 #undef PSW_MASK_IO 279 #undef PSW_MASK_EXT 280 #undef PSW_MASK_KEY 281 #undef PSW_SHIFT_KEY 282 #undef PSW_MASK_MCHECK 283 #undef PSW_MASK_WAIT 284 #undef PSW_MASK_PSTATE 285 #undef PSW_MASK_ASC 286 #undef PSW_SHIFT_ASC 287 #undef PSW_MASK_CC 288 #undef PSW_MASK_PM 289 #undef PSW_MASK_RI 290 #undef PSW_SHIFT_MASK_PM 291 #undef PSW_MASK_64 292 #undef PSW_MASK_32 293 #undef PSW_MASK_ESA_ADDR 294 295 #define PSW_MASK_PER 0x4000000000000000ULL 296 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 297 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 298 #define PSW_MASK_DAT 0x0400000000000000ULL 299 #define PSW_MASK_IO 0x0200000000000000ULL 300 #define PSW_MASK_EXT 0x0100000000000000ULL 301 #define PSW_MASK_KEY 0x00F0000000000000ULL 302 #define PSW_SHIFT_KEY 52 303 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 304 #define PSW_MASK_MCHECK 0x0004000000000000ULL 305 #define PSW_MASK_WAIT 0x0002000000000000ULL 306 #define PSW_MASK_PSTATE 0x0001000000000000ULL 307 #define PSW_MASK_ASC 0x0000C00000000000ULL 308 #define PSW_SHIFT_ASC 46 309 #define PSW_MASK_CC 0x0000300000000000ULL 310 #define PSW_MASK_PM 0x00000F0000000000ULL 311 #define PSW_SHIFT_MASK_PM 40 312 #define PSW_MASK_RI 0x0000008000000000ULL 313 #define PSW_MASK_64 0x0000000100000000ULL 314 #define PSW_MASK_32 0x0000000080000000ULL 315 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 316 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 317 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL 318 319 #undef PSW_ASC_PRIMARY 320 #undef PSW_ASC_ACCREG 321 #undef PSW_ASC_SECONDARY 322 #undef PSW_ASC_HOME 323 324 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 325 #define PSW_ASC_ACCREG 0x0000400000000000ULL 326 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 327 #define PSW_ASC_HOME 0x0000C00000000000ULL 328 329 /* the address space values shifted */ 330 #define AS_PRIMARY 0 331 #define AS_ACCREG 1 332 #define AS_SECONDARY 2 333 #define AS_HOME 3 334 335 /* tb flags */ 336 337 #define FLAG_MASK_PSW_SHIFT 31 338 #define FLAG_MASK_32 0x00000001u 339 #define FLAG_MASK_64 0x00000002u 340 #define FLAG_MASK_AFP 0x00000004u 341 #define FLAG_MASK_VECTOR 0x00000008u 342 #define FLAG_MASK_ASC 0x00018000u 343 #define FLAG_MASK_PSTATE 0x00020000u 344 #define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u 345 #define FLAG_MASK_DAT 0x08000000u 346 #define FLAG_MASK_PER_STORE_REAL 0x20000000u 347 #define FLAG_MASK_PER_IFETCH 0x40000000u 348 #define FLAG_MASK_PER_BRANCH 0x80000000u 349 350 QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT); 351 QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT); 352 QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT); 353 QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT); 354 QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT); 355 356 #define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \ 357 FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 358 #define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH) 359 #define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \ 360 FLAG_MASK_PER_IFETCH | \ 361 FLAG_MASK_PER_IFETCH_NULLIFY | \ 362 FLAG_MASK_PER_STORE_REAL) 363 364 /* Control register 0 bits */ 365 #define CR0_LOWPROT 0x0000000010000000ULL 366 #define CR0_SECONDARY 0x0000000004000000ULL 367 #define CR0_EDAT 0x0000000000800000ULL 368 #define CR0_AFP 0x0000000000040000ULL 369 #define CR0_VECTOR 0x0000000000020000ULL 370 #define CR0_IEP 0x0000000000100000ULL 371 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 372 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 373 #define CR0_CKC_SC 0x0000000000000800ULL 374 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 375 #define CR0_SERVICE_SC 0x0000000000000200ULL 376 377 /* Control register 14 bits */ 378 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 379 380 /* MMU */ 381 #define MMU_PRIMARY_IDX 0 382 #define MMU_SECONDARY_IDX 1 383 #define MMU_HOME_IDX 2 384 #define MMU_REAL_IDX 3 385 386 static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) 387 { 388 #ifdef CONFIG_USER_ONLY 389 return MMU_USER_IDX; 390 #else 391 if (!(env->psw.mask & PSW_MASK_DAT)) { 392 return MMU_REAL_IDX; 393 } 394 395 if (ifetch) { 396 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 397 return MMU_HOME_IDX; 398 } 399 return MMU_PRIMARY_IDX; 400 } 401 402 switch (env->psw.mask & PSW_MASK_ASC) { 403 case PSW_ASC_PRIMARY: 404 return MMU_PRIMARY_IDX; 405 case PSW_ASC_SECONDARY: 406 return MMU_SECONDARY_IDX; 407 case PSW_ASC_HOME: 408 return MMU_HOME_IDX; 409 case PSW_ASC_ACCREG: 410 /* Fallthrough: access register mode is not yet supported */ 411 default: 412 abort(); 413 } 414 #endif 415 } 416 417 #ifdef CONFIG_TCG 418 419 #include "tcg/tcg_s390x.h" 420 421 void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, 422 uint64_t *cs_base, uint32_t *flags); 423 424 #endif /* CONFIG_TCG */ 425 426 /* PER bits from control register 9 */ 427 #define PER_CR9_EVENT_BRANCH 0x80000000 428 #define PER_CR9_EVENT_IFETCH 0x40000000 429 #define PER_CR9_EVENT_STORE 0x20000000 430 #define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000 431 #define PER_CR9_EVENT_STORE_REAL 0x08000000 432 #define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000 433 #define PER_CR9_EVENT_TRANSACTION_END 0x02000000 434 #define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000 435 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 436 #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000 437 #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000 438 439 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH); 440 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH); 441 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY != 442 PER_CR9_EVENT_IFETCH_NULLIFICATION); 443 444 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 445 #define PER_CODE_EVENT_BRANCH 0x8000 446 #define PER_CODE_EVENT_IFETCH 0x4000 447 #define PER_CODE_EVENT_STORE 0x2000 448 #define PER_CODE_EVENT_STORE_REAL 0x0800 449 #define PER_CODE_EVENT_NULLIFICATION 0x0100 450 451 #define EXCP_EXT 1 /* external interrupt */ 452 #define EXCP_SVC 2 /* supervisor call (syscall) */ 453 #define EXCP_PGM 3 /* program interruption */ 454 #define EXCP_RESTART 4 /* restart interrupt */ 455 #define EXCP_STOP 5 /* stop interrupt */ 456 #define EXCP_IO 7 /* I/O interrupt */ 457 #define EXCP_MCHK 8 /* machine check */ 458 459 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 460 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 461 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 462 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 463 #define INTERRUPT_RESTART (1 << 7) 464 #define INTERRUPT_STOP (1 << 8) 465 466 /* Program Status Word. */ 467 #define S390_PSWM_REGNUM 0 468 #define S390_PSWA_REGNUM 1 469 /* General Purpose Registers. */ 470 #define S390_R0_REGNUM 2 471 #define S390_R1_REGNUM 3 472 #define S390_R2_REGNUM 4 473 #define S390_R3_REGNUM 5 474 #define S390_R4_REGNUM 6 475 #define S390_R5_REGNUM 7 476 #define S390_R6_REGNUM 8 477 #define S390_R7_REGNUM 9 478 #define S390_R8_REGNUM 10 479 #define S390_R9_REGNUM 11 480 #define S390_R10_REGNUM 12 481 #define S390_R11_REGNUM 13 482 #define S390_R12_REGNUM 14 483 #define S390_R13_REGNUM 15 484 #define S390_R14_REGNUM 16 485 #define S390_R15_REGNUM 17 486 487 static inline void setcc(S390CPU *cpu, uint64_t cc) 488 { 489 CPUS390XState *env = &cpu->env; 490 491 env->psw.mask &= ~(3ull << 44); 492 env->psw.mask |= (cc & 3) << 44; 493 env->cc_op = cc; 494 } 495 496 /* STSI */ 497 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 498 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 499 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 500 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 501 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 502 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 503 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 504 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 505 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 506 507 /* Basic Machine Configuration */ 508 typedef struct SysIB_111 { 509 uint8_t res1[32]; 510 uint8_t manuf[16]; 511 uint8_t type[4]; 512 uint8_t res2[12]; 513 uint8_t model[16]; 514 uint8_t sequence[16]; 515 uint8_t plant[4]; 516 uint8_t res3[3996]; 517 } SysIB_111; 518 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 519 520 /* Basic Machine CPU */ 521 typedef struct SysIB_121 { 522 uint8_t res1[80]; 523 uint8_t sequence[16]; 524 uint8_t plant[4]; 525 uint8_t res2[2]; 526 uint16_t cpu_addr; 527 uint8_t res3[3992]; 528 } SysIB_121; 529 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 530 531 /* Basic Machine CPUs */ 532 typedef struct SysIB_122 { 533 uint8_t res1[32]; 534 uint32_t capability; 535 uint16_t total_cpus; 536 uint16_t conf_cpus; 537 uint16_t standby_cpus; 538 uint16_t reserved_cpus; 539 uint16_t adjustments[2026]; 540 } SysIB_122; 541 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 542 543 /* LPAR CPU */ 544 typedef struct SysIB_221 { 545 uint8_t res1[80]; 546 uint8_t sequence[16]; 547 uint8_t plant[4]; 548 uint16_t cpu_id; 549 uint16_t cpu_addr; 550 uint8_t res3[3992]; 551 } SysIB_221; 552 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 553 554 /* LPAR CPUs */ 555 typedef struct SysIB_222 { 556 uint8_t res1[32]; 557 uint16_t lpar_num; 558 uint8_t res2; 559 uint8_t lcpuc; 560 uint16_t total_cpus; 561 uint16_t conf_cpus; 562 uint16_t standby_cpus; 563 uint16_t reserved_cpus; 564 uint8_t name[8]; 565 uint32_t caf; 566 uint8_t res3[16]; 567 uint16_t dedicated_cpus; 568 uint16_t shared_cpus; 569 uint8_t res4[4020]; 570 } SysIB_222; 571 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 572 573 /* VM CPUs */ 574 typedef struct SysIB_322 { 575 uint8_t res1[31]; 576 uint8_t count; 577 struct { 578 uint8_t res2[4]; 579 uint16_t total_cpus; 580 uint16_t conf_cpus; 581 uint16_t standby_cpus; 582 uint16_t reserved_cpus; 583 uint8_t name[8]; 584 uint32_t caf; 585 uint8_t cpi[16]; 586 uint8_t res5[3]; 587 uint8_t ext_name_encoding; 588 uint32_t res3; 589 uint8_t uuid[16]; 590 } vm[8]; 591 uint8_t res4[1504]; 592 uint8_t ext_names[8][256]; 593 } SysIB_322; 594 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 595 596 /* 597 * Topology Magnitude fields (MAG) indicates the maximum number of 598 * topology list entries (TLE) at the corresponding nesting level. 599 */ 600 #define S390_TOPOLOGY_MAG 6 601 #define S390_TOPOLOGY_MAG6 0 602 #define S390_TOPOLOGY_MAG5 1 603 #define S390_TOPOLOGY_MAG4 2 604 #define S390_TOPOLOGY_MAG3 3 605 #define S390_TOPOLOGY_MAG2 4 606 #define S390_TOPOLOGY_MAG1 5 607 /* Configuration topology */ 608 typedef struct SysIB_151x { 609 uint8_t reserved0[2]; 610 uint16_t length; 611 uint8_t mag[S390_TOPOLOGY_MAG]; 612 uint8_t reserved1; 613 uint8_t mnest; 614 uint32_t reserved2; 615 char tle[]; 616 } SysIB_151x; 617 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16); 618 619 typedef union SysIB { 620 SysIB_111 sysib_111; 621 SysIB_121 sysib_121; 622 SysIB_122 sysib_122; 623 SysIB_221 sysib_221; 624 SysIB_222 sysib_222; 625 SysIB_322 sysib_322; 626 SysIB_151x sysib_151x; 627 } SysIB; 628 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 629 630 /* 631 * CPU Topology List provided by STSI with fc=15 provides a list 632 * of two different Topology List Entries (TLE) types to specify 633 * the topology hierarchy. 634 * 635 * - Container Topology List Entry 636 * Defines a container to contain other Topology List Entries 637 * of any type, nested containers or CPU. 638 * - CPU Topology List Entry 639 * Specifies the CPUs position, type, entitlement and polarization 640 * of the CPUs contained in the last container TLE. 641 * 642 * There can be theoretically up to five levels of containers, QEMU 643 * uses only three levels, the drawer's, book's and socket's level. 644 * 645 * A container with a nesting level (NL) greater than 1 can only 646 * contain another container of nesting level NL-1. 647 * 648 * A container of nesting level 1 (socket), contains as many CPU TLE 649 * as needed to describe the position and qualities of all CPUs inside 650 * the container. 651 * The qualities of a CPU are polarization, entitlement and type. 652 * 653 * The CPU TLE defines the position of the CPUs of identical qualities 654 * using a 64bits mask which first bit has its offset defined by 655 * the CPU address origin field of the CPU TLE like in: 656 * CPU address = origin * 64 + bit position within the mask 657 */ 658 /* Container type Topology List Entry */ 659 typedef struct SYSIBContainerListEntry { 660 uint8_t nl; 661 uint8_t reserved[6]; 662 uint8_t id; 663 } SYSIBContainerListEntry; 664 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8); 665 666 /* CPU type Topology List Entry */ 667 typedef struct SysIBCPUListEntry { 668 uint8_t nl; 669 uint8_t reserved0[3]; 670 #define SYSIB_TLE_POLARITY_MASK 0x03 671 #define SYSIB_TLE_DEDICATED 0x04 672 uint8_t flags; 673 uint8_t type; 674 uint16_t origin; 675 uint64_t mask; 676 } SysIBCPUListEntry; 677 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16); 678 679 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra); 680 void s390_cpu_topology_set_changed(bool changed); 681 682 /* MMU defines */ 683 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 684 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 685 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 686 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 687 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 688 #define ASCE_REAL_SPACE 0x20 /* real space control */ 689 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 690 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 691 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 692 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 693 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 694 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 695 696 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 697 #define REGION_ENTRY_P 0x0000000000000200ULL 698 #define REGION_ENTRY_TF 0x00000000000000c0ULL 699 #define REGION_ENTRY_I 0x0000000000000020ULL 700 #define REGION_ENTRY_TT 0x000000000000000cULL 701 #define REGION_ENTRY_TL 0x0000000000000003ULL 702 703 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 704 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 705 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 706 707 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 708 #define REGION3_ENTRY_AV 0x0000000000010000ULL 709 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 710 #define REGION3_ENTRY_F 0x0000000000000800ULL 711 #define REGION3_ENTRY_FC 0x0000000000000400ULL 712 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 713 #define REGION3_ENTRY_CR 0x0000000000000010ULL 714 715 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 716 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 717 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 718 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 719 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 720 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 721 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 722 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 723 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 724 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 725 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 726 727 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 728 729 #define PAGE_ENTRY_0 0x0000000000000800ULL 730 #define PAGE_ENTRY_I 0x0000000000000400ULL 731 #define PAGE_ENTRY_P 0x0000000000000200ULL 732 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 733 734 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 735 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 736 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 737 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 738 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 739 740 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 741 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 742 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 743 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 744 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 745 746 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 747 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 748 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 749 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 750 751 #define SK_C (0x1 << 1) 752 #define SK_R (0x1 << 2) 753 #define SK_F (0x1 << 3) 754 #define SK_ACC_MASK (0xf << 4) 755 756 /* SIGP order codes */ 757 #define SIGP_SENSE 0x01 758 #define SIGP_EXTERNAL_CALL 0x02 759 #define SIGP_EMERGENCY 0x03 760 #define SIGP_START 0x04 761 #define SIGP_STOP 0x05 762 #define SIGP_RESTART 0x06 763 #define SIGP_STOP_STORE_STATUS 0x09 764 #define SIGP_INITIAL_CPU_RESET 0x0b 765 #define SIGP_CPU_RESET 0x0c 766 #define SIGP_SET_PREFIX 0x0d 767 #define SIGP_STORE_STATUS_ADDR 0x0e 768 #define SIGP_SET_ARCH 0x12 769 #define SIGP_COND_EMERGENCY 0x13 770 #define SIGP_SENSE_RUNNING 0x15 771 #define SIGP_STORE_ADTL_STATUS 0x17 772 773 /* SIGP condition codes */ 774 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 775 #define SIGP_CC_STATUS_STORED 1 776 #define SIGP_CC_BUSY 2 777 #define SIGP_CC_NOT_OPERATIONAL 3 778 779 /* SIGP status bits */ 780 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 781 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 782 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 783 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 784 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 785 #define SIGP_STAT_STOPPED 0x00000040UL 786 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 787 #define SIGP_STAT_CHECK_STOP 0x00000010UL 788 #define SIGP_STAT_INOPERATIVE 0x00000004UL 789 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 790 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 791 792 /* SIGP order code mask corresponding to bit positions 56-63 */ 793 #define SIGP_ORDER_MASK 0x000000ff 794 795 /* machine check interruption code */ 796 797 /* subclasses */ 798 #define MCIC_SC_SD 0x8000000000000000ULL 799 #define MCIC_SC_PD 0x4000000000000000ULL 800 #define MCIC_SC_SR 0x2000000000000000ULL 801 #define MCIC_SC_CD 0x0800000000000000ULL 802 #define MCIC_SC_ED 0x0400000000000000ULL 803 #define MCIC_SC_DG 0x0100000000000000ULL 804 #define MCIC_SC_W 0x0080000000000000ULL 805 #define MCIC_SC_CP 0x0040000000000000ULL 806 #define MCIC_SC_SP 0x0020000000000000ULL 807 #define MCIC_SC_CK 0x0010000000000000ULL 808 809 /* subclass modifiers */ 810 #define MCIC_SCM_B 0x0002000000000000ULL 811 #define MCIC_SCM_DA 0x0000000020000000ULL 812 #define MCIC_SCM_AP 0x0000000000080000ULL 813 814 /* storage errors */ 815 #define MCIC_SE_SE 0x0000800000000000ULL 816 #define MCIC_SE_SC 0x0000400000000000ULL 817 #define MCIC_SE_KE 0x0000200000000000ULL 818 #define MCIC_SE_DS 0x0000100000000000ULL 819 #define MCIC_SE_IE 0x0000000080000000ULL 820 821 /* validity bits */ 822 #define MCIC_VB_WP 0x0000080000000000ULL 823 #define MCIC_VB_MS 0x0000040000000000ULL 824 #define MCIC_VB_PM 0x0000020000000000ULL 825 #define MCIC_VB_IA 0x0000010000000000ULL 826 #define MCIC_VB_FA 0x0000008000000000ULL 827 #define MCIC_VB_VR 0x0000004000000000ULL 828 #define MCIC_VB_EC 0x0000002000000000ULL 829 #define MCIC_VB_FP 0x0000001000000000ULL 830 #define MCIC_VB_GR 0x0000000800000000ULL 831 #define MCIC_VB_CR 0x0000000400000000ULL 832 #define MCIC_VB_ST 0x0000000100000000ULL 833 #define MCIC_VB_AR 0x0000000040000000ULL 834 #define MCIC_VB_GS 0x0000000008000000ULL 835 #define MCIC_VB_PR 0x0000000000200000ULL 836 #define MCIC_VB_FC 0x0000000000100000ULL 837 #define MCIC_VB_CT 0x0000000000020000ULL 838 #define MCIC_VB_CC 0x0000000000010000ULL 839 840 static inline uint64_t s390_build_validity_mcic(void) 841 { 842 uint64_t mcic; 843 844 /* 845 * Indicate all validity bits (no damage) only. Other bits have to be 846 * added by the caller. (storage errors, subclasses and subclass modifiers) 847 */ 848 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 849 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 850 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 851 if (s390_has_feat(S390_FEAT_VECTOR)) { 852 mcic |= MCIC_VB_VR; 853 } 854 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 855 mcic |= MCIC_VB_GS; 856 } 857 return mcic; 858 } 859 860 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 861 { 862 cpu_reset(cs); 863 } 864 865 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 866 { 867 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL); 868 } 869 870 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 871 { 872 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL); 873 } 874 875 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 876 { 877 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 878 879 scc->load_normal(cs); 880 } 881 882 883 /* cpu.c */ 884 void s390_crypto_reset(void); 885 void s390_cmma_reset(void); 886 void s390_enable_css_support(S390CPU *cpu); 887 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 888 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 889 int vq, bool assign); 890 #ifndef CONFIG_USER_ONLY 891 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 892 #else 893 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 894 { 895 return 0; 896 } 897 #endif /* CONFIG_USER_ONLY */ 898 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 899 { 900 return cpu->env.cpu_state; 901 } 902 903 904 /* cpu_models.c */ 905 void s390_cpu_list(void); 906 #define cpu_list s390_cpu_list 907 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 908 const S390FeatInit feat_init); 909 910 911 /* helper.c */ 912 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 913 914 /* interrupt.c */ 915 #define RA_IGNORED 0 916 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 917 /* service interrupts are floating therefore we must not pass an cpustate */ 918 void s390_sclp_extint(uint32_t parm); 919 920 /* mmu_helper.c */ 921 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 922 int len, bool is_write); 923 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 924 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 925 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 926 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 927 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 928 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 929 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 930 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 931 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 932 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 933 int len, bool is_write); 934 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 935 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 936 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 937 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 938 939 /* sigp.c */ 940 int s390_cpu_restart(S390CPU *cpu); 941 void s390_init_sigp(void); 942 943 /* helper.c */ 944 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); 945 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); 946 947 /* outside of target/s390x/ */ 948 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 949 950 #include "exec/cpu-all.h" 951 952 #endif 953