1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 35 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 36 37 #define TARGET_INSN_START_EXTRA_WORDS 2 38 39 #define MMU_USER_IDX 0 40 41 #define S390_MAX_CPUS 248 42 43 typedef struct PSW { 44 uint64_t mask; 45 uint64_t addr; 46 } PSW; 47 48 struct CPUS390XState { 49 uint64_t regs[16]; /* GP registers */ 50 /* 51 * The floating point registers are part of the vector registers. 52 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 53 */ 54 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 55 uint32_t aregs[16]; /* access registers */ 56 uint64_t gscb[4]; /* guarded storage control */ 57 uint64_t etoken; /* etoken */ 58 uint64_t etoken_extension; /* etoken extension */ 59 60 /* Fields up to this point are not cleared by initial CPU reset */ 61 struct {} start_initial_reset_fields; 62 63 uint32_t fpc; /* floating-point control register */ 64 uint32_t cc_op; 65 bool bpbc; /* branch prediction blocking */ 66 67 float_status fpu_status; /* passed to softfloat lib */ 68 69 /* The low part of a 128-bit return, or remainder of a divide. */ 70 uint64_t retxl; 71 72 PSW psw; 73 74 S390CrashReason crash_reason; 75 76 uint64_t cc_src; 77 uint64_t cc_dst; 78 uint64_t cc_vr; 79 80 uint64_t ex_value; 81 82 uint64_t __excp_addr; 83 uint64_t psa; 84 85 uint32_t int_pgm_code; 86 uint32_t int_pgm_ilen; 87 88 uint32_t int_svc_code; 89 uint32_t int_svc_ilen; 90 91 uint64_t per_address; 92 uint16_t per_perc_atmid; 93 94 uint64_t cregs[16]; /* control registers */ 95 96 uint64_t ckc; 97 uint64_t cputm; 98 uint32_t todpr; 99 100 uint64_t pfault_token; 101 uint64_t pfault_compare; 102 uint64_t pfault_select; 103 104 uint64_t gbea; 105 uint64_t pp; 106 107 /* Fields up to this point are not cleared by normal CPU reset */ 108 struct {} start_normal_reset_fields; 109 uint8_t riccb[64]; /* runtime instrumentation control */ 110 111 int pending_int; 112 uint16_t external_call_addr; 113 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 114 115 uint64_t diag318_info; 116 117 #if !defined(CONFIG_USER_ONLY) 118 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 119 int tlb_fill_exc; /* exception number seen during tlb_fill */ 120 #endif 121 122 /* Fields up to this point are cleared by a CPU reset */ 123 struct {} end_reset_fields; 124 125 #if !defined(CONFIG_USER_ONLY) 126 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 127 uint64_t cpuid; 128 #endif 129 130 QEMUTimer *tod_timer; 131 132 QEMUTimer *cpu_timer; 133 134 /* 135 * The cpu state represents the logical state of a cpu. In contrast to other 136 * architectures, there is a difference between a halt and a stop on s390. 137 * If all cpus are either stopped (including check stop) or in the disabled 138 * wait state, the vm can be shut down. 139 * The acceptable cpu_state values are defined in the CpuInfoS390State 140 * enum. 141 */ 142 uint8_t cpu_state; 143 144 /* currently processed sigp order */ 145 uint8_t sigp_order; 146 147 }; 148 149 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 150 { 151 return &cs->vregs[nr][0]; 152 } 153 154 /** 155 * S390CPU: 156 * @env: #CPUS390XState. 157 * 158 * An S/390 CPU. 159 */ 160 struct S390CPU { 161 /*< private >*/ 162 CPUState parent_obj; 163 /*< public >*/ 164 165 CPUNegativeOffsetState neg; 166 CPUS390XState env; 167 S390CPUModel *model; 168 /* needed for live migration */ 169 void *irqstate; 170 uint32_t irqstate_saved_size; 171 }; 172 173 174 #ifndef CONFIG_USER_ONLY 175 extern const VMStateDescription vmstate_s390_cpu; 176 #endif 177 178 /* distinguish between 24 bit and 31 bit addressing */ 179 #define HIGH_ORDER_BIT 0x80000000 180 181 /* Interrupt Codes */ 182 /* Program Interrupts */ 183 #define PGM_OPERATION 0x0001 184 #define PGM_PRIVILEGED 0x0002 185 #define PGM_EXECUTE 0x0003 186 #define PGM_PROTECTION 0x0004 187 #define PGM_ADDRESSING 0x0005 188 #define PGM_SPECIFICATION 0x0006 189 #define PGM_DATA 0x0007 190 #define PGM_FIXPT_OVERFLOW 0x0008 191 #define PGM_FIXPT_DIVIDE 0x0009 192 #define PGM_DEC_OVERFLOW 0x000a 193 #define PGM_DEC_DIVIDE 0x000b 194 #define PGM_HFP_EXP_OVERFLOW 0x000c 195 #define PGM_HFP_EXP_UNDERFLOW 0x000d 196 #define PGM_HFP_SIGNIFICANCE 0x000e 197 #define PGM_HFP_DIVIDE 0x000f 198 #define PGM_SEGMENT_TRANS 0x0010 199 #define PGM_PAGE_TRANS 0x0011 200 #define PGM_TRANS_SPEC 0x0012 201 #define PGM_SPECIAL_OP 0x0013 202 #define PGM_OPERAND 0x0015 203 #define PGM_TRACE_TABLE 0x0016 204 #define PGM_VECTOR_PROCESSING 0x001b 205 #define PGM_SPACE_SWITCH 0x001c 206 #define PGM_HFP_SQRT 0x001d 207 #define PGM_PC_TRANS_SPEC 0x001f 208 #define PGM_AFX_TRANS 0x0020 209 #define PGM_ASX_TRANS 0x0021 210 #define PGM_LX_TRANS 0x0022 211 #define PGM_EX_TRANS 0x0023 212 #define PGM_PRIM_AUTH 0x0024 213 #define PGM_SEC_AUTH 0x0025 214 #define PGM_ALET_SPEC 0x0028 215 #define PGM_ALEN_SPEC 0x0029 216 #define PGM_ALE_SEQ 0x002a 217 #define PGM_ASTE_VALID 0x002b 218 #define PGM_ASTE_SEQ 0x002c 219 #define PGM_EXT_AUTH 0x002d 220 #define PGM_STACK_FULL 0x0030 221 #define PGM_STACK_EMPTY 0x0031 222 #define PGM_STACK_SPEC 0x0032 223 #define PGM_STACK_TYPE 0x0033 224 #define PGM_STACK_OP 0x0034 225 #define PGM_ASCE_TYPE 0x0038 226 #define PGM_REG_FIRST_TRANS 0x0039 227 #define PGM_REG_SEC_TRANS 0x003a 228 #define PGM_REG_THIRD_TRANS 0x003b 229 #define PGM_MONITOR 0x0040 230 #define PGM_PER 0x0080 231 #define PGM_CRYPTO 0x0119 232 233 /* External Interrupts */ 234 #define EXT_INTERRUPT_KEY 0x0040 235 #define EXT_CLOCK_COMP 0x1004 236 #define EXT_CPU_TIMER 0x1005 237 #define EXT_MALFUNCTION 0x1200 238 #define EXT_EMERGENCY 0x1201 239 #define EXT_EXTERNAL_CALL 0x1202 240 #define EXT_ETR 0x1406 241 #define EXT_SERVICE 0x2401 242 #define EXT_VIRTIO 0x2603 243 244 /* PSW defines */ 245 #undef PSW_MASK_PER 246 #undef PSW_MASK_UNUSED_2 247 #undef PSW_MASK_UNUSED_3 248 #undef PSW_MASK_DAT 249 #undef PSW_MASK_IO 250 #undef PSW_MASK_EXT 251 #undef PSW_MASK_KEY 252 #undef PSW_SHIFT_KEY 253 #undef PSW_MASK_MCHECK 254 #undef PSW_MASK_WAIT 255 #undef PSW_MASK_PSTATE 256 #undef PSW_MASK_ASC 257 #undef PSW_SHIFT_ASC 258 #undef PSW_MASK_CC 259 #undef PSW_MASK_PM 260 #undef PSW_MASK_RI 261 #undef PSW_SHIFT_MASK_PM 262 #undef PSW_MASK_64 263 #undef PSW_MASK_32 264 #undef PSW_MASK_ESA_ADDR 265 266 #define PSW_MASK_PER 0x4000000000000000ULL 267 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 268 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 269 #define PSW_MASK_DAT 0x0400000000000000ULL 270 #define PSW_MASK_IO 0x0200000000000000ULL 271 #define PSW_MASK_EXT 0x0100000000000000ULL 272 #define PSW_MASK_KEY 0x00F0000000000000ULL 273 #define PSW_SHIFT_KEY 52 274 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 275 #define PSW_MASK_MCHECK 0x0004000000000000ULL 276 #define PSW_MASK_WAIT 0x0002000000000000ULL 277 #define PSW_MASK_PSTATE 0x0001000000000000ULL 278 #define PSW_MASK_ASC 0x0000C00000000000ULL 279 #define PSW_SHIFT_ASC 46 280 #define PSW_MASK_CC 0x0000300000000000ULL 281 #define PSW_MASK_PM 0x00000F0000000000ULL 282 #define PSW_SHIFT_MASK_PM 40 283 #define PSW_MASK_RI 0x0000008000000000ULL 284 #define PSW_MASK_64 0x0000000100000000ULL 285 #define PSW_MASK_32 0x0000000080000000ULL 286 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 287 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 288 289 #undef PSW_ASC_PRIMARY 290 #undef PSW_ASC_ACCREG 291 #undef PSW_ASC_SECONDARY 292 #undef PSW_ASC_HOME 293 294 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 295 #define PSW_ASC_ACCREG 0x0000400000000000ULL 296 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 297 #define PSW_ASC_HOME 0x0000C00000000000ULL 298 299 /* the address space values shifted */ 300 #define AS_PRIMARY 0 301 #define AS_ACCREG 1 302 #define AS_SECONDARY 2 303 #define AS_HOME 3 304 305 /* tb flags */ 306 307 #define FLAG_MASK_PSW_SHIFT 31 308 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 309 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 310 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 311 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 312 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 313 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 314 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 315 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 316 317 /* we'll use some unused PSW positions to store CR flags in tb flags */ 318 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 319 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 320 321 /* Control register 0 bits */ 322 #define CR0_LOWPROT 0x0000000010000000ULL 323 #define CR0_SECONDARY 0x0000000004000000ULL 324 #define CR0_EDAT 0x0000000000800000ULL 325 #define CR0_AFP 0x0000000000040000ULL 326 #define CR0_VECTOR 0x0000000000020000ULL 327 #define CR0_IEP 0x0000000000100000ULL 328 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 329 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 330 #define CR0_CKC_SC 0x0000000000000800ULL 331 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 332 #define CR0_SERVICE_SC 0x0000000000000200ULL 333 334 /* Control register 14 bits */ 335 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 336 337 /* MMU */ 338 #define MMU_PRIMARY_IDX 0 339 #define MMU_SECONDARY_IDX 1 340 #define MMU_HOME_IDX 2 341 #define MMU_REAL_IDX 3 342 343 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 344 { 345 #ifdef CONFIG_USER_ONLY 346 return MMU_USER_IDX; 347 #else 348 if (!(env->psw.mask & PSW_MASK_DAT)) { 349 return MMU_REAL_IDX; 350 } 351 352 if (ifetch) { 353 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 354 return MMU_HOME_IDX; 355 } 356 return MMU_PRIMARY_IDX; 357 } 358 359 switch (env->psw.mask & PSW_MASK_ASC) { 360 case PSW_ASC_PRIMARY: 361 return MMU_PRIMARY_IDX; 362 case PSW_ASC_SECONDARY: 363 return MMU_SECONDARY_IDX; 364 case PSW_ASC_HOME: 365 return MMU_HOME_IDX; 366 case PSW_ASC_ACCREG: 367 /* Fallthrough: access register mode is not yet supported */ 368 default: 369 abort(); 370 } 371 #endif 372 } 373 374 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 375 target_ulong *cs_base, uint32_t *flags) 376 { 377 *pc = env->psw.addr; 378 *cs_base = env->ex_value; 379 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 380 if (env->cregs[0] & CR0_AFP) { 381 *flags |= FLAG_MASK_AFP; 382 } 383 if (env->cregs[0] & CR0_VECTOR) { 384 *flags |= FLAG_MASK_VECTOR; 385 } 386 } 387 388 /* PER bits from control register 9 */ 389 #define PER_CR9_EVENT_BRANCH 0x80000000 390 #define PER_CR9_EVENT_IFETCH 0x40000000 391 #define PER_CR9_EVENT_STORE 0x20000000 392 #define PER_CR9_EVENT_STORE_REAL 0x08000000 393 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 394 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 395 #define PER_CR9_CONTROL_ALTERATION 0x00200000 396 397 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 398 #define PER_CODE_EVENT_BRANCH 0x8000 399 #define PER_CODE_EVENT_IFETCH 0x4000 400 #define PER_CODE_EVENT_STORE 0x2000 401 #define PER_CODE_EVENT_STORE_REAL 0x0800 402 #define PER_CODE_EVENT_NULLIFICATION 0x0100 403 404 #define EXCP_EXT 1 /* external interrupt */ 405 #define EXCP_SVC 2 /* supervisor call (syscall) */ 406 #define EXCP_PGM 3 /* program interruption */ 407 #define EXCP_RESTART 4 /* restart interrupt */ 408 #define EXCP_STOP 5 /* stop interrupt */ 409 #define EXCP_IO 7 /* I/O interrupt */ 410 #define EXCP_MCHK 8 /* machine check */ 411 412 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 413 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 414 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 415 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 416 #define INTERRUPT_RESTART (1 << 7) 417 #define INTERRUPT_STOP (1 << 8) 418 419 /* Program Status Word. */ 420 #define S390_PSWM_REGNUM 0 421 #define S390_PSWA_REGNUM 1 422 /* General Purpose Registers. */ 423 #define S390_R0_REGNUM 2 424 #define S390_R1_REGNUM 3 425 #define S390_R2_REGNUM 4 426 #define S390_R3_REGNUM 5 427 #define S390_R4_REGNUM 6 428 #define S390_R5_REGNUM 7 429 #define S390_R6_REGNUM 8 430 #define S390_R7_REGNUM 9 431 #define S390_R8_REGNUM 10 432 #define S390_R9_REGNUM 11 433 #define S390_R10_REGNUM 12 434 #define S390_R11_REGNUM 13 435 #define S390_R12_REGNUM 14 436 #define S390_R13_REGNUM 15 437 #define S390_R14_REGNUM 16 438 #define S390_R15_REGNUM 17 439 /* Total Core Registers. */ 440 #define S390_NUM_CORE_REGS 18 441 442 static inline void setcc(S390CPU *cpu, uint64_t cc) 443 { 444 CPUS390XState *env = &cpu->env; 445 446 env->psw.mask &= ~(3ull << 44); 447 env->psw.mask |= (cc & 3) << 44; 448 env->cc_op = cc; 449 } 450 451 /* STSI */ 452 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 453 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 454 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 455 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 456 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 457 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 458 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 459 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 460 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 461 462 /* Basic Machine Configuration */ 463 typedef struct SysIB_111 { 464 uint8_t res1[32]; 465 uint8_t manuf[16]; 466 uint8_t type[4]; 467 uint8_t res2[12]; 468 uint8_t model[16]; 469 uint8_t sequence[16]; 470 uint8_t plant[4]; 471 uint8_t res3[3996]; 472 } SysIB_111; 473 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 474 475 /* Basic Machine CPU */ 476 typedef struct SysIB_121 { 477 uint8_t res1[80]; 478 uint8_t sequence[16]; 479 uint8_t plant[4]; 480 uint8_t res2[2]; 481 uint16_t cpu_addr; 482 uint8_t res3[3992]; 483 } SysIB_121; 484 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 485 486 /* Basic Machine CPUs */ 487 typedef struct SysIB_122 { 488 uint8_t res1[32]; 489 uint32_t capability; 490 uint16_t total_cpus; 491 uint16_t conf_cpus; 492 uint16_t standby_cpus; 493 uint16_t reserved_cpus; 494 uint16_t adjustments[2026]; 495 } SysIB_122; 496 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 497 498 /* LPAR CPU */ 499 typedef struct SysIB_221 { 500 uint8_t res1[80]; 501 uint8_t sequence[16]; 502 uint8_t plant[4]; 503 uint16_t cpu_id; 504 uint16_t cpu_addr; 505 uint8_t res3[3992]; 506 } SysIB_221; 507 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 508 509 /* LPAR CPUs */ 510 typedef struct SysIB_222 { 511 uint8_t res1[32]; 512 uint16_t lpar_num; 513 uint8_t res2; 514 uint8_t lcpuc; 515 uint16_t total_cpus; 516 uint16_t conf_cpus; 517 uint16_t standby_cpus; 518 uint16_t reserved_cpus; 519 uint8_t name[8]; 520 uint32_t caf; 521 uint8_t res3[16]; 522 uint16_t dedicated_cpus; 523 uint16_t shared_cpus; 524 uint8_t res4[4020]; 525 } SysIB_222; 526 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 527 528 /* VM CPUs */ 529 typedef struct SysIB_322 { 530 uint8_t res1[31]; 531 uint8_t count; 532 struct { 533 uint8_t res2[4]; 534 uint16_t total_cpus; 535 uint16_t conf_cpus; 536 uint16_t standby_cpus; 537 uint16_t reserved_cpus; 538 uint8_t name[8]; 539 uint32_t caf; 540 uint8_t cpi[16]; 541 uint8_t res5[3]; 542 uint8_t ext_name_encoding; 543 uint32_t res3; 544 uint8_t uuid[16]; 545 } vm[8]; 546 uint8_t res4[1504]; 547 uint8_t ext_names[8][256]; 548 } SysIB_322; 549 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 550 551 typedef union SysIB { 552 SysIB_111 sysib_111; 553 SysIB_121 sysib_121; 554 SysIB_122 sysib_122; 555 SysIB_221 sysib_221; 556 SysIB_222 sysib_222; 557 SysIB_322 sysib_322; 558 } SysIB; 559 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 560 561 /* MMU defines */ 562 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 563 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 564 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 565 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 566 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 567 #define ASCE_REAL_SPACE 0x20 /* real space control */ 568 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 569 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 570 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 571 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 572 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 573 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 574 575 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 576 #define REGION_ENTRY_P 0x0000000000000200ULL 577 #define REGION_ENTRY_TF 0x00000000000000c0ULL 578 #define REGION_ENTRY_I 0x0000000000000020ULL 579 #define REGION_ENTRY_TT 0x000000000000000cULL 580 #define REGION_ENTRY_TL 0x0000000000000003ULL 581 582 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 583 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 584 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 585 586 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 587 #define REGION3_ENTRY_AV 0x0000000000010000ULL 588 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 589 #define REGION3_ENTRY_F 0x0000000000000800ULL 590 #define REGION3_ENTRY_FC 0x0000000000000400ULL 591 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 592 #define REGION3_ENTRY_CR 0x0000000000000010ULL 593 594 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 595 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 596 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 597 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 598 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 599 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 600 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 601 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 602 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 603 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 604 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 605 606 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 607 608 #define PAGE_ENTRY_0 0x0000000000000800ULL 609 #define PAGE_ENTRY_I 0x0000000000000400ULL 610 #define PAGE_ENTRY_P 0x0000000000000200ULL 611 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 612 613 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 614 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 615 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 616 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 617 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 618 619 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 620 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 621 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 622 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 623 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 624 625 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 626 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 627 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 628 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 629 630 #define SK_C (0x1 << 1) 631 #define SK_R (0x1 << 2) 632 #define SK_F (0x1 << 3) 633 #define SK_ACC_MASK (0xf << 4) 634 635 /* SIGP order codes */ 636 #define SIGP_SENSE 0x01 637 #define SIGP_EXTERNAL_CALL 0x02 638 #define SIGP_EMERGENCY 0x03 639 #define SIGP_START 0x04 640 #define SIGP_STOP 0x05 641 #define SIGP_RESTART 0x06 642 #define SIGP_STOP_STORE_STATUS 0x09 643 #define SIGP_INITIAL_CPU_RESET 0x0b 644 #define SIGP_CPU_RESET 0x0c 645 #define SIGP_SET_PREFIX 0x0d 646 #define SIGP_STORE_STATUS_ADDR 0x0e 647 #define SIGP_SET_ARCH 0x12 648 #define SIGP_COND_EMERGENCY 0x13 649 #define SIGP_SENSE_RUNNING 0x15 650 #define SIGP_STORE_ADTL_STATUS 0x17 651 652 /* SIGP condition codes */ 653 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 654 #define SIGP_CC_STATUS_STORED 1 655 #define SIGP_CC_BUSY 2 656 #define SIGP_CC_NOT_OPERATIONAL 3 657 658 /* SIGP status bits */ 659 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 660 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 661 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 662 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 663 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 664 #define SIGP_STAT_STOPPED 0x00000040UL 665 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 666 #define SIGP_STAT_CHECK_STOP 0x00000010UL 667 #define SIGP_STAT_INOPERATIVE 0x00000004UL 668 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 669 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 670 671 /* SIGP SET ARCHITECTURE modes */ 672 #define SIGP_MODE_ESA_S390 0 673 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 674 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 675 676 /* SIGP order code mask corresponding to bit positions 56-63 */ 677 #define SIGP_ORDER_MASK 0x000000ff 678 679 /* machine check interruption code */ 680 681 /* subclasses */ 682 #define MCIC_SC_SD 0x8000000000000000ULL 683 #define MCIC_SC_PD 0x4000000000000000ULL 684 #define MCIC_SC_SR 0x2000000000000000ULL 685 #define MCIC_SC_CD 0x0800000000000000ULL 686 #define MCIC_SC_ED 0x0400000000000000ULL 687 #define MCIC_SC_DG 0x0100000000000000ULL 688 #define MCIC_SC_W 0x0080000000000000ULL 689 #define MCIC_SC_CP 0x0040000000000000ULL 690 #define MCIC_SC_SP 0x0020000000000000ULL 691 #define MCIC_SC_CK 0x0010000000000000ULL 692 693 /* subclass modifiers */ 694 #define MCIC_SCM_B 0x0002000000000000ULL 695 #define MCIC_SCM_DA 0x0000000020000000ULL 696 #define MCIC_SCM_AP 0x0000000000080000ULL 697 698 /* storage errors */ 699 #define MCIC_SE_SE 0x0000800000000000ULL 700 #define MCIC_SE_SC 0x0000400000000000ULL 701 #define MCIC_SE_KE 0x0000200000000000ULL 702 #define MCIC_SE_DS 0x0000100000000000ULL 703 #define MCIC_SE_IE 0x0000000080000000ULL 704 705 /* validity bits */ 706 #define MCIC_VB_WP 0x0000080000000000ULL 707 #define MCIC_VB_MS 0x0000040000000000ULL 708 #define MCIC_VB_PM 0x0000020000000000ULL 709 #define MCIC_VB_IA 0x0000010000000000ULL 710 #define MCIC_VB_FA 0x0000008000000000ULL 711 #define MCIC_VB_VR 0x0000004000000000ULL 712 #define MCIC_VB_EC 0x0000002000000000ULL 713 #define MCIC_VB_FP 0x0000001000000000ULL 714 #define MCIC_VB_GR 0x0000000800000000ULL 715 #define MCIC_VB_CR 0x0000000400000000ULL 716 #define MCIC_VB_ST 0x0000000100000000ULL 717 #define MCIC_VB_AR 0x0000000040000000ULL 718 #define MCIC_VB_GS 0x0000000008000000ULL 719 #define MCIC_VB_PR 0x0000000000200000ULL 720 #define MCIC_VB_FC 0x0000000000100000ULL 721 #define MCIC_VB_CT 0x0000000000020000ULL 722 #define MCIC_VB_CC 0x0000000000010000ULL 723 724 static inline uint64_t s390_build_validity_mcic(void) 725 { 726 uint64_t mcic; 727 728 /* 729 * Indicate all validity bits (no damage) only. Other bits have to be 730 * added by the caller. (storage errors, subclasses and subclass modifiers) 731 */ 732 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 733 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 734 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 735 if (s390_has_feat(S390_FEAT_VECTOR)) { 736 mcic |= MCIC_VB_VR; 737 } 738 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 739 mcic |= MCIC_VB_GS; 740 } 741 return mcic; 742 } 743 744 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 745 { 746 cpu_reset(cs); 747 } 748 749 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 750 { 751 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 752 753 scc->reset(cs, S390_CPU_RESET_NORMAL); 754 } 755 756 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 757 { 758 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 759 760 scc->reset(cs, S390_CPU_RESET_INITIAL); 761 } 762 763 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 764 { 765 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 766 767 scc->load_normal(cs); 768 } 769 770 771 /* cpu.c */ 772 void s390_crypto_reset(void); 773 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 774 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 775 void s390_cmma_reset(void); 776 void s390_enable_css_support(S390CPU *cpu); 777 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 778 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 779 int vq, bool assign); 780 #ifndef CONFIG_USER_ONLY 781 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 782 #else 783 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 784 { 785 return 0; 786 } 787 #endif /* CONFIG_USER_ONLY */ 788 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 789 { 790 return cpu->env.cpu_state; 791 } 792 793 794 /* cpu_models.c */ 795 void s390_cpu_list(void); 796 #define cpu_list s390_cpu_list 797 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 798 const S390FeatInit feat_init); 799 800 801 /* helper.c */ 802 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 803 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 804 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 805 806 /* you can call this signal handler from your SIGBUS and SIGSEGV 807 signal handlers to inform the virtual CPU of exceptions. non zero 808 is returned if the signal was handled by the virtual CPU. */ 809 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 810 #define cpu_signal_handler cpu_s390x_signal_handler 811 812 813 /* interrupt.c */ 814 void s390_crw_mchk(void); 815 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 816 uint32_t io_int_parm, uint32_t io_int_word); 817 #define RA_IGNORED 0 818 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 819 /* service interrupts are floating therefore we must not pass an cpustate */ 820 void s390_sclp_extint(uint32_t parm); 821 822 /* mmu_helper.c */ 823 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 824 int len, bool is_write); 825 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 826 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 827 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 828 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 829 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 830 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 831 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 832 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 833 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 834 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 835 int len, bool is_write); 836 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 837 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 838 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 839 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 840 841 /* sigp.c */ 842 int s390_cpu_restart(S390CPU *cpu); 843 void s390_init_sigp(void); 844 845 846 /* outside of target/s390x/ */ 847 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 848 849 typedef CPUS390XState CPUArchState; 850 typedef S390CPU ArchCPU; 851 852 #include "exec/cpu-all.h" 853 854 #endif 855