1 /* 2 * S/390 virtual CPU header 3 * 4 * Copyright (c) 2009 Ulrich Hecht 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * Contributions after 2012-10-29 are licensed under the terms of the 17 * GNU GPL, version 2 or (at your option) any later version. 18 * 19 * You should have received a copy of the GNU (Lesser) General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #ifndef S390X_CPU_H 24 #define S390X_CPU_H 25 26 #include "qemu-common.h" 27 #include "cpu-qom.h" 28 #include "cpu_models.h" 29 30 #define TARGET_LONG_BITS 64 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 #define CPUArchState struct CPUS390XState 35 36 #include "exec/cpu-defs.h" 37 #define TARGET_PAGE_BITS 12 38 39 #define TARGET_PHYS_ADDR_SPACE_BITS 64 40 #define TARGET_VIRT_ADDR_SPACE_BITS 64 41 42 #include "exec/cpu-all.h" 43 44 #include "fpu/softfloat.h" 45 46 #define NB_MMU_MODES 4 47 #define TARGET_INSN_START_EXTRA_WORDS 1 48 49 #define MMU_MODE0_SUFFIX _primary 50 #define MMU_MODE1_SUFFIX _secondary 51 #define MMU_MODE2_SUFFIX _home 52 #define MMU_MODE3_SUFFIX _real 53 54 #define MMU_USER_IDX 0 55 56 #define MAX_IO_QUEUE 16 57 #define MAX_MCHK_QUEUE 16 58 59 #define PSW_MCHK_MASK 0x0004000000000000 60 #define PSW_IO_MASK 0x0200000000000000 61 62 #define S390_MAX_CPUS 248 63 64 typedef struct PSW { 65 uint64_t mask; 66 uint64_t addr; 67 } PSW; 68 69 typedef struct IOIntQueue { 70 uint16_t id; 71 uint16_t nr; 72 uint32_t parm; 73 uint32_t word; 74 } IOIntQueue; 75 76 typedef struct MchkQueue { 77 uint16_t type; 78 } MchkQueue; 79 80 struct CPUS390XState { 81 uint64_t regs[16]; /* GP registers */ 82 /* 83 * The floating point registers are part of the vector registers. 84 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 85 */ 86 CPU_DoubleU vregs[32][2]; /* vector registers */ 87 uint32_t aregs[16]; /* access registers */ 88 uint8_t riccb[64]; /* runtime instrumentation control */ 89 uint64_t gscb[4]; /* guarded storage control */ 90 91 /* Fields up to this point are not cleared by initial CPU reset */ 92 struct {} start_initial_reset_fields; 93 94 uint32_t fpc; /* floating-point control register */ 95 uint32_t cc_op; 96 97 float_status fpu_status; /* passed to softfloat lib */ 98 99 /* The low part of a 128-bit return, or remainder of a divide. */ 100 uint64_t retxl; 101 102 PSW psw; 103 104 uint64_t cc_src; 105 uint64_t cc_dst; 106 uint64_t cc_vr; 107 108 uint64_t ex_value; 109 110 uint64_t __excp_addr; 111 uint64_t psa; 112 113 uint32_t int_pgm_code; 114 uint32_t int_pgm_ilen; 115 116 uint32_t int_svc_code; 117 uint32_t int_svc_ilen; 118 119 uint64_t per_address; 120 uint16_t per_perc_atmid; 121 122 uint64_t cregs[16]; /* control registers */ 123 124 IOIntQueue io_queue[MAX_IO_QUEUE][8]; 125 MchkQueue mchk_queue[MAX_MCHK_QUEUE]; 126 127 int pending_int; 128 uint32_t service_param; 129 uint16_t external_call_addr; 130 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 131 int io_index[8]; 132 int mchk_index; 133 134 uint64_t ckc; 135 uint64_t cputm; 136 uint32_t todpr; 137 138 uint64_t pfault_token; 139 uint64_t pfault_compare; 140 uint64_t pfault_select; 141 142 uint64_t gbea; 143 uint64_t pp; 144 145 /* Fields up to this point are cleared by a CPU reset */ 146 struct {} end_reset_fields; 147 148 CPU_COMMON 149 150 #if !defined(CONFIG_USER_ONLY) 151 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 152 uint64_t cpuid; 153 #endif 154 155 uint64_t tod_offset; 156 uint64_t tod_basetime; 157 QEMUTimer *tod_timer; 158 159 QEMUTimer *cpu_timer; 160 161 /* 162 * The cpu state represents the logical state of a cpu. In contrast to other 163 * architectures, there is a difference between a halt and a stop on s390. 164 * If all cpus are either stopped (including check stop) or in the disabled 165 * wait state, the vm can be shut down. 166 */ 167 #define CPU_STATE_UNINITIALIZED 0x00 168 #define CPU_STATE_STOPPED 0x01 169 #define CPU_STATE_CHECK_STOP 0x02 170 #define CPU_STATE_OPERATING 0x03 171 #define CPU_STATE_LOAD 0x04 172 uint8_t cpu_state; 173 174 /* currently processed sigp order */ 175 uint8_t sigp_order; 176 177 }; 178 179 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr) 180 { 181 return &cs->vregs[nr][0]; 182 } 183 184 /** 185 * S390CPU: 186 * @env: #CPUS390XState. 187 * 188 * An S/390 CPU. 189 */ 190 struct S390CPU { 191 /*< private >*/ 192 CPUState parent_obj; 193 /*< public >*/ 194 195 CPUS390XState env; 196 S390CPUModel *model; 197 /* needed for live migration */ 198 void *irqstate; 199 uint32_t irqstate_saved_size; 200 }; 201 202 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) 203 { 204 return container_of(env, S390CPU, env); 205 } 206 207 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e)) 208 209 #define ENV_OFFSET offsetof(S390CPU, env) 210 211 #ifndef CONFIG_USER_ONLY 212 extern const struct VMStateDescription vmstate_s390_cpu; 213 #endif 214 215 /* distinguish between 24 bit and 31 bit addressing */ 216 #define HIGH_ORDER_BIT 0x80000000 217 218 /* Interrupt Codes */ 219 /* Program Interrupts */ 220 #define PGM_OPERATION 0x0001 221 #define PGM_PRIVILEGED 0x0002 222 #define PGM_EXECUTE 0x0003 223 #define PGM_PROTECTION 0x0004 224 #define PGM_ADDRESSING 0x0005 225 #define PGM_SPECIFICATION 0x0006 226 #define PGM_DATA 0x0007 227 #define PGM_FIXPT_OVERFLOW 0x0008 228 #define PGM_FIXPT_DIVIDE 0x0009 229 #define PGM_DEC_OVERFLOW 0x000a 230 #define PGM_DEC_DIVIDE 0x000b 231 #define PGM_HFP_EXP_OVERFLOW 0x000c 232 #define PGM_HFP_EXP_UNDERFLOW 0x000d 233 #define PGM_HFP_SIGNIFICANCE 0x000e 234 #define PGM_HFP_DIVIDE 0x000f 235 #define PGM_SEGMENT_TRANS 0x0010 236 #define PGM_PAGE_TRANS 0x0011 237 #define PGM_TRANS_SPEC 0x0012 238 #define PGM_SPECIAL_OP 0x0013 239 #define PGM_OPERAND 0x0015 240 #define PGM_TRACE_TABLE 0x0016 241 #define PGM_SPACE_SWITCH 0x001c 242 #define PGM_HFP_SQRT 0x001d 243 #define PGM_PC_TRANS_SPEC 0x001f 244 #define PGM_AFX_TRANS 0x0020 245 #define PGM_ASX_TRANS 0x0021 246 #define PGM_LX_TRANS 0x0022 247 #define PGM_EX_TRANS 0x0023 248 #define PGM_PRIM_AUTH 0x0024 249 #define PGM_SEC_AUTH 0x0025 250 #define PGM_ALET_SPEC 0x0028 251 #define PGM_ALEN_SPEC 0x0029 252 #define PGM_ALE_SEQ 0x002a 253 #define PGM_ASTE_VALID 0x002b 254 #define PGM_ASTE_SEQ 0x002c 255 #define PGM_EXT_AUTH 0x002d 256 #define PGM_STACK_FULL 0x0030 257 #define PGM_STACK_EMPTY 0x0031 258 #define PGM_STACK_SPEC 0x0032 259 #define PGM_STACK_TYPE 0x0033 260 #define PGM_STACK_OP 0x0034 261 #define PGM_ASCE_TYPE 0x0038 262 #define PGM_REG_FIRST_TRANS 0x0039 263 #define PGM_REG_SEC_TRANS 0x003a 264 #define PGM_REG_THIRD_TRANS 0x003b 265 #define PGM_MONITOR 0x0040 266 #define PGM_PER 0x0080 267 #define PGM_CRYPTO 0x0119 268 269 /* External Interrupts */ 270 #define EXT_INTERRUPT_KEY 0x0040 271 #define EXT_CLOCK_COMP 0x1004 272 #define EXT_CPU_TIMER 0x1005 273 #define EXT_MALFUNCTION 0x1200 274 #define EXT_EMERGENCY 0x1201 275 #define EXT_EXTERNAL_CALL 0x1202 276 #define EXT_ETR 0x1406 277 #define EXT_SERVICE 0x2401 278 #define EXT_VIRTIO 0x2603 279 280 /* PSW defines */ 281 #undef PSW_MASK_PER 282 #undef PSW_MASK_DAT 283 #undef PSW_MASK_IO 284 #undef PSW_MASK_EXT 285 #undef PSW_MASK_KEY 286 #undef PSW_SHIFT_KEY 287 #undef PSW_MASK_MCHECK 288 #undef PSW_MASK_WAIT 289 #undef PSW_MASK_PSTATE 290 #undef PSW_MASK_ASC 291 #undef PSW_SHIFT_ASC 292 #undef PSW_MASK_CC 293 #undef PSW_MASK_PM 294 #undef PSW_SHIFT_MASK_PM 295 #undef PSW_MASK_64 296 #undef PSW_MASK_32 297 #undef PSW_MASK_ESA_ADDR 298 299 #define PSW_MASK_PER 0x4000000000000000ULL 300 #define PSW_MASK_DAT 0x0400000000000000ULL 301 #define PSW_MASK_IO 0x0200000000000000ULL 302 #define PSW_MASK_EXT 0x0100000000000000ULL 303 #define PSW_MASK_KEY 0x00F0000000000000ULL 304 #define PSW_SHIFT_KEY 52 305 #define PSW_MASK_MCHECK 0x0004000000000000ULL 306 #define PSW_MASK_WAIT 0x0002000000000000ULL 307 #define PSW_MASK_PSTATE 0x0001000000000000ULL 308 #define PSW_MASK_ASC 0x0000C00000000000ULL 309 #define PSW_SHIFT_ASC 46 310 #define PSW_MASK_CC 0x0000300000000000ULL 311 #define PSW_MASK_PM 0x00000F0000000000ULL 312 #define PSW_SHIFT_MASK_PM 40 313 #define PSW_MASK_64 0x0000000100000000ULL 314 #define PSW_MASK_32 0x0000000080000000ULL 315 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 316 317 #undef PSW_ASC_PRIMARY 318 #undef PSW_ASC_ACCREG 319 #undef PSW_ASC_SECONDARY 320 #undef PSW_ASC_HOME 321 322 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 323 #define PSW_ASC_ACCREG 0x0000400000000000ULL 324 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 325 #define PSW_ASC_HOME 0x0000C00000000000ULL 326 327 /* the address space values shifted */ 328 #define AS_PRIMARY 0 329 #define AS_ACCREG 1 330 #define AS_SECONDARY 2 331 #define AS_HOME 3 332 333 /* tb flags */ 334 335 #define FLAG_MASK_PSW_SHIFT 31 336 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 337 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 338 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 339 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 340 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 341 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \ 342 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 343 344 /* Control register 0 bits */ 345 #define CR0_LOWPROT 0x0000000010000000ULL 346 #define CR0_SECONDARY 0x0000000004000000ULL 347 #define CR0_EDAT 0x0000000000800000ULL 348 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 349 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 350 #define CR0_CKC_SC 0x0000000000000800ULL 351 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 352 #define CR0_SERVICE_SC 0x0000000000000200ULL 353 354 /* Control register 14 bits */ 355 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 356 357 /* MMU */ 358 #define MMU_PRIMARY_IDX 0 359 #define MMU_SECONDARY_IDX 1 360 #define MMU_HOME_IDX 2 361 #define MMU_REAL_IDX 3 362 363 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 364 { 365 switch (env->psw.mask & PSW_MASK_ASC) { 366 case PSW_ASC_PRIMARY: 367 return MMU_PRIMARY_IDX; 368 case PSW_ASC_SECONDARY: 369 return MMU_SECONDARY_IDX; 370 case PSW_ASC_HOME: 371 return MMU_HOME_IDX; 372 case PSW_ASC_ACCREG: 373 /* Fallthrough: access register mode is not yet supported */ 374 default: 375 abort(); 376 } 377 } 378 379 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 380 target_ulong *cs_base, uint32_t *flags) 381 { 382 *pc = env->psw.addr; 383 *cs_base = env->ex_value; 384 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 385 } 386 387 /* PER bits from control register 9 */ 388 #define PER_CR9_EVENT_BRANCH 0x80000000 389 #define PER_CR9_EVENT_IFETCH 0x40000000 390 #define PER_CR9_EVENT_STORE 0x20000000 391 #define PER_CR9_EVENT_STORE_REAL 0x08000000 392 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 393 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 394 #define PER_CR9_CONTROL_ALTERATION 0x00200000 395 396 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 397 #define PER_CODE_EVENT_BRANCH 0x8000 398 #define PER_CODE_EVENT_IFETCH 0x4000 399 #define PER_CODE_EVENT_STORE 0x2000 400 #define PER_CODE_EVENT_STORE_REAL 0x0800 401 #define PER_CODE_EVENT_NULLIFICATION 0x0100 402 403 #define EXCP_EXT 1 /* external interrupt */ 404 #define EXCP_SVC 2 /* supervisor call (syscall) */ 405 #define EXCP_PGM 3 /* program interruption */ 406 #define EXCP_RESTART 4 /* restart interrupt */ 407 #define EXCP_STOP 5 /* stop interrupt */ 408 #define EXCP_IO 7 /* I/O interrupt */ 409 #define EXCP_MCHK 8 /* machine check */ 410 411 #define INTERRUPT_IO (1 << 0) 412 #define INTERRUPT_MCHK (1 << 1) 413 #define INTERRUPT_EXT_SERVICE (1 << 2) 414 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 415 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 416 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 417 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 418 #define INTERRUPT_RESTART (1 << 7) 419 #define INTERRUPT_STOP (1 << 8) 420 421 /* Program Status Word. */ 422 #define S390_PSWM_REGNUM 0 423 #define S390_PSWA_REGNUM 1 424 /* General Purpose Registers. */ 425 #define S390_R0_REGNUM 2 426 #define S390_R1_REGNUM 3 427 #define S390_R2_REGNUM 4 428 #define S390_R3_REGNUM 5 429 #define S390_R4_REGNUM 6 430 #define S390_R5_REGNUM 7 431 #define S390_R6_REGNUM 8 432 #define S390_R7_REGNUM 9 433 #define S390_R8_REGNUM 10 434 #define S390_R9_REGNUM 11 435 #define S390_R10_REGNUM 12 436 #define S390_R11_REGNUM 13 437 #define S390_R12_REGNUM 14 438 #define S390_R13_REGNUM 15 439 #define S390_R14_REGNUM 16 440 #define S390_R15_REGNUM 17 441 /* Total Core Registers. */ 442 #define S390_NUM_CORE_REGS 18 443 444 static inline void setcc(S390CPU *cpu, uint64_t cc) 445 { 446 CPUS390XState *env = &cpu->env; 447 448 env->psw.mask &= ~(3ull << 44); 449 env->psw.mask |= (cc & 3) << 44; 450 env->cc_op = cc; 451 } 452 453 /* STSI */ 454 #define STSI_LEVEL_MASK 0x00000000f0000000ULL 455 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL 456 #define STSI_LEVEL_1 0x0000000010000000ULL 457 #define STSI_LEVEL_2 0x0000000020000000ULL 458 #define STSI_LEVEL_3 0x0000000030000000ULL 459 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 460 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 461 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 462 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 463 464 /* Basic Machine Configuration */ 465 struct sysib_111 { 466 uint32_t res1[8]; 467 uint8_t manuf[16]; 468 uint8_t type[4]; 469 uint8_t res2[12]; 470 uint8_t model[16]; 471 uint8_t sequence[16]; 472 uint8_t plant[4]; 473 uint8_t res3[156]; 474 }; 475 476 /* Basic Machine CPU */ 477 struct sysib_121 { 478 uint32_t res1[80]; 479 uint8_t sequence[16]; 480 uint8_t plant[4]; 481 uint8_t res2[2]; 482 uint16_t cpu_addr; 483 uint8_t res3[152]; 484 }; 485 486 /* Basic Machine CPUs */ 487 struct sysib_122 { 488 uint8_t res1[32]; 489 uint32_t capability; 490 uint16_t total_cpus; 491 uint16_t active_cpus; 492 uint16_t standby_cpus; 493 uint16_t reserved_cpus; 494 uint16_t adjustments[2026]; 495 }; 496 497 /* LPAR CPU */ 498 struct sysib_221 { 499 uint32_t res1[80]; 500 uint8_t sequence[16]; 501 uint8_t plant[4]; 502 uint16_t cpu_id; 503 uint16_t cpu_addr; 504 uint8_t res3[152]; 505 }; 506 507 /* LPAR CPUs */ 508 struct sysib_222 { 509 uint32_t res1[32]; 510 uint16_t lpar_num; 511 uint8_t res2; 512 uint8_t lcpuc; 513 uint16_t total_cpus; 514 uint16_t conf_cpus; 515 uint16_t standby_cpus; 516 uint16_t reserved_cpus; 517 uint8_t name[8]; 518 uint32_t caf; 519 uint8_t res3[16]; 520 uint16_t dedicated_cpus; 521 uint16_t shared_cpus; 522 uint8_t res4[180]; 523 }; 524 525 /* VM CPUs */ 526 struct sysib_322 { 527 uint8_t res1[31]; 528 uint8_t count; 529 struct { 530 uint8_t res2[4]; 531 uint16_t total_cpus; 532 uint16_t conf_cpus; 533 uint16_t standby_cpus; 534 uint16_t reserved_cpus; 535 uint8_t name[8]; 536 uint32_t caf; 537 uint8_t cpi[16]; 538 uint8_t res5[3]; 539 uint8_t ext_name_encoding; 540 uint32_t res3; 541 uint8_t uuid[16]; 542 } vm[8]; 543 uint8_t res4[1504]; 544 uint8_t ext_names[8][256]; 545 }; 546 547 /* MMU defines */ 548 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */ 549 #define _ASCE_SUBSPACE 0x200 /* subspace group control */ 550 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */ 551 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 552 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */ 553 #define _ASCE_REAL_SPACE 0x20 /* real space control */ 554 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */ 555 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */ 556 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */ 557 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */ 558 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 559 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */ 560 561 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */ 562 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */ 563 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */ 564 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */ 565 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */ 566 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */ 567 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */ 568 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */ 569 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */ 570 571 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */ 572 #define _SEGMENT_ENTRY_FC 0x400 /* format control */ 573 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */ 574 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */ 575 576 #define VADDR_PX 0xff000 /* page index bits */ 577 578 #define _PAGE_RO 0x200 /* HW read-only bit */ 579 #define _PAGE_INVALID 0x400 /* HW invalid bit */ 580 #define _PAGE_RES0 0x800 /* bit must be zero */ 581 582 #define SK_C (0x1 << 1) 583 #define SK_R (0x1 << 2) 584 #define SK_F (0x1 << 3) 585 #define SK_ACC_MASK (0xf << 4) 586 587 /* SIGP order codes */ 588 #define SIGP_SENSE 0x01 589 #define SIGP_EXTERNAL_CALL 0x02 590 #define SIGP_EMERGENCY 0x03 591 #define SIGP_START 0x04 592 #define SIGP_STOP 0x05 593 #define SIGP_RESTART 0x06 594 #define SIGP_STOP_STORE_STATUS 0x09 595 #define SIGP_INITIAL_CPU_RESET 0x0b 596 #define SIGP_CPU_RESET 0x0c 597 #define SIGP_SET_PREFIX 0x0d 598 #define SIGP_STORE_STATUS_ADDR 0x0e 599 #define SIGP_SET_ARCH 0x12 600 #define SIGP_COND_EMERGENCY 0x13 601 #define SIGP_SENSE_RUNNING 0x15 602 #define SIGP_STORE_ADTL_STATUS 0x17 603 604 /* SIGP condition codes */ 605 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 606 #define SIGP_CC_STATUS_STORED 1 607 #define SIGP_CC_BUSY 2 608 #define SIGP_CC_NOT_OPERATIONAL 3 609 610 /* SIGP status bits */ 611 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 612 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 613 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 614 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 615 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 616 #define SIGP_STAT_STOPPED 0x00000040UL 617 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 618 #define SIGP_STAT_CHECK_STOP 0x00000010UL 619 #define SIGP_STAT_INOPERATIVE 0x00000004UL 620 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 621 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 622 623 /* SIGP SET ARCHITECTURE modes */ 624 #define SIGP_MODE_ESA_S390 0 625 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 626 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 627 628 /* SIGP order code mask corresponding to bit positions 56-63 */ 629 #define SIGP_ORDER_MASK 0x000000ff 630 631 /* from s390-virtio-ccw */ 632 #define MEM_SECTION_SIZE 0x10000000UL 633 #define MAX_AVAIL_SLOTS 32 634 635 /* machine check interruption code */ 636 637 /* subclasses */ 638 #define MCIC_SC_SD 0x8000000000000000ULL 639 #define MCIC_SC_PD 0x4000000000000000ULL 640 #define MCIC_SC_SR 0x2000000000000000ULL 641 #define MCIC_SC_CD 0x0800000000000000ULL 642 #define MCIC_SC_ED 0x0400000000000000ULL 643 #define MCIC_SC_DG 0x0100000000000000ULL 644 #define MCIC_SC_W 0x0080000000000000ULL 645 #define MCIC_SC_CP 0x0040000000000000ULL 646 #define MCIC_SC_SP 0x0020000000000000ULL 647 #define MCIC_SC_CK 0x0010000000000000ULL 648 649 /* subclass modifiers */ 650 #define MCIC_SCM_B 0x0002000000000000ULL 651 #define MCIC_SCM_DA 0x0000000020000000ULL 652 #define MCIC_SCM_AP 0x0000000000080000ULL 653 654 /* storage errors */ 655 #define MCIC_SE_SE 0x0000800000000000ULL 656 #define MCIC_SE_SC 0x0000400000000000ULL 657 #define MCIC_SE_KE 0x0000200000000000ULL 658 #define MCIC_SE_DS 0x0000100000000000ULL 659 #define MCIC_SE_IE 0x0000000080000000ULL 660 661 /* validity bits */ 662 #define MCIC_VB_WP 0x0000080000000000ULL 663 #define MCIC_VB_MS 0x0000040000000000ULL 664 #define MCIC_VB_PM 0x0000020000000000ULL 665 #define MCIC_VB_IA 0x0000010000000000ULL 666 #define MCIC_VB_FA 0x0000008000000000ULL 667 #define MCIC_VB_VR 0x0000004000000000ULL 668 #define MCIC_VB_EC 0x0000002000000000ULL 669 #define MCIC_VB_FP 0x0000001000000000ULL 670 #define MCIC_VB_GR 0x0000000800000000ULL 671 #define MCIC_VB_CR 0x0000000400000000ULL 672 #define MCIC_VB_ST 0x0000000100000000ULL 673 #define MCIC_VB_AR 0x0000000040000000ULL 674 #define MCIC_VB_GS 0x0000000008000000ULL 675 #define MCIC_VB_PR 0x0000000000200000ULL 676 #define MCIC_VB_FC 0x0000000000100000ULL 677 #define MCIC_VB_CT 0x0000000000020000ULL 678 #define MCIC_VB_CC 0x0000000000010000ULL 679 680 static inline uint64_t s390_build_validity_mcic(void) 681 { 682 uint64_t mcic; 683 684 /* 685 * Indicate all validity bits (no damage) only. Other bits have to be 686 * added by the caller. (storage errors, subclasses and subclass modifiers) 687 */ 688 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 689 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 690 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 691 if (s390_has_feat(S390_FEAT_VECTOR)) { 692 mcic |= MCIC_VB_VR; 693 } 694 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 695 mcic |= MCIC_VB_GS; 696 } 697 return mcic; 698 } 699 700 701 /* cpu.c */ 702 int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low); 703 int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low); 704 void s390_crypto_reset(void); 705 bool s390_get_squash_mcss(void); 706 int s390_get_memslot_count(void); 707 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 708 void s390_cmma_reset(void); 709 void s390_enable_css_support(S390CPU *cpu); 710 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 711 int vq, bool assign); 712 #ifndef CONFIG_USER_ONLY 713 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 714 #else 715 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 716 { 717 return 0; 718 } 719 #endif /* CONFIG_USER_ONLY */ 720 721 722 /* cpu_models.c */ 723 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf); 724 #define cpu_list s390_cpu_list 725 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 726 const S390FeatInit feat_init); 727 728 729 /* helper.c */ 730 #define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model) 731 732 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 733 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 734 735 /* you can call this signal handler from your SIGBUS and SIGSEGV 736 signal handlers to inform the virtual CPU of exceptions. non zero 737 is returned if the signal was handled by the virtual CPU. */ 738 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 739 #define cpu_signal_handler cpu_s390x_signal_handler 740 741 742 /* interrupt.c */ 743 void s390_crw_mchk(void); 744 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 745 uint32_t io_int_parm, uint32_t io_int_word); 746 /* automatically detect the instruction length */ 747 #define ILEN_AUTO 0xff 748 #define RA_IGNORED 0 749 void s390_program_interrupt(CPUS390XState *env, uint32_t code, int ilen, 750 uintptr_t ra); 751 /* service interrupts are floating therefore we must not pass an cpustate */ 752 void s390_sclp_extint(uint32_t parm); 753 754 755 /* mmu_helper.c */ 756 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 757 int len, bool is_write); 758 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 759 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 760 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 761 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 762 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 763 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 764 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 765 766 767 /* sigp.c */ 768 int s390_cpu_restart(S390CPU *cpu); 769 void s390_init_sigp(void); 770 771 772 /* outside of target/s390x/ */ 773 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 774 775 #endif 776