1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-defs.h" 31 32 #define ELF_MACHINE_UNAME "S390X" 33 34 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ 35 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) 36 37 #define TARGET_INSN_START_EXTRA_WORDS 2 38 39 #define MMU_MODE0_SUFFIX _primary 40 #define MMU_MODE1_SUFFIX _secondary 41 #define MMU_MODE2_SUFFIX _home 42 #define MMU_MODE3_SUFFIX _real 43 44 #define MMU_USER_IDX 0 45 46 #define S390_MAX_CPUS 248 47 48 typedef struct PSW { 49 uint64_t mask; 50 uint64_t addr; 51 } PSW; 52 53 struct CPUS390XState { 54 uint64_t regs[16]; /* GP registers */ 55 /* 56 * The floating point registers are part of the vector registers. 57 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 58 */ 59 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 60 uint32_t aregs[16]; /* access registers */ 61 uint64_t gscb[4]; /* guarded storage control */ 62 uint64_t etoken; /* etoken */ 63 uint64_t etoken_extension; /* etoken extension */ 64 65 /* Fields up to this point are not cleared by initial CPU reset */ 66 struct {} start_initial_reset_fields; 67 68 uint32_t fpc; /* floating-point control register */ 69 uint32_t cc_op; 70 bool bpbc; /* branch prediction blocking */ 71 72 float_status fpu_status; /* passed to softfloat lib */ 73 74 /* The low part of a 128-bit return, or remainder of a divide. */ 75 uint64_t retxl; 76 77 PSW psw; 78 79 S390CrashReason crash_reason; 80 81 uint64_t cc_src; 82 uint64_t cc_dst; 83 uint64_t cc_vr; 84 85 uint64_t ex_value; 86 87 uint64_t __excp_addr; 88 uint64_t psa; 89 90 uint32_t int_pgm_code; 91 uint32_t int_pgm_ilen; 92 93 uint32_t int_svc_code; 94 uint32_t int_svc_ilen; 95 96 uint64_t per_address; 97 uint16_t per_perc_atmid; 98 99 uint64_t cregs[16]; /* control registers */ 100 101 uint64_t ckc; 102 uint64_t cputm; 103 uint32_t todpr; 104 105 uint64_t pfault_token; 106 uint64_t pfault_compare; 107 uint64_t pfault_select; 108 109 uint64_t gbea; 110 uint64_t pp; 111 112 /* Fields up to this point are not cleared by normal CPU reset */ 113 struct {} start_normal_reset_fields; 114 uint8_t riccb[64]; /* runtime instrumentation control */ 115 116 int pending_int; 117 uint16_t external_call_addr; 118 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 119 120 /* Fields up to this point are cleared by a CPU reset */ 121 struct {} end_reset_fields; 122 123 #if !defined(CONFIG_USER_ONLY) 124 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 125 uint64_t cpuid; 126 #endif 127 128 QEMUTimer *tod_timer; 129 130 QEMUTimer *cpu_timer; 131 132 /* 133 * The cpu state represents the logical state of a cpu. In contrast to other 134 * architectures, there is a difference between a halt and a stop on s390. 135 * If all cpus are either stopped (including check stop) or in the disabled 136 * wait state, the vm can be shut down. 137 * The acceptable cpu_state values are defined in the CpuInfoS390State 138 * enum. 139 */ 140 uint8_t cpu_state; 141 142 /* currently processed sigp order */ 143 uint8_t sigp_order; 144 145 }; 146 147 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 148 { 149 return &cs->vregs[nr][0]; 150 } 151 152 /** 153 * S390CPU: 154 * @env: #CPUS390XState. 155 * 156 * An S/390 CPU. 157 */ 158 struct S390CPU { 159 /*< private >*/ 160 CPUState parent_obj; 161 /*< public >*/ 162 163 CPUNegativeOffsetState neg; 164 CPUS390XState env; 165 S390CPUModel *model; 166 /* needed for live migration */ 167 void *irqstate; 168 uint32_t irqstate_saved_size; 169 }; 170 171 172 #ifndef CONFIG_USER_ONLY 173 extern const VMStateDescription vmstate_s390_cpu; 174 #endif 175 176 /* distinguish between 24 bit and 31 bit addressing */ 177 #define HIGH_ORDER_BIT 0x80000000 178 179 /* Interrupt Codes */ 180 /* Program Interrupts */ 181 #define PGM_OPERATION 0x0001 182 #define PGM_PRIVILEGED 0x0002 183 #define PGM_EXECUTE 0x0003 184 #define PGM_PROTECTION 0x0004 185 #define PGM_ADDRESSING 0x0005 186 #define PGM_SPECIFICATION 0x0006 187 #define PGM_DATA 0x0007 188 #define PGM_FIXPT_OVERFLOW 0x0008 189 #define PGM_FIXPT_DIVIDE 0x0009 190 #define PGM_DEC_OVERFLOW 0x000a 191 #define PGM_DEC_DIVIDE 0x000b 192 #define PGM_HFP_EXP_OVERFLOW 0x000c 193 #define PGM_HFP_EXP_UNDERFLOW 0x000d 194 #define PGM_HFP_SIGNIFICANCE 0x000e 195 #define PGM_HFP_DIVIDE 0x000f 196 #define PGM_SEGMENT_TRANS 0x0010 197 #define PGM_PAGE_TRANS 0x0011 198 #define PGM_TRANS_SPEC 0x0012 199 #define PGM_SPECIAL_OP 0x0013 200 #define PGM_OPERAND 0x0015 201 #define PGM_TRACE_TABLE 0x0016 202 #define PGM_VECTOR_PROCESSING 0x001b 203 #define PGM_SPACE_SWITCH 0x001c 204 #define PGM_HFP_SQRT 0x001d 205 #define PGM_PC_TRANS_SPEC 0x001f 206 #define PGM_AFX_TRANS 0x0020 207 #define PGM_ASX_TRANS 0x0021 208 #define PGM_LX_TRANS 0x0022 209 #define PGM_EX_TRANS 0x0023 210 #define PGM_PRIM_AUTH 0x0024 211 #define PGM_SEC_AUTH 0x0025 212 #define PGM_ALET_SPEC 0x0028 213 #define PGM_ALEN_SPEC 0x0029 214 #define PGM_ALE_SEQ 0x002a 215 #define PGM_ASTE_VALID 0x002b 216 #define PGM_ASTE_SEQ 0x002c 217 #define PGM_EXT_AUTH 0x002d 218 #define PGM_STACK_FULL 0x0030 219 #define PGM_STACK_EMPTY 0x0031 220 #define PGM_STACK_SPEC 0x0032 221 #define PGM_STACK_TYPE 0x0033 222 #define PGM_STACK_OP 0x0034 223 #define PGM_ASCE_TYPE 0x0038 224 #define PGM_REG_FIRST_TRANS 0x0039 225 #define PGM_REG_SEC_TRANS 0x003a 226 #define PGM_REG_THIRD_TRANS 0x003b 227 #define PGM_MONITOR 0x0040 228 #define PGM_PER 0x0080 229 #define PGM_CRYPTO 0x0119 230 231 /* External Interrupts */ 232 #define EXT_INTERRUPT_KEY 0x0040 233 #define EXT_CLOCK_COMP 0x1004 234 #define EXT_CPU_TIMER 0x1005 235 #define EXT_MALFUNCTION 0x1200 236 #define EXT_EMERGENCY 0x1201 237 #define EXT_EXTERNAL_CALL 0x1202 238 #define EXT_ETR 0x1406 239 #define EXT_SERVICE 0x2401 240 #define EXT_VIRTIO 0x2603 241 242 /* PSW defines */ 243 #undef PSW_MASK_PER 244 #undef PSW_MASK_UNUSED_2 245 #undef PSW_MASK_UNUSED_3 246 #undef PSW_MASK_DAT 247 #undef PSW_MASK_IO 248 #undef PSW_MASK_EXT 249 #undef PSW_MASK_KEY 250 #undef PSW_SHIFT_KEY 251 #undef PSW_MASK_MCHECK 252 #undef PSW_MASK_WAIT 253 #undef PSW_MASK_PSTATE 254 #undef PSW_MASK_ASC 255 #undef PSW_SHIFT_ASC 256 #undef PSW_MASK_CC 257 #undef PSW_MASK_PM 258 #undef PSW_MASK_RI 259 #undef PSW_SHIFT_MASK_PM 260 #undef PSW_MASK_64 261 #undef PSW_MASK_32 262 #undef PSW_MASK_ESA_ADDR 263 264 #define PSW_MASK_PER 0x4000000000000000ULL 265 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 266 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 267 #define PSW_MASK_DAT 0x0400000000000000ULL 268 #define PSW_MASK_IO 0x0200000000000000ULL 269 #define PSW_MASK_EXT 0x0100000000000000ULL 270 #define PSW_MASK_KEY 0x00F0000000000000ULL 271 #define PSW_SHIFT_KEY 52 272 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 273 #define PSW_MASK_MCHECK 0x0004000000000000ULL 274 #define PSW_MASK_WAIT 0x0002000000000000ULL 275 #define PSW_MASK_PSTATE 0x0001000000000000ULL 276 #define PSW_MASK_ASC 0x0000C00000000000ULL 277 #define PSW_SHIFT_ASC 46 278 #define PSW_MASK_CC 0x0000300000000000ULL 279 #define PSW_MASK_PM 0x00000F0000000000ULL 280 #define PSW_SHIFT_MASK_PM 40 281 #define PSW_MASK_RI 0x0000008000000000ULL 282 #define PSW_MASK_64 0x0000000100000000ULL 283 #define PSW_MASK_32 0x0000000080000000ULL 284 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL 285 286 #undef PSW_ASC_PRIMARY 287 #undef PSW_ASC_ACCREG 288 #undef PSW_ASC_SECONDARY 289 #undef PSW_ASC_HOME 290 291 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 292 #define PSW_ASC_ACCREG 0x0000400000000000ULL 293 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 294 #define PSW_ASC_HOME 0x0000C00000000000ULL 295 296 /* the address space values shifted */ 297 #define AS_PRIMARY 0 298 #define AS_ACCREG 1 299 #define AS_SECONDARY 2 300 #define AS_HOME 3 301 302 /* tb flags */ 303 304 #define FLAG_MASK_PSW_SHIFT 31 305 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT) 306 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT) 307 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT) 308 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT) 309 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT) 310 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT) 311 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \ 312 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 313 314 /* we'll use some unused PSW positions to store CR flags in tb flags */ 315 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT) 316 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT) 317 318 /* Control register 0 bits */ 319 #define CR0_LOWPROT 0x0000000010000000ULL 320 #define CR0_SECONDARY 0x0000000004000000ULL 321 #define CR0_EDAT 0x0000000000800000ULL 322 #define CR0_AFP 0x0000000000040000ULL 323 #define CR0_VECTOR 0x0000000000020000ULL 324 #define CR0_IEP 0x0000000000100000ULL 325 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 326 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 327 #define CR0_CKC_SC 0x0000000000000800ULL 328 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 329 #define CR0_SERVICE_SC 0x0000000000000200ULL 330 331 /* Control register 14 bits */ 332 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 333 334 /* MMU */ 335 #define MMU_PRIMARY_IDX 0 336 #define MMU_SECONDARY_IDX 1 337 #define MMU_HOME_IDX 2 338 #define MMU_REAL_IDX 3 339 340 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch) 341 { 342 #ifdef CONFIG_USER_ONLY 343 return MMU_USER_IDX; 344 #else 345 if (!(env->psw.mask & PSW_MASK_DAT)) { 346 return MMU_REAL_IDX; 347 } 348 349 if (ifetch) { 350 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 351 return MMU_HOME_IDX; 352 } 353 return MMU_PRIMARY_IDX; 354 } 355 356 switch (env->psw.mask & PSW_MASK_ASC) { 357 case PSW_ASC_PRIMARY: 358 return MMU_PRIMARY_IDX; 359 case PSW_ASC_SECONDARY: 360 return MMU_SECONDARY_IDX; 361 case PSW_ASC_HOME: 362 return MMU_HOME_IDX; 363 case PSW_ASC_ACCREG: 364 /* Fallthrough: access register mode is not yet supported */ 365 default: 366 abort(); 367 } 368 #endif 369 } 370 371 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc, 372 target_ulong *cs_base, uint32_t *flags) 373 { 374 *pc = env->psw.addr; 375 *cs_base = env->ex_value; 376 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW; 377 if (env->cregs[0] & CR0_AFP) { 378 *flags |= FLAG_MASK_AFP; 379 } 380 if (env->cregs[0] & CR0_VECTOR) { 381 *flags |= FLAG_MASK_VECTOR; 382 } 383 } 384 385 /* PER bits from control register 9 */ 386 #define PER_CR9_EVENT_BRANCH 0x80000000 387 #define PER_CR9_EVENT_IFETCH 0x40000000 388 #define PER_CR9_EVENT_STORE 0x20000000 389 #define PER_CR9_EVENT_STORE_REAL 0x08000000 390 #define PER_CR9_EVENT_NULLIFICATION 0x01000000 391 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 392 #define PER_CR9_CONTROL_ALTERATION 0x00200000 393 394 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 395 #define PER_CODE_EVENT_BRANCH 0x8000 396 #define PER_CODE_EVENT_IFETCH 0x4000 397 #define PER_CODE_EVENT_STORE 0x2000 398 #define PER_CODE_EVENT_STORE_REAL 0x0800 399 #define PER_CODE_EVENT_NULLIFICATION 0x0100 400 401 #define EXCP_EXT 1 /* external interrupt */ 402 #define EXCP_SVC 2 /* supervisor call (syscall) */ 403 #define EXCP_PGM 3 /* program interruption */ 404 #define EXCP_RESTART 4 /* restart interrupt */ 405 #define EXCP_STOP 5 /* stop interrupt */ 406 #define EXCP_IO 7 /* I/O interrupt */ 407 #define EXCP_MCHK 8 /* machine check */ 408 409 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 410 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 411 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 412 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 413 #define INTERRUPT_RESTART (1 << 7) 414 #define INTERRUPT_STOP (1 << 8) 415 416 /* Program Status Word. */ 417 #define S390_PSWM_REGNUM 0 418 #define S390_PSWA_REGNUM 1 419 /* General Purpose Registers. */ 420 #define S390_R0_REGNUM 2 421 #define S390_R1_REGNUM 3 422 #define S390_R2_REGNUM 4 423 #define S390_R3_REGNUM 5 424 #define S390_R4_REGNUM 6 425 #define S390_R5_REGNUM 7 426 #define S390_R6_REGNUM 8 427 #define S390_R7_REGNUM 9 428 #define S390_R8_REGNUM 10 429 #define S390_R9_REGNUM 11 430 #define S390_R10_REGNUM 12 431 #define S390_R11_REGNUM 13 432 #define S390_R12_REGNUM 14 433 #define S390_R13_REGNUM 15 434 #define S390_R14_REGNUM 16 435 #define S390_R15_REGNUM 17 436 /* Total Core Registers. */ 437 #define S390_NUM_CORE_REGS 18 438 439 static inline void setcc(S390CPU *cpu, uint64_t cc) 440 { 441 CPUS390XState *env = &cpu->env; 442 443 env->psw.mask &= ~(3ull << 44); 444 env->psw.mask |= (cc & 3) << 44; 445 env->cc_op = cc; 446 } 447 448 /* STSI */ 449 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 450 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 451 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 452 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 453 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 454 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 455 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 456 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 457 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 458 459 /* Basic Machine Configuration */ 460 typedef struct SysIB_111 { 461 uint8_t res1[32]; 462 uint8_t manuf[16]; 463 uint8_t type[4]; 464 uint8_t res2[12]; 465 uint8_t model[16]; 466 uint8_t sequence[16]; 467 uint8_t plant[4]; 468 uint8_t res3[3996]; 469 } SysIB_111; 470 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 471 472 /* Basic Machine CPU */ 473 typedef struct SysIB_121 { 474 uint8_t res1[80]; 475 uint8_t sequence[16]; 476 uint8_t plant[4]; 477 uint8_t res2[2]; 478 uint16_t cpu_addr; 479 uint8_t res3[3992]; 480 } SysIB_121; 481 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 482 483 /* Basic Machine CPUs */ 484 typedef struct SysIB_122 { 485 uint8_t res1[32]; 486 uint32_t capability; 487 uint16_t total_cpus; 488 uint16_t conf_cpus; 489 uint16_t standby_cpus; 490 uint16_t reserved_cpus; 491 uint16_t adjustments[2026]; 492 } SysIB_122; 493 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 494 495 /* LPAR CPU */ 496 typedef struct SysIB_221 { 497 uint8_t res1[80]; 498 uint8_t sequence[16]; 499 uint8_t plant[4]; 500 uint16_t cpu_id; 501 uint16_t cpu_addr; 502 uint8_t res3[3992]; 503 } SysIB_221; 504 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 505 506 /* LPAR CPUs */ 507 typedef struct SysIB_222 { 508 uint8_t res1[32]; 509 uint16_t lpar_num; 510 uint8_t res2; 511 uint8_t lcpuc; 512 uint16_t total_cpus; 513 uint16_t conf_cpus; 514 uint16_t standby_cpus; 515 uint16_t reserved_cpus; 516 uint8_t name[8]; 517 uint32_t caf; 518 uint8_t res3[16]; 519 uint16_t dedicated_cpus; 520 uint16_t shared_cpus; 521 uint8_t res4[4020]; 522 } SysIB_222; 523 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 524 525 /* VM CPUs */ 526 typedef struct SysIB_322 { 527 uint8_t res1[31]; 528 uint8_t count; 529 struct { 530 uint8_t res2[4]; 531 uint16_t total_cpus; 532 uint16_t conf_cpus; 533 uint16_t standby_cpus; 534 uint16_t reserved_cpus; 535 uint8_t name[8]; 536 uint32_t caf; 537 uint8_t cpi[16]; 538 uint8_t res5[3]; 539 uint8_t ext_name_encoding; 540 uint32_t res3; 541 uint8_t uuid[16]; 542 } vm[8]; 543 uint8_t res4[1504]; 544 uint8_t ext_names[8][256]; 545 } SysIB_322; 546 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 547 548 typedef union SysIB { 549 SysIB_111 sysib_111; 550 SysIB_121 sysib_121; 551 SysIB_122 sysib_122; 552 SysIB_221 sysib_221; 553 SysIB_222 sysib_222; 554 SysIB_322 sysib_322; 555 } SysIB; 556 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 557 558 /* MMU defines */ 559 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 560 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 561 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 562 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 563 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 564 #define ASCE_REAL_SPACE 0x20 /* real space control */ 565 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 566 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 567 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 568 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 569 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 570 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 571 572 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 573 #define REGION_ENTRY_P 0x0000000000000200ULL 574 #define REGION_ENTRY_TF 0x00000000000000c0ULL 575 #define REGION_ENTRY_I 0x0000000000000020ULL 576 #define REGION_ENTRY_TT 0x000000000000000cULL 577 #define REGION_ENTRY_TL 0x0000000000000003ULL 578 579 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 580 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 581 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 582 583 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 584 #define REGION3_ENTRY_AV 0x0000000000010000ULL 585 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 586 #define REGION3_ENTRY_F 0x0000000000000800ULL 587 #define REGION3_ENTRY_FC 0x0000000000000400ULL 588 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 589 #define REGION3_ENTRY_CR 0x0000000000000010ULL 590 591 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 592 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 593 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 594 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 595 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 596 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 597 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 598 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 599 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 600 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 601 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 602 603 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 604 605 #define PAGE_ENTRY_0 0x0000000000000800ULL 606 #define PAGE_ENTRY_I 0x0000000000000400ULL 607 #define PAGE_ENTRY_P 0x0000000000000200ULL 608 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 609 610 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 611 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 612 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 613 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 614 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 615 616 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 617 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 618 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 619 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 620 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 621 622 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 623 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 624 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 625 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 626 627 #define SK_C (0x1 << 1) 628 #define SK_R (0x1 << 2) 629 #define SK_F (0x1 << 3) 630 #define SK_ACC_MASK (0xf << 4) 631 632 /* SIGP order codes */ 633 #define SIGP_SENSE 0x01 634 #define SIGP_EXTERNAL_CALL 0x02 635 #define SIGP_EMERGENCY 0x03 636 #define SIGP_START 0x04 637 #define SIGP_STOP 0x05 638 #define SIGP_RESTART 0x06 639 #define SIGP_STOP_STORE_STATUS 0x09 640 #define SIGP_INITIAL_CPU_RESET 0x0b 641 #define SIGP_CPU_RESET 0x0c 642 #define SIGP_SET_PREFIX 0x0d 643 #define SIGP_STORE_STATUS_ADDR 0x0e 644 #define SIGP_SET_ARCH 0x12 645 #define SIGP_COND_EMERGENCY 0x13 646 #define SIGP_SENSE_RUNNING 0x15 647 #define SIGP_STORE_ADTL_STATUS 0x17 648 649 /* SIGP condition codes */ 650 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 651 #define SIGP_CC_STATUS_STORED 1 652 #define SIGP_CC_BUSY 2 653 #define SIGP_CC_NOT_OPERATIONAL 3 654 655 /* SIGP status bits */ 656 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 657 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 658 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 659 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 660 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 661 #define SIGP_STAT_STOPPED 0x00000040UL 662 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 663 #define SIGP_STAT_CHECK_STOP 0x00000010UL 664 #define SIGP_STAT_INOPERATIVE 0x00000004UL 665 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 666 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 667 668 /* SIGP SET ARCHITECTURE modes */ 669 #define SIGP_MODE_ESA_S390 0 670 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1 671 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2 672 673 /* SIGP order code mask corresponding to bit positions 56-63 */ 674 #define SIGP_ORDER_MASK 0x000000ff 675 676 /* machine check interruption code */ 677 678 /* subclasses */ 679 #define MCIC_SC_SD 0x8000000000000000ULL 680 #define MCIC_SC_PD 0x4000000000000000ULL 681 #define MCIC_SC_SR 0x2000000000000000ULL 682 #define MCIC_SC_CD 0x0800000000000000ULL 683 #define MCIC_SC_ED 0x0400000000000000ULL 684 #define MCIC_SC_DG 0x0100000000000000ULL 685 #define MCIC_SC_W 0x0080000000000000ULL 686 #define MCIC_SC_CP 0x0040000000000000ULL 687 #define MCIC_SC_SP 0x0020000000000000ULL 688 #define MCIC_SC_CK 0x0010000000000000ULL 689 690 /* subclass modifiers */ 691 #define MCIC_SCM_B 0x0002000000000000ULL 692 #define MCIC_SCM_DA 0x0000000020000000ULL 693 #define MCIC_SCM_AP 0x0000000000080000ULL 694 695 /* storage errors */ 696 #define MCIC_SE_SE 0x0000800000000000ULL 697 #define MCIC_SE_SC 0x0000400000000000ULL 698 #define MCIC_SE_KE 0x0000200000000000ULL 699 #define MCIC_SE_DS 0x0000100000000000ULL 700 #define MCIC_SE_IE 0x0000000080000000ULL 701 702 /* validity bits */ 703 #define MCIC_VB_WP 0x0000080000000000ULL 704 #define MCIC_VB_MS 0x0000040000000000ULL 705 #define MCIC_VB_PM 0x0000020000000000ULL 706 #define MCIC_VB_IA 0x0000010000000000ULL 707 #define MCIC_VB_FA 0x0000008000000000ULL 708 #define MCIC_VB_VR 0x0000004000000000ULL 709 #define MCIC_VB_EC 0x0000002000000000ULL 710 #define MCIC_VB_FP 0x0000001000000000ULL 711 #define MCIC_VB_GR 0x0000000800000000ULL 712 #define MCIC_VB_CR 0x0000000400000000ULL 713 #define MCIC_VB_ST 0x0000000100000000ULL 714 #define MCIC_VB_AR 0x0000000040000000ULL 715 #define MCIC_VB_GS 0x0000000008000000ULL 716 #define MCIC_VB_PR 0x0000000000200000ULL 717 #define MCIC_VB_FC 0x0000000000100000ULL 718 #define MCIC_VB_CT 0x0000000000020000ULL 719 #define MCIC_VB_CC 0x0000000000010000ULL 720 721 static inline uint64_t s390_build_validity_mcic(void) 722 { 723 uint64_t mcic; 724 725 /* 726 * Indicate all validity bits (no damage) only. Other bits have to be 727 * added by the caller. (storage errors, subclasses and subclass modifiers) 728 */ 729 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 730 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 731 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 732 if (s390_has_feat(S390_FEAT_VECTOR)) { 733 mcic |= MCIC_VB_VR; 734 } 735 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 736 mcic |= MCIC_VB_GS; 737 } 738 return mcic; 739 } 740 741 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 742 { 743 cpu_reset(cs); 744 } 745 746 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 747 { 748 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 749 750 scc->reset(cs, S390_CPU_RESET_NORMAL); 751 } 752 753 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 754 { 755 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 756 757 scc->reset(cs, S390_CPU_RESET_INITIAL); 758 } 759 760 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 761 { 762 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 763 764 scc->load_normal(cs); 765 } 766 767 768 /* cpu.c */ 769 void s390_crypto_reset(void); 770 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit); 771 void s390_set_max_pagesize(uint64_t pagesize, Error **errp); 772 void s390_cmma_reset(void); 773 void s390_enable_css_support(S390CPU *cpu); 774 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 775 int vq, bool assign); 776 #ifndef CONFIG_USER_ONLY 777 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 778 #else 779 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 780 { 781 return 0; 782 } 783 #endif /* CONFIG_USER_ONLY */ 784 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 785 { 786 return cpu->env.cpu_state; 787 } 788 789 790 /* cpu_models.c */ 791 void s390_cpu_list(void); 792 #define cpu_list s390_cpu_list 793 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 794 const S390FeatInit feat_init); 795 796 797 /* helper.c */ 798 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU 799 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX) 800 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 801 802 /* you can call this signal handler from your SIGBUS and SIGSEGV 803 signal handlers to inform the virtual CPU of exceptions. non zero 804 is returned if the signal was handled by the virtual CPU. */ 805 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc); 806 #define cpu_signal_handler cpu_s390x_signal_handler 807 808 809 /* interrupt.c */ 810 void s390_crw_mchk(void); 811 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr, 812 uint32_t io_int_parm, uint32_t io_int_word); 813 #define RA_IGNORED 0 814 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 815 /* service interrupts are floating therefore we must not pass an cpustate */ 816 void s390_sclp_extint(uint32_t parm); 817 818 /* mmu_helper.c */ 819 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 820 int len, bool is_write); 821 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 822 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 823 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 824 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 825 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 826 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 827 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 828 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 829 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 830 831 832 /* sigp.c */ 833 int s390_cpu_restart(S390CPU *cpu); 834 void s390_init_sigp(void); 835 836 837 /* outside of target/s390x/ */ 838 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 839 840 typedef CPUS390XState CPUArchState; 841 typedef S390CPU ArchCPU; 842 843 #include "exec/cpu-all.h" 844 845 #endif 846