1 /* 2 * S/390 virtual CPU header 3 * 4 * For details on the s390x architecture and used definitions (e.g., 5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to 6 * the "z/Architecture Principles of Operations" - a.k.a. PoP. 7 * 8 * Copyright (c) 2009 Ulrich Hecht 9 * Copyright IBM Corp. 2012, 2018 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef S390X_CPU_H 26 #define S390X_CPU_H 27 28 #include "cpu-qom.h" 29 #include "cpu_models.h" 30 #include "exec/cpu-common.h" 31 #include "exec/cpu-defs.h" 32 #include "exec/cpu-interrupt.h" 33 #include "qemu/cpu-float.h" 34 #include "qapi/qapi-types-machine-common.h" 35 36 #define ELF_MACHINE_UNAME "S390X" 37 38 #define TARGET_HAS_PRECISE_SMC 39 40 #define TARGET_INSN_START_EXTRA_WORDS 2 41 42 #define MMU_USER_IDX 0 43 44 #define S390_MAX_CPUS 248 45 46 #ifndef CONFIG_KVM 47 #define S390_ADAPTER_SUPPRESSIBLE 0x01 48 #else 49 #define S390_ADAPTER_SUPPRESSIBLE KVM_S390_ADAPTER_SUPPRESSIBLE 50 #endif 51 52 typedef struct PSW { 53 uint64_t mask; 54 uint64_t addr; 55 } PSW; 56 57 typedef struct CPUArchState { 58 uint64_t regs[16]; /* GP registers */ 59 /* 60 * The floating point registers are part of the vector registers. 61 * vregs[0][0] -> vregs[15][0] are 16 floating point registers 62 */ 63 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */ 64 uint32_t aregs[16]; /* access registers */ 65 uint64_t gscb[4]; /* guarded storage control */ 66 uint64_t etoken; /* etoken */ 67 uint64_t etoken_extension; /* etoken extension */ 68 69 uint64_t diag318_info; 70 71 /* Fields up to this point are not cleared by initial CPU reset */ 72 struct {} start_initial_reset_fields; 73 74 uint32_t fpc; /* floating-point control register */ 75 uint32_t cc_op; 76 bool bpbc; /* branch prediction blocking */ 77 78 float_status fpu_status; /* passed to softfloat lib */ 79 80 PSW psw; 81 82 S390CrashReason crash_reason; 83 84 uint64_t cc_src; 85 uint64_t cc_dst; 86 uint64_t cc_vr; 87 88 uint64_t ex_value; 89 uint64_t ex_target; 90 91 uint64_t __excp_addr; 92 uint64_t psa; 93 94 uint32_t int_pgm_code; 95 uint32_t int_pgm_ilen; 96 97 uint32_t int_svc_code; 98 uint32_t int_svc_ilen; 99 100 uint64_t per_address; 101 uint16_t per_perc_atmid; 102 103 uint64_t cregs[16]; /* control registers */ 104 105 uint64_t ckc; 106 uint64_t cputm; 107 uint32_t todpr; 108 109 uint64_t pfault_token; 110 uint64_t pfault_compare; 111 uint64_t pfault_select; 112 113 uint64_t gbea; 114 uint64_t pp; 115 116 /* Fields up to this point are not cleared by normal CPU reset */ 117 struct {} start_normal_reset_fields; 118 uint8_t riccb[64]; /* runtime instrumentation control */ 119 120 int pending_int; 121 uint16_t external_call_addr; 122 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS); 123 124 #if !defined(CONFIG_USER_ONLY) 125 uint64_t tlb_fill_tec; /* translation exception code during tlb_fill */ 126 int tlb_fill_exc; /* exception number seen during tlb_fill */ 127 #endif 128 129 /* Fields up to this point are cleared by a CPU reset */ 130 struct {} end_reset_fields; 131 132 #if !defined(CONFIG_USER_ONLY) 133 uint32_t core_id; /* PoP "CPU address", same as cpu_index */ 134 int32_t socket_id; 135 int32_t book_id; 136 int32_t drawer_id; 137 bool dedicated; 138 S390CpuEntitlement entitlement; /* Used only for vertical polarization */ 139 uint64_t cpuid; 140 #endif 141 142 QEMUTimer *tod_timer; 143 144 QEMUTimer *cpu_timer; 145 146 /* 147 * The cpu state represents the logical state of a cpu. In contrast to other 148 * architectures, there is a difference between a halt and a stop on s390. 149 * If all cpus are either stopped (including check stop) or in the disabled 150 * wait state, the vm can be shut down. 151 * The acceptable cpu_state values are defined in the CpuInfoS390State 152 * enum. 153 */ 154 uint8_t cpu_state; 155 156 /* currently processed sigp order */ 157 uint8_t sigp_order; 158 159 } CPUS390XState; 160 161 static inline uint64_t *get_freg(CPUS390XState *cs, int nr) 162 { 163 return &cs->vregs[nr][0]; 164 } 165 166 /** 167 * S390CPU: 168 * @env: #CPUS390XState. 169 * 170 * An S/390 CPU. 171 */ 172 struct ArchCPU { 173 CPUState parent_obj; 174 175 CPUS390XState env; 176 S390CPUModel *model; 177 /* needed for live migration */ 178 void *irqstate; 179 uint32_t irqstate_saved_size; 180 }; 181 182 /** 183 * S390CPUClass: 184 * @parent_realize: The parent class' realize handler. 185 * @parent_phases: The parent class' reset phase handlers. 186 * @load_normal: Performs a load normal. 187 * 188 * An S/390 CPU model. 189 */ 190 struct S390CPUClass { 191 CPUClass parent_class; 192 193 const S390CPUDef *cpu_def; 194 bool kvm_required; 195 bool is_static; 196 bool is_migration_safe; 197 const char *desc; 198 199 DeviceRealize parent_realize; 200 ResettablePhases parent_phases; 201 void (*load_normal)(CPUState *cpu); 202 }; 203 204 #ifndef CONFIG_USER_ONLY 205 extern const VMStateDescription vmstate_s390_cpu; 206 #endif 207 208 /* distinguish between 24 bit and 31 bit addressing */ 209 #define HIGH_ORDER_BIT 0x80000000 210 211 /* Interrupt Codes */ 212 /* Program Interrupts */ 213 #define PGM_OPERATION 0x0001 214 #define PGM_PRIVILEGED 0x0002 215 #define PGM_EXECUTE 0x0003 216 #define PGM_PROTECTION 0x0004 217 #define PGM_ADDRESSING 0x0005 218 #define PGM_SPECIFICATION 0x0006 219 #define PGM_DATA 0x0007 220 #define PGM_FIXPT_OVERFLOW 0x0008 221 #define PGM_FIXPT_DIVIDE 0x0009 222 #define PGM_DEC_OVERFLOW 0x000a 223 #define PGM_DEC_DIVIDE 0x000b 224 #define PGM_HFP_EXP_OVERFLOW 0x000c 225 #define PGM_HFP_EXP_UNDERFLOW 0x000d 226 #define PGM_HFP_SIGNIFICANCE 0x000e 227 #define PGM_HFP_DIVIDE 0x000f 228 #define PGM_SEGMENT_TRANS 0x0010 229 #define PGM_PAGE_TRANS 0x0011 230 #define PGM_TRANS_SPEC 0x0012 231 #define PGM_SPECIAL_OP 0x0013 232 #define PGM_OPERAND 0x0015 233 #define PGM_TRACE_TABLE 0x0016 234 #define PGM_VECTOR_PROCESSING 0x001b 235 #define PGM_SPACE_SWITCH 0x001c 236 #define PGM_HFP_SQRT 0x001d 237 #define PGM_PC_TRANS_SPEC 0x001f 238 #define PGM_AFX_TRANS 0x0020 239 #define PGM_ASX_TRANS 0x0021 240 #define PGM_LX_TRANS 0x0022 241 #define PGM_EX_TRANS 0x0023 242 #define PGM_PRIM_AUTH 0x0024 243 #define PGM_SEC_AUTH 0x0025 244 #define PGM_ALET_SPEC 0x0028 245 #define PGM_ALEN_SPEC 0x0029 246 #define PGM_ALE_SEQ 0x002a 247 #define PGM_ASTE_VALID 0x002b 248 #define PGM_ASTE_SEQ 0x002c 249 #define PGM_EXT_AUTH 0x002d 250 #define PGM_STACK_FULL 0x0030 251 #define PGM_STACK_EMPTY 0x0031 252 #define PGM_STACK_SPEC 0x0032 253 #define PGM_STACK_TYPE 0x0033 254 #define PGM_STACK_OP 0x0034 255 #define PGM_ASCE_TYPE 0x0038 256 #define PGM_REG_FIRST_TRANS 0x0039 257 #define PGM_REG_SEC_TRANS 0x003a 258 #define PGM_REG_THIRD_TRANS 0x003b 259 #define PGM_MONITOR 0x0040 260 #define PGM_PER 0x0080 261 #define PGM_CRYPTO 0x0119 262 263 /* External Interrupts */ 264 #define EXT_INTERRUPT_KEY 0x0040 265 #define EXT_CLOCK_COMP 0x1004 266 #define EXT_CPU_TIMER 0x1005 267 #define EXT_MALFUNCTION 0x1200 268 #define EXT_EMERGENCY 0x1201 269 #define EXT_EXTERNAL_CALL 0x1202 270 #define EXT_ETR 0x1406 271 #define EXT_SERVICE 0x2401 272 #define EXT_VIRTIO 0x2603 273 274 /* PSW defines */ 275 #undef PSW_MASK_PER 276 #undef PSW_MASK_UNUSED_2 277 #undef PSW_MASK_UNUSED_3 278 #undef PSW_MASK_DAT 279 #undef PSW_MASK_IO 280 #undef PSW_MASK_EXT 281 #undef PSW_MASK_KEY 282 #undef PSW_SHIFT_KEY 283 #undef PSW_MASK_MCHECK 284 #undef PSW_MASK_WAIT 285 #undef PSW_MASK_PSTATE 286 #undef PSW_MASK_ASC 287 #undef PSW_SHIFT_ASC 288 #undef PSW_MASK_CC 289 #undef PSW_MASK_PM 290 #undef PSW_MASK_RI 291 #undef PSW_SHIFT_MASK_PM 292 #undef PSW_MASK_64 293 #undef PSW_MASK_32 294 #undef PSW_MASK_ESA_ADDR 295 296 #define PSW_MASK_PER 0x4000000000000000ULL 297 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL 298 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL 299 #define PSW_MASK_DAT 0x0400000000000000ULL 300 #define PSW_MASK_IO 0x0200000000000000ULL 301 #define PSW_MASK_EXT 0x0100000000000000ULL 302 #define PSW_MASK_KEY 0x00F0000000000000ULL 303 #define PSW_SHIFT_KEY 52 304 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL 305 #define PSW_MASK_MCHECK 0x0004000000000000ULL 306 #define PSW_MASK_WAIT 0x0002000000000000ULL 307 #define PSW_MASK_PSTATE 0x0001000000000000ULL 308 #define PSW_MASK_ASC 0x0000C00000000000ULL 309 #define PSW_SHIFT_ASC 46 310 #define PSW_MASK_CC 0x0000300000000000ULL 311 #define PSW_MASK_PM 0x00000F0000000000ULL 312 #define PSW_SHIFT_MASK_PM 40 313 #define PSW_MASK_RI 0x0000008000000000ULL 314 #define PSW_MASK_64 0x0000000100000000ULL 315 #define PSW_MASK_32 0x0000000080000000ULL 316 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL 317 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL 318 #define PSW_MASK_RESERVED 0xb80800fe7fffffffULL 319 320 #undef PSW_ASC_PRIMARY 321 #undef PSW_ASC_ACCREG 322 #undef PSW_ASC_SECONDARY 323 #undef PSW_ASC_HOME 324 325 #define PSW_ASC_PRIMARY 0x0000000000000000ULL 326 #define PSW_ASC_ACCREG 0x0000400000000000ULL 327 #define PSW_ASC_SECONDARY 0x0000800000000000ULL 328 #define PSW_ASC_HOME 0x0000C00000000000ULL 329 330 /* the address space values shifted */ 331 #define AS_PRIMARY 0 332 #define AS_ACCREG 1 333 #define AS_SECONDARY 2 334 #define AS_HOME 3 335 336 /* tb flags */ 337 338 #define FLAG_MASK_PSW_SHIFT 31 339 #define FLAG_MASK_32 0x00000001u 340 #define FLAG_MASK_64 0x00000002u 341 #define FLAG_MASK_AFP 0x00000004u 342 #define FLAG_MASK_VECTOR 0x00000008u 343 #define FLAG_MASK_ASC 0x00018000u 344 #define FLAG_MASK_PSTATE 0x00020000u 345 #define FLAG_MASK_PER_IFETCH_NULLIFY 0x01000000u 346 #define FLAG_MASK_DAT 0x08000000u 347 #define FLAG_MASK_PER_STORE_REAL 0x20000000u 348 #define FLAG_MASK_PER_IFETCH 0x40000000u 349 #define FLAG_MASK_PER_BRANCH 0x80000000u 350 351 QEMU_BUILD_BUG_ON(FLAG_MASK_32 != PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT); 352 QEMU_BUILD_BUG_ON(FLAG_MASK_64 != PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT); 353 QEMU_BUILD_BUG_ON(FLAG_MASK_ASC != PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT); 354 QEMU_BUILD_BUG_ON(FLAG_MASK_PSTATE != PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT); 355 QEMU_BUILD_BUG_ON(FLAG_MASK_DAT != PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT); 356 357 #define FLAG_MASK_PSW (FLAG_MASK_DAT | FLAG_MASK_PSTATE | \ 358 FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32) 359 #define FLAG_MASK_CR9 (FLAG_MASK_PER_BRANCH | FLAG_MASK_PER_IFETCH) 360 #define FLAG_MASK_PER (FLAG_MASK_PER_BRANCH | \ 361 FLAG_MASK_PER_IFETCH | \ 362 FLAG_MASK_PER_IFETCH_NULLIFY | \ 363 FLAG_MASK_PER_STORE_REAL) 364 365 /* Control register 0 bits */ 366 #define CR0_LOWPROT 0x0000000010000000ULL 367 #define CR0_SECONDARY 0x0000000004000000ULL 368 #define CR0_EDAT 0x0000000000800000ULL 369 #define CR0_AFP 0x0000000000040000ULL 370 #define CR0_VECTOR 0x0000000000020000ULL 371 #define CR0_IEP 0x0000000000100000ULL 372 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL 373 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL 374 #define CR0_CKC_SC 0x0000000000000800ULL 375 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL 376 #define CR0_SERVICE_SC 0x0000000000000200ULL 377 378 /* Control register 14 bits */ 379 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL 380 381 /* MMU */ 382 #define MMU_PRIMARY_IDX 0 383 #define MMU_SECONDARY_IDX 1 384 #define MMU_HOME_IDX 2 385 #define MMU_REAL_IDX 3 386 387 static inline int s390x_env_mmu_index(CPUS390XState *env, bool ifetch) 388 { 389 #ifdef CONFIG_USER_ONLY 390 return MMU_USER_IDX; 391 #else 392 if (!(env->psw.mask & PSW_MASK_DAT)) { 393 return MMU_REAL_IDX; 394 } 395 396 if (ifetch) { 397 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) { 398 return MMU_HOME_IDX; 399 } 400 return MMU_PRIMARY_IDX; 401 } 402 403 switch (env->psw.mask & PSW_MASK_ASC) { 404 case PSW_ASC_PRIMARY: 405 return MMU_PRIMARY_IDX; 406 case PSW_ASC_SECONDARY: 407 return MMU_SECONDARY_IDX; 408 case PSW_ASC_HOME: 409 return MMU_HOME_IDX; 410 case PSW_ASC_ACCREG: 411 /* Fallthrough: access register mode is not yet supported */ 412 default: 413 abort(); 414 } 415 #endif 416 } 417 418 #ifdef CONFIG_TCG 419 420 #include "tcg/tcg_s390x.h" 421 422 void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc, 423 uint64_t *cs_base, uint32_t *flags); 424 425 #endif /* CONFIG_TCG */ 426 427 /* PER bits from control register 9 */ 428 #define PER_CR9_EVENT_BRANCH 0x80000000 429 #define PER_CR9_EVENT_IFETCH 0x40000000 430 #define PER_CR9_EVENT_STORE 0x20000000 431 #define PER_CR9_EVENT_STORAGE_KEY_ALTERATION 0x10000000 432 #define PER_CR9_EVENT_STORE_REAL 0x08000000 433 #define PER_CR9_EVENT_ZERO_ADDRESS_DETECTION 0x04000000 434 #define PER_CR9_EVENT_TRANSACTION_END 0x02000000 435 #define PER_CR9_EVENT_IFETCH_NULLIFICATION 0x01000000 436 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000 437 #define PER_CR9_CONTROL_TRANSACTION_SUPRESS 0x00400000 438 #define PER_CR9_CONTROL_STORAGE_ALTERATION 0x00200000 439 440 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_BRANCH != PER_CR9_EVENT_BRANCH); 441 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH != PER_CR9_EVENT_IFETCH); 442 QEMU_BUILD_BUG_ON(FLAG_MASK_PER_IFETCH_NULLIFY != 443 PER_CR9_EVENT_IFETCH_NULLIFICATION); 444 445 /* PER bits from the PER CODE/ATMID/AI in lowcore */ 446 #define PER_CODE_EVENT_BRANCH 0x8000 447 #define PER_CODE_EVENT_IFETCH 0x4000 448 #define PER_CODE_EVENT_STORE 0x2000 449 #define PER_CODE_EVENT_STORE_REAL 0x0800 450 #define PER_CODE_EVENT_NULLIFICATION 0x0100 451 452 #define EXCP_EXT 1 /* external interrupt */ 453 #define EXCP_SVC 2 /* supervisor call (syscall) */ 454 #define EXCP_PGM 3 /* program interruption */ 455 #define EXCP_RESTART 4 /* restart interrupt */ 456 #define EXCP_STOP 5 /* stop interrupt */ 457 #define EXCP_IO 7 /* I/O interrupt */ 458 #define EXCP_MCHK 8 /* machine check */ 459 460 #define INTERRUPT_EXT_CPU_TIMER (1 << 3) 461 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4) 462 #define INTERRUPT_EXTERNAL_CALL (1 << 5) 463 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6) 464 #define INTERRUPT_RESTART (1 << 7) 465 #define INTERRUPT_STOP (1 << 8) 466 467 /* Program Status Word. */ 468 #define S390_PSWM_REGNUM 0 469 #define S390_PSWA_REGNUM 1 470 /* General Purpose Registers. */ 471 #define S390_R0_REGNUM 2 472 #define S390_R1_REGNUM 3 473 #define S390_R2_REGNUM 4 474 #define S390_R3_REGNUM 5 475 #define S390_R4_REGNUM 6 476 #define S390_R5_REGNUM 7 477 #define S390_R6_REGNUM 8 478 #define S390_R7_REGNUM 9 479 #define S390_R8_REGNUM 10 480 #define S390_R9_REGNUM 11 481 #define S390_R10_REGNUM 12 482 #define S390_R11_REGNUM 13 483 #define S390_R12_REGNUM 14 484 #define S390_R13_REGNUM 15 485 #define S390_R14_REGNUM 16 486 #define S390_R15_REGNUM 17 487 488 static inline void setcc(S390CPU *cpu, uint64_t cc) 489 { 490 CPUS390XState *env = &cpu->env; 491 492 env->psw.mask &= ~(3ull << 44); 493 env->psw.mask |= (cc & 3) << 44; 494 env->cc_op = cc; 495 } 496 497 /* STSI */ 498 #define STSI_R0_FC_MASK 0x00000000f0000000ULL 499 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL 500 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL 501 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL 502 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL 503 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL 504 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL 505 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL 506 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL 507 508 /* Basic Machine Configuration */ 509 typedef struct SysIB_111 { 510 uint8_t res1[32]; 511 uint8_t manuf[16]; 512 uint8_t type[4]; 513 uint8_t res2[12]; 514 uint8_t model[16]; 515 uint8_t sequence[16]; 516 uint8_t plant[4]; 517 uint8_t res3[3996]; 518 } SysIB_111; 519 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096); 520 521 /* Basic Machine CPU */ 522 typedef struct SysIB_121 { 523 uint8_t res1[80]; 524 uint8_t sequence[16]; 525 uint8_t plant[4]; 526 uint8_t res2[2]; 527 uint16_t cpu_addr; 528 uint8_t res3[3992]; 529 } SysIB_121; 530 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096); 531 532 /* Basic Machine CPUs */ 533 typedef struct SysIB_122 { 534 uint8_t res1[32]; 535 uint32_t capability; 536 uint16_t total_cpus; 537 uint16_t conf_cpus; 538 uint16_t standby_cpus; 539 uint16_t reserved_cpus; 540 uint16_t adjustments[2026]; 541 } SysIB_122; 542 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096); 543 544 /* LPAR CPU */ 545 typedef struct SysIB_221 { 546 uint8_t res1[80]; 547 uint8_t sequence[16]; 548 uint8_t plant[4]; 549 uint16_t cpu_id; 550 uint16_t cpu_addr; 551 uint8_t res3[3992]; 552 } SysIB_221; 553 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096); 554 555 /* LPAR CPUs */ 556 typedef struct SysIB_222 { 557 uint8_t res1[32]; 558 uint16_t lpar_num; 559 uint8_t res2; 560 uint8_t lcpuc; 561 uint16_t total_cpus; 562 uint16_t conf_cpus; 563 uint16_t standby_cpus; 564 uint16_t reserved_cpus; 565 uint8_t name[8]; 566 uint32_t caf; 567 uint8_t res3[16]; 568 uint16_t dedicated_cpus; 569 uint16_t shared_cpus; 570 uint8_t res4[4020]; 571 } SysIB_222; 572 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096); 573 574 /* VM CPUs */ 575 typedef struct SysIB_322 { 576 uint8_t res1[31]; 577 uint8_t count; 578 struct { 579 uint8_t res2[4]; 580 uint16_t total_cpus; 581 uint16_t conf_cpus; 582 uint16_t standby_cpus; 583 uint16_t reserved_cpus; 584 uint8_t name[8]; 585 uint32_t caf; 586 uint8_t cpi[16]; 587 uint8_t res5[3]; 588 uint8_t ext_name_encoding; 589 uint32_t res3; 590 uint8_t uuid[16]; 591 } vm[8]; 592 uint8_t res4[1504]; 593 uint8_t ext_names[8][256]; 594 } SysIB_322; 595 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096); 596 597 /* 598 * Topology Magnitude fields (MAG) indicates the maximum number of 599 * topology list entries (TLE) at the corresponding nesting level. 600 */ 601 #define S390_TOPOLOGY_MAG 6 602 #define S390_TOPOLOGY_MAG6 0 603 #define S390_TOPOLOGY_MAG5 1 604 #define S390_TOPOLOGY_MAG4 2 605 #define S390_TOPOLOGY_MAG3 3 606 #define S390_TOPOLOGY_MAG2 4 607 #define S390_TOPOLOGY_MAG1 5 608 /* Configuration topology */ 609 typedef struct SysIB_151x { 610 uint8_t reserved0[2]; 611 uint16_t length; 612 uint8_t mag[S390_TOPOLOGY_MAG]; 613 uint8_t reserved1; 614 uint8_t mnest; 615 uint32_t reserved2; 616 char tle[]; 617 } SysIB_151x; 618 QEMU_BUILD_BUG_ON(sizeof(SysIB_151x) != 16); 619 620 typedef union SysIB { 621 SysIB_111 sysib_111; 622 SysIB_121 sysib_121; 623 SysIB_122 sysib_122; 624 SysIB_221 sysib_221; 625 SysIB_222 sysib_222; 626 SysIB_322 sysib_322; 627 SysIB_151x sysib_151x; 628 } SysIB; 629 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096); 630 631 /* 632 * CPU Topology List provided by STSI with fc=15 provides a list 633 * of two different Topology List Entries (TLE) types to specify 634 * the topology hierarchy. 635 * 636 * - Container Topology List Entry 637 * Defines a container to contain other Topology List Entries 638 * of any type, nested containers or CPU. 639 * - CPU Topology List Entry 640 * Specifies the CPUs position, type, entitlement and polarization 641 * of the CPUs contained in the last container TLE. 642 * 643 * There can be theoretically up to five levels of containers, QEMU 644 * uses only three levels, the drawer's, book's and socket's level. 645 * 646 * A container with a nesting level (NL) greater than 1 can only 647 * contain another container of nesting level NL-1. 648 * 649 * A container of nesting level 1 (socket), contains as many CPU TLE 650 * as needed to describe the position and qualities of all CPUs inside 651 * the container. 652 * The qualities of a CPU are polarization, entitlement and type. 653 * 654 * The CPU TLE defines the position of the CPUs of identical qualities 655 * using a 64bits mask which first bit has its offset defined by 656 * the CPU address origin field of the CPU TLE like in: 657 * CPU address = origin * 64 + bit position within the mask 658 */ 659 /* Container type Topology List Entry */ 660 typedef struct SYSIBContainerListEntry { 661 uint8_t nl; 662 uint8_t reserved[6]; 663 uint8_t id; 664 } SYSIBContainerListEntry; 665 QEMU_BUILD_BUG_ON(sizeof(SYSIBContainerListEntry) != 8); 666 667 /* CPU type Topology List Entry */ 668 typedef struct SysIBCPUListEntry { 669 uint8_t nl; 670 uint8_t reserved0[3]; 671 #define SYSIB_TLE_POLARITY_MASK 0x03 672 #define SYSIB_TLE_DEDICATED 0x04 673 uint8_t flags; 674 uint8_t type; 675 uint16_t origin; 676 uint64_t mask; 677 } SysIBCPUListEntry; 678 QEMU_BUILD_BUG_ON(sizeof(SysIBCPUListEntry) != 16); 679 680 void insert_stsi_15_1_x(S390CPU *cpu, int sel2, uint64_t addr, uint8_t ar, uintptr_t ra); 681 void s390_cpu_topology_set_changed(bool changed); 682 683 /* MMU defines */ 684 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */ 685 #define ASCE_SUBSPACE 0x200 /* subspace group control */ 686 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */ 687 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */ 688 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */ 689 #define ASCE_REAL_SPACE 0x20 /* real space control */ 690 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */ 691 #define ASCE_TYPE_REGION1 0x0c /* region first table type */ 692 #define ASCE_TYPE_REGION2 0x08 /* region second table type */ 693 #define ASCE_TYPE_REGION3 0x04 /* region third table type */ 694 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */ 695 #define ASCE_TABLE_LENGTH 0x03 /* region table length */ 696 697 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL 698 #define REGION_ENTRY_P 0x0000000000000200ULL 699 #define REGION_ENTRY_TF 0x00000000000000c0ULL 700 #define REGION_ENTRY_I 0x0000000000000020ULL 701 #define REGION_ENTRY_TT 0x000000000000000cULL 702 #define REGION_ENTRY_TL 0x0000000000000003ULL 703 704 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL 705 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL 706 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL 707 708 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL 709 #define REGION3_ENTRY_AV 0x0000000000010000ULL 710 #define REGION3_ENTRY_ACC 0x000000000000f000ULL 711 #define REGION3_ENTRY_F 0x0000000000000800ULL 712 #define REGION3_ENTRY_FC 0x0000000000000400ULL 713 #define REGION3_ENTRY_IEP 0x0000000000000100ULL 714 #define REGION3_ENTRY_CR 0x0000000000000010ULL 715 716 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL 717 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL 718 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL 719 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL 720 #define SEGMENT_ENTRY_F 0x0000000000000800ULL 721 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL 722 #define SEGMENT_ENTRY_P 0x0000000000000200ULL 723 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL 724 #define SEGMENT_ENTRY_I 0x0000000000000020ULL 725 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL 726 #define SEGMENT_ENTRY_TT 0x000000000000000cULL 727 728 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL 729 730 #define PAGE_ENTRY_0 0x0000000000000800ULL 731 #define PAGE_ENTRY_I 0x0000000000000400ULL 732 #define PAGE_ENTRY_P 0x0000000000000200ULL 733 #define PAGE_ENTRY_IEP 0x0000000000000100ULL 734 735 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL 736 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL 737 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL 738 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL 739 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL 740 741 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53) 742 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42) 743 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31) 744 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20) 745 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12) 746 747 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62) 748 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51) 749 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40) 750 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29) 751 752 #define SK_C (0x1 << 1) 753 #define SK_R (0x1 << 2) 754 #define SK_F (0x1 << 3) 755 #define SK_ACC_MASK (0xf << 4) 756 757 /* SIGP order codes */ 758 #define SIGP_SENSE 0x01 759 #define SIGP_EXTERNAL_CALL 0x02 760 #define SIGP_EMERGENCY 0x03 761 #define SIGP_START 0x04 762 #define SIGP_STOP 0x05 763 #define SIGP_RESTART 0x06 764 #define SIGP_STOP_STORE_STATUS 0x09 765 #define SIGP_INITIAL_CPU_RESET 0x0b 766 #define SIGP_CPU_RESET 0x0c 767 #define SIGP_SET_PREFIX 0x0d 768 #define SIGP_STORE_STATUS_ADDR 0x0e 769 #define SIGP_SET_ARCH 0x12 770 #define SIGP_COND_EMERGENCY 0x13 771 #define SIGP_SENSE_RUNNING 0x15 772 #define SIGP_STORE_ADTL_STATUS 0x17 773 774 /* SIGP condition codes */ 775 #define SIGP_CC_ORDER_CODE_ACCEPTED 0 776 #define SIGP_CC_STATUS_STORED 1 777 #define SIGP_CC_BUSY 2 778 #define SIGP_CC_NOT_OPERATIONAL 3 779 780 /* SIGP status bits */ 781 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL 782 #define SIGP_STAT_NOT_RUNNING 0x00000400UL 783 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL 784 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL 785 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL 786 #define SIGP_STAT_STOPPED 0x00000040UL 787 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL 788 #define SIGP_STAT_CHECK_STOP 0x00000010UL 789 #define SIGP_STAT_INOPERATIVE 0x00000004UL 790 #define SIGP_STAT_INVALID_ORDER 0x00000002UL 791 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL 792 793 /* SIGP order code mask corresponding to bit positions 56-63 */ 794 #define SIGP_ORDER_MASK 0x000000ff 795 796 /* machine check interruption code */ 797 798 /* subclasses */ 799 #define MCIC_SC_SD 0x8000000000000000ULL 800 #define MCIC_SC_PD 0x4000000000000000ULL 801 #define MCIC_SC_SR 0x2000000000000000ULL 802 #define MCIC_SC_CD 0x0800000000000000ULL 803 #define MCIC_SC_ED 0x0400000000000000ULL 804 #define MCIC_SC_DG 0x0100000000000000ULL 805 #define MCIC_SC_W 0x0080000000000000ULL 806 #define MCIC_SC_CP 0x0040000000000000ULL 807 #define MCIC_SC_SP 0x0020000000000000ULL 808 #define MCIC_SC_CK 0x0010000000000000ULL 809 810 /* subclass modifiers */ 811 #define MCIC_SCM_B 0x0002000000000000ULL 812 #define MCIC_SCM_DA 0x0000000020000000ULL 813 #define MCIC_SCM_AP 0x0000000000080000ULL 814 815 /* storage errors */ 816 #define MCIC_SE_SE 0x0000800000000000ULL 817 #define MCIC_SE_SC 0x0000400000000000ULL 818 #define MCIC_SE_KE 0x0000200000000000ULL 819 #define MCIC_SE_DS 0x0000100000000000ULL 820 #define MCIC_SE_IE 0x0000000080000000ULL 821 822 /* validity bits */ 823 #define MCIC_VB_WP 0x0000080000000000ULL 824 #define MCIC_VB_MS 0x0000040000000000ULL 825 #define MCIC_VB_PM 0x0000020000000000ULL 826 #define MCIC_VB_IA 0x0000010000000000ULL 827 #define MCIC_VB_FA 0x0000008000000000ULL 828 #define MCIC_VB_VR 0x0000004000000000ULL 829 #define MCIC_VB_EC 0x0000002000000000ULL 830 #define MCIC_VB_FP 0x0000001000000000ULL 831 #define MCIC_VB_GR 0x0000000800000000ULL 832 #define MCIC_VB_CR 0x0000000400000000ULL 833 #define MCIC_VB_ST 0x0000000100000000ULL 834 #define MCIC_VB_AR 0x0000000040000000ULL 835 #define MCIC_VB_GS 0x0000000008000000ULL 836 #define MCIC_VB_PR 0x0000000000200000ULL 837 #define MCIC_VB_FC 0x0000000000100000ULL 838 #define MCIC_VB_CT 0x0000000000020000ULL 839 #define MCIC_VB_CC 0x0000000000010000ULL 840 841 static inline uint64_t s390_build_validity_mcic(void) 842 { 843 uint64_t mcic; 844 845 /* 846 * Indicate all validity bits (no damage) only. Other bits have to be 847 * added by the caller. (storage errors, subclasses and subclass modifiers) 848 */ 849 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP | 850 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR | 851 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC; 852 if (s390_has_feat(S390_FEAT_VECTOR)) { 853 mcic |= MCIC_VB_VR; 854 } 855 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) { 856 mcic |= MCIC_VB_GS; 857 } 858 return mcic; 859 } 860 861 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg) 862 { 863 cpu_reset(cs); 864 } 865 866 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg) 867 { 868 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_NORMAL); 869 } 870 871 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg) 872 { 873 resettable_reset(OBJECT(cs), RESET_TYPE_S390_CPU_INITIAL); 874 } 875 876 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg) 877 { 878 S390CPUClass *scc = S390_CPU_GET_CLASS(cs); 879 880 scc->load_normal(cs); 881 } 882 883 884 /* cpu.c */ 885 void s390_crypto_reset(void); 886 void s390_cmma_reset(void); 887 void s390_enable_css_support(S390CPU *cpu); 888 void s390_do_cpu_set_diag318(CPUState *cs, run_on_cpu_data arg); 889 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id, 890 int vq, bool assign); 891 #ifndef CONFIG_USER_ONLY 892 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu); 893 #else 894 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu) 895 { 896 return 0; 897 } 898 #endif /* CONFIG_USER_ONLY */ 899 static inline uint8_t s390_cpu_get_state(S390CPU *cpu) 900 { 901 return cpu->env.cpu_state; 902 } 903 904 905 /* cpu_models.c */ 906 void s390_cpu_list(void); 907 #define cpu_list s390_cpu_list 908 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga, 909 const S390FeatInit feat_init); 910 911 912 /* helper.c */ 913 #define CPU_RESOLVING_TYPE TYPE_S390_CPU 914 915 /* interrupt.c */ 916 #define RA_IGNORED 0 917 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra); 918 /* service interrupts are floating therefore we must not pass an cpustate */ 919 void s390_sclp_extint(uint32_t parm); 920 921 /* mmu_helper.c */ 922 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf, 923 int len, bool is_write); 924 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \ 925 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false) 926 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \ 927 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true) 928 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \ 929 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false) 930 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \ 931 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true) 932 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra); 933 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf, 934 int len, bool is_write); 935 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \ 936 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false) 937 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \ 938 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true) 939 940 /* sigp.c */ 941 int s390_cpu_restart(S390CPU *cpu); 942 void s390_init_sigp(void); 943 944 /* helper.c */ 945 void s390_cpu_set_psw(CPUS390XState *env, uint64_t mask, uint64_t addr); 946 uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); 947 948 /* outside of target/s390x/ */ 949 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); 950 951 #endif 952