1 /* 2 * RX emulation definition 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RX_CPU_H 20 #define RX_CPU_H 21 22 #include "qemu/bitops.h" 23 #include "hw/registerfields.h" 24 #include "cpu-qom.h" 25 26 #include "exec/cpu-defs.h" 27 28 /* PSW define */ 29 REG32(PSW, 0) 30 FIELD(PSW, C, 0, 1) 31 FIELD(PSW, Z, 1, 1) 32 FIELD(PSW, S, 2, 1) 33 FIELD(PSW, O, 3, 1) 34 FIELD(PSW, I, 16, 1) 35 FIELD(PSW, U, 17, 1) 36 FIELD(PSW, PM, 20, 1) 37 FIELD(PSW, IPL, 24, 4) 38 39 /* FPSW define */ 40 REG32(FPSW, 0) 41 FIELD(FPSW, RM, 0, 2) 42 FIELD(FPSW, CV, 2, 1) 43 FIELD(FPSW, CO, 3, 1) 44 FIELD(FPSW, CZ, 4, 1) 45 FIELD(FPSW, CU, 5, 1) 46 FIELD(FPSW, CX, 6, 1) 47 FIELD(FPSW, CE, 7, 1) 48 FIELD(FPSW, CAUSE, 2, 6) 49 FIELD(FPSW, DN, 8, 1) 50 FIELD(FPSW, EV, 10, 1) 51 FIELD(FPSW, EO, 11, 1) 52 FIELD(FPSW, EZ, 12, 1) 53 FIELD(FPSW, EU, 13, 1) 54 FIELD(FPSW, EX, 14, 1) 55 FIELD(FPSW, ENABLE, 10, 5) 56 FIELD(FPSW, FV, 26, 1) 57 FIELD(FPSW, FO, 27, 1) 58 FIELD(FPSW, FZ, 28, 1) 59 FIELD(FPSW, FU, 29, 1) 60 FIELD(FPSW, FX, 30, 1) 61 FIELD(FPSW, FLAGS, 26, 4) 62 FIELD(FPSW, FS, 31, 1) 63 64 enum { 65 NUM_REGS = 16, 66 }; 67 68 typedef struct CPURXState { 69 /* CPU registers */ 70 uint32_t regs[NUM_REGS]; /* general registers */ 71 uint32_t psw_o; /* O bit of status register */ 72 uint32_t psw_s; /* S bit of status register */ 73 uint32_t psw_z; /* Z bit of status register */ 74 uint32_t psw_c; /* C bit of status register */ 75 uint32_t psw_u; 76 uint32_t psw_i; 77 uint32_t psw_pm; 78 uint32_t psw_ipl; 79 uint32_t bpsw; /* backup status */ 80 uint32_t bpc; /* backup pc */ 81 uint32_t isp; /* global base register */ 82 uint32_t usp; /* vector base register */ 83 uint32_t pc; /* program counter */ 84 uint32_t intb; /* interrupt vector */ 85 uint32_t fintv; 86 uint32_t fpsw; 87 uint64_t acc; 88 89 /* Fields up to this point are cleared by a CPU reset */ 90 struct {} end_reset_fields; 91 92 /* Internal use */ 93 uint32_t in_sleep; 94 uint32_t req_irq; /* Requested interrupt no (hard) */ 95 uint32_t req_ipl; /* Requested interrupt level */ 96 uint32_t ack_irq; /* execute irq */ 97 uint32_t ack_ipl; /* execute ipl */ 98 float_status fp_status; 99 qemu_irq ack; /* Interrupt acknowledge */ 100 } CPURXState; 101 102 /* 103 * RXCPU: 104 * @env: #CPURXState 105 * 106 * A RX CPU 107 */ 108 struct RXCPU { 109 /*< private >*/ 110 CPUState parent_obj; 111 /*< public >*/ 112 113 CPUNegativeOffsetState neg; 114 CPURXState env; 115 }; 116 117 typedef RXCPU ArchCPU; 118 119 #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU 120 #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX 121 #define CPU_RESOLVING_TYPE TYPE_RX_CPU 122 123 const char *rx_crname(uint8_t cr); 124 #ifndef CONFIG_USER_ONLY 125 void rx_cpu_do_interrupt(CPUState *cpu); 126 bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); 127 #endif /* !CONFIG_USER_ONLY */ 128 void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 129 int rx_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 130 int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 131 hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 132 133 void rx_translate_init(void); 134 void rx_cpu_list(void); 135 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); 136 137 #define cpu_list rx_cpu_list 138 139 #include "exec/cpu-all.h" 140 141 #define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 142 #define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 143 144 #define RX_CPU_IRQ 0 145 #define RX_CPU_FIR 1 146 147 static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, 148 target_ulong *cs_base, uint32_t *flags) 149 { 150 *pc = env->pc; 151 *cs_base = 0; 152 *flags = FIELD_DP32(0, PSW, PM, env->psw_pm); 153 } 154 155 static inline int cpu_mmu_index(CPURXState *env, bool ifetch) 156 { 157 return 0; 158 } 159 160 static inline uint32_t rx_cpu_pack_psw(CPURXState *env) 161 { 162 uint32_t psw = 0; 163 psw = FIELD_DP32(psw, PSW, IPL, env->psw_ipl); 164 psw = FIELD_DP32(psw, PSW, PM, env->psw_pm); 165 psw = FIELD_DP32(psw, PSW, U, env->psw_u); 166 psw = FIELD_DP32(psw, PSW, I, env->psw_i); 167 psw = FIELD_DP32(psw, PSW, O, env->psw_o >> 31); 168 psw = FIELD_DP32(psw, PSW, S, env->psw_s >> 31); 169 psw = FIELD_DP32(psw, PSW, Z, env->psw_z == 0); 170 psw = FIELD_DP32(psw, PSW, C, env->psw_c); 171 return psw; 172 } 173 174 #endif /* RX_CPU_H */ 175