1 /* 2 * QEMU RX CPU 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/qemu-print.h" 21 #include "qapi/error.h" 22 #include "cpu.h" 23 #include "migration/vmstate.h" 24 #include "exec/exec-all.h" 25 #include "hw/loader.h" 26 #include "fpu/softfloat.h" 27 #include "tcg/debug-assert.h" 28 29 static void rx_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 RXCPU *cpu = RX_CPU(cs); 32 33 cpu->env.pc = value; 34 } 35 36 static vaddr rx_cpu_get_pc(CPUState *cs) 37 { 38 RXCPU *cpu = RX_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void rx_cpu_synchronize_from_tb(CPUState *cs, 44 const TranslationBlock *tb) 45 { 46 RXCPU *cpu = RX_CPU(cs); 47 48 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 49 cpu->env.pc = tb->pc; 50 } 51 52 static void rx_restore_state_to_opc(CPUState *cs, 53 const TranslationBlock *tb, 54 const uint64_t *data) 55 { 56 RXCPU *cpu = RX_CPU(cs); 57 58 cpu->env.pc = data[0]; 59 } 60 61 static bool rx_cpu_has_work(CPUState *cs) 62 { 63 return cs->interrupt_request & 64 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); 65 } 66 67 static void rx_cpu_reset_hold(Object *obj) 68 { 69 RXCPU *cpu = RX_CPU(obj); 70 RXCPUClass *rcc = RX_CPU_GET_CLASS(cpu); 71 CPURXState *env = &cpu->env; 72 uint32_t *resetvec; 73 74 if (rcc->parent_phases.hold) { 75 rcc->parent_phases.hold(obj); 76 } 77 78 memset(env, 0, offsetof(CPURXState, end_reset_fields)); 79 80 resetvec = rom_ptr(0xfffffffc, 4); 81 if (resetvec) { 82 /* In the case of kernel, it is ignored because it is not set. */ 83 env->pc = ldl_p(resetvec); 84 } 85 rx_cpu_unpack_psw(env, 0, 1); 86 env->regs[0] = env->isp = env->usp = 0; 87 env->fpsw = 0; 88 set_flush_to_zero(1, &env->fp_status); 89 set_flush_inputs_to_zero(1, &env->fp_status); 90 } 91 92 static void rx_cpu_list_entry(gpointer data, gpointer user_data) 93 { 94 ObjectClass *oc = data; 95 96 qemu_printf(" %s\n", object_class_get_name(oc)); 97 } 98 99 void rx_cpu_list(void) 100 { 101 GSList *list; 102 list = object_class_get_list_sorted(TYPE_RX_CPU, false); 103 qemu_printf("Available CPUs:\n"); 104 g_slist_foreach(list, rx_cpu_list_entry, NULL); 105 g_slist_free(list); 106 } 107 108 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) 109 { 110 ObjectClass *oc; 111 char *typename; 112 113 oc = object_class_by_name(cpu_model); 114 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) { 115 return oc; 116 } 117 typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); 118 oc = object_class_by_name(typename); 119 g_free(typename); 120 121 return oc; 122 } 123 124 static void rx_cpu_realize(DeviceState *dev, Error **errp) 125 { 126 CPUState *cs = CPU(dev); 127 RXCPUClass *rcc = RX_CPU_GET_CLASS(dev); 128 Error *local_err = NULL; 129 130 cpu_exec_realizefn(cs, &local_err); 131 if (local_err != NULL) { 132 error_propagate(errp, local_err); 133 return; 134 } 135 136 qemu_init_vcpu(cs); 137 cpu_reset(cs); 138 139 rcc->parent_realize(dev, errp); 140 } 141 142 static void rx_cpu_set_irq(void *opaque, int no, int request) 143 { 144 RXCPU *cpu = opaque; 145 CPUState *cs = CPU(cpu); 146 int irq = request & 0xff; 147 148 static const int mask[] = { 149 [RX_CPU_IRQ] = CPU_INTERRUPT_HARD, 150 [RX_CPU_FIR] = CPU_INTERRUPT_FIR, 151 }; 152 if (irq) { 153 cpu->env.req_irq = irq; 154 cpu->env.req_ipl = (request >> 8) & 0x0f; 155 cpu_interrupt(cs, mask[no]); 156 } else { 157 cpu_reset_interrupt(cs, mask[no]); 158 } 159 } 160 161 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) 162 { 163 info->mach = bfd_mach_rx; 164 info->print_insn = print_insn_rx; 165 } 166 167 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, 168 MMUAccessType access_type, int mmu_idx, 169 bool probe, uintptr_t retaddr) 170 { 171 uint32_t address, physical, prot; 172 173 /* Linear mapping */ 174 address = physical = addr & TARGET_PAGE_MASK; 175 prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; 176 tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); 177 return true; 178 } 179 180 static void rx_cpu_init(Object *obj) 181 { 182 RXCPU *cpu = RX_CPU(obj); 183 184 qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); 185 } 186 187 #ifndef CONFIG_USER_ONLY 188 #include "hw/core/sysemu-cpu-ops.h" 189 190 static const struct SysemuCPUOps rx_sysemu_ops = { 191 .get_phys_page_debug = rx_cpu_get_phys_page_debug, 192 }; 193 #endif 194 195 #include "hw/core/tcg-cpu-ops.h" 196 197 static const struct TCGCPUOps rx_tcg_ops = { 198 .initialize = rx_translate_init, 199 .synchronize_from_tb = rx_cpu_synchronize_from_tb, 200 .restore_state_to_opc = rx_restore_state_to_opc, 201 .tlb_fill = rx_cpu_tlb_fill, 202 203 #ifndef CONFIG_USER_ONLY 204 .cpu_exec_interrupt = rx_cpu_exec_interrupt, 205 .do_interrupt = rx_cpu_do_interrupt, 206 #endif /* !CONFIG_USER_ONLY */ 207 }; 208 209 static void rx_cpu_class_init(ObjectClass *klass, void *data) 210 { 211 DeviceClass *dc = DEVICE_CLASS(klass); 212 CPUClass *cc = CPU_CLASS(klass); 213 RXCPUClass *rcc = RX_CPU_CLASS(klass); 214 ResettableClass *rc = RESETTABLE_CLASS(klass); 215 216 device_class_set_parent_realize(dc, rx_cpu_realize, 217 &rcc->parent_realize); 218 resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL, 219 &rcc->parent_phases); 220 221 cc->class_by_name = rx_cpu_class_by_name; 222 cc->has_work = rx_cpu_has_work; 223 cc->dump_state = rx_cpu_dump_state; 224 cc->set_pc = rx_cpu_set_pc; 225 cc->get_pc = rx_cpu_get_pc; 226 227 #ifndef CONFIG_USER_ONLY 228 cc->sysemu_ops = &rx_sysemu_ops; 229 #endif 230 cc->gdb_read_register = rx_cpu_gdb_read_register; 231 cc->gdb_write_register = rx_cpu_gdb_write_register; 232 cc->disas_set_info = rx_cpu_disas_set_info; 233 234 cc->gdb_num_core_regs = 26; 235 cc->gdb_core_xml_file = "rx-core.xml"; 236 cc->tcg_ops = &rx_tcg_ops; 237 } 238 239 static const TypeInfo rx_cpu_info = { 240 .name = TYPE_RX_CPU, 241 .parent = TYPE_CPU, 242 .instance_size = sizeof(RXCPU), 243 .instance_align = __alignof(RXCPU), 244 .instance_init = rx_cpu_init, 245 .abstract = true, 246 .class_size = sizeof(RXCPUClass), 247 .class_init = rx_cpu_class_init, 248 }; 249 250 static const TypeInfo rx62n_rx_cpu_info = { 251 .name = TYPE_RX62N_CPU, 252 .parent = TYPE_RX_CPU, 253 }; 254 255 static void rx_cpu_register_types(void) 256 { 257 type_register_static(&rx_cpu_info); 258 type_register_static(&rx62n_rx_cpu_info); 259 } 260 261 type_init(rx_cpu_register_types) 262