xref: /openbmc/qemu/target/rx/cpu.c (revision 2e1cacfb)
1 /*
2  * QEMU RX CPU
3  *
4  * Copyright (c) 2019 Yoshinori Sato
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "qemu/osdep.h"
20 #include "qemu/qemu-print.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "migration/vmstate.h"
24 #include "exec/exec-all.h"
25 #include "exec/page-protection.h"
26 #include "hw/loader.h"
27 #include "fpu/softfloat.h"
28 #include "tcg/debug-assert.h"
29 
30 static void rx_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32     RXCPU *cpu = RX_CPU(cs);
33 
34     cpu->env.pc = value;
35 }
36 
37 static vaddr rx_cpu_get_pc(CPUState *cs)
38 {
39     RXCPU *cpu = RX_CPU(cs);
40 
41     return cpu->env.pc;
42 }
43 
44 static void rx_cpu_synchronize_from_tb(CPUState *cs,
45                                        const TranslationBlock *tb)
46 {
47     RXCPU *cpu = RX_CPU(cs);
48 
49     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
50     cpu->env.pc = tb->pc;
51 }
52 
53 static void rx_restore_state_to_opc(CPUState *cs,
54                                     const TranslationBlock *tb,
55                                     const uint64_t *data)
56 {
57     RXCPU *cpu = RX_CPU(cs);
58 
59     cpu->env.pc = data[0];
60 }
61 
62 static bool rx_cpu_has_work(CPUState *cs)
63 {
64     return cs->interrupt_request &
65         (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR);
66 }
67 
68 static int riscv_cpu_mmu_index(CPUState *cs, bool ifunc)
69 {
70     return 0;
71 }
72 
73 static void rx_cpu_reset_hold(Object *obj, ResetType type)
74 {
75     CPUState *cs = CPU(obj);
76     RXCPUClass *rcc = RX_CPU_GET_CLASS(obj);
77     CPURXState *env = cpu_env(cs);
78     uint32_t *resetvec;
79 
80     if (rcc->parent_phases.hold) {
81         rcc->parent_phases.hold(obj, type);
82     }
83 
84     memset(env, 0, offsetof(CPURXState, end_reset_fields));
85 
86     resetvec = rom_ptr(0xfffffffc, 4);
87     if (resetvec) {
88         /* In the case of kernel, it is ignored because it is not set. */
89         env->pc = ldl_p(resetvec);
90     }
91     rx_cpu_unpack_psw(env, 0, 1);
92     env->regs[0] = env->isp = env->usp = 0;
93     env->fpsw = 0;
94     set_flush_to_zero(1, &env->fp_status);
95     set_flush_inputs_to_zero(1, &env->fp_status);
96 }
97 
98 static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
99 {
100     ObjectClass *oc;
101     char *typename;
102 
103     oc = object_class_by_name(cpu_model);
104     if (oc != NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) != NULL) {
105         return oc;
106     }
107     typename = g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model);
108     oc = object_class_by_name(typename);
109     g_free(typename);
110 
111     return oc;
112 }
113 
114 static void rx_cpu_realize(DeviceState *dev, Error **errp)
115 {
116     CPUState *cs = CPU(dev);
117     RXCPUClass *rcc = RX_CPU_GET_CLASS(dev);
118     Error *local_err = NULL;
119 
120     cpu_exec_realizefn(cs, &local_err);
121     if (local_err != NULL) {
122         error_propagate(errp, local_err);
123         return;
124     }
125 
126     qemu_init_vcpu(cs);
127     cpu_reset(cs);
128 
129     rcc->parent_realize(dev, errp);
130 }
131 
132 static void rx_cpu_set_irq(void *opaque, int no, int request)
133 {
134     RXCPU *cpu = opaque;
135     CPUState *cs = CPU(cpu);
136     int irq = request & 0xff;
137 
138     static const int mask[] = {
139         [RX_CPU_IRQ] = CPU_INTERRUPT_HARD,
140         [RX_CPU_FIR] = CPU_INTERRUPT_FIR,
141     };
142     if (irq) {
143         cpu->env.req_irq = irq;
144         cpu->env.req_ipl = (request >> 8) & 0x0f;
145         cpu_interrupt(cs, mask[no]);
146     } else {
147         cpu_reset_interrupt(cs, mask[no]);
148     }
149 }
150 
151 static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
152 {
153     info->mach = bfd_mach_rx;
154     info->print_insn = print_insn_rx;
155 }
156 
157 static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size,
158                             MMUAccessType access_type, int mmu_idx,
159                             bool probe, uintptr_t retaddr)
160 {
161     uint32_t address, physical, prot;
162 
163     /* Linear mapping */
164     address = physical = addr & TARGET_PAGE_MASK;
165     prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
166     tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
167     return true;
168 }
169 
170 static void rx_cpu_init(Object *obj)
171 {
172     RXCPU *cpu = RX_CPU(obj);
173 
174     qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2);
175 }
176 
177 #ifndef CONFIG_USER_ONLY
178 #include "hw/core/sysemu-cpu-ops.h"
179 
180 static const struct SysemuCPUOps rx_sysemu_ops = {
181     .get_phys_page_debug = rx_cpu_get_phys_page_debug,
182 };
183 #endif
184 
185 #include "hw/core/tcg-cpu-ops.h"
186 
187 static const TCGCPUOps rx_tcg_ops = {
188     .initialize = rx_translate_init,
189     .synchronize_from_tb = rx_cpu_synchronize_from_tb,
190     .restore_state_to_opc = rx_restore_state_to_opc,
191     .tlb_fill = rx_cpu_tlb_fill,
192 
193 #ifndef CONFIG_USER_ONLY
194     .cpu_exec_interrupt = rx_cpu_exec_interrupt,
195     .cpu_exec_halt = rx_cpu_has_work,
196     .do_interrupt = rx_cpu_do_interrupt,
197 #endif /* !CONFIG_USER_ONLY */
198 };
199 
200 static void rx_cpu_class_init(ObjectClass *klass, void *data)
201 {
202     DeviceClass *dc = DEVICE_CLASS(klass);
203     CPUClass *cc = CPU_CLASS(klass);
204     RXCPUClass *rcc = RX_CPU_CLASS(klass);
205     ResettableClass *rc = RESETTABLE_CLASS(klass);
206 
207     device_class_set_parent_realize(dc, rx_cpu_realize,
208                                     &rcc->parent_realize);
209     resettable_class_set_parent_phases(rc, NULL, rx_cpu_reset_hold, NULL,
210                                        &rcc->parent_phases);
211 
212     cc->class_by_name = rx_cpu_class_by_name;
213     cc->has_work = rx_cpu_has_work;
214     cc->mmu_index = riscv_cpu_mmu_index;
215     cc->dump_state = rx_cpu_dump_state;
216     cc->set_pc = rx_cpu_set_pc;
217     cc->get_pc = rx_cpu_get_pc;
218 
219 #ifndef CONFIG_USER_ONLY
220     cc->sysemu_ops = &rx_sysemu_ops;
221 #endif
222     cc->gdb_read_register = rx_cpu_gdb_read_register;
223     cc->gdb_write_register = rx_cpu_gdb_write_register;
224     cc->disas_set_info = rx_cpu_disas_set_info;
225 
226     cc->gdb_core_xml_file = "rx-core.xml";
227     cc->tcg_ops = &rx_tcg_ops;
228 }
229 
230 static const TypeInfo rx_cpu_info = {
231     .name = TYPE_RX_CPU,
232     .parent = TYPE_CPU,
233     .instance_size = sizeof(RXCPU),
234     .instance_align = __alignof(RXCPU),
235     .instance_init = rx_cpu_init,
236     .abstract = true,
237     .class_size = sizeof(RXCPUClass),
238     .class_init = rx_cpu_class_init,
239 };
240 
241 static const TypeInfo rx62n_rx_cpu_info = {
242     .name = TYPE_RX62N_CPU,
243     .parent = TYPE_RX_CPU,
244 };
245 
246 static void rx_cpu_register_types(void)
247 {
248     type_register_static(&rx_cpu_info);
249     type_register_static(&rx62n_rx_cpu_info);
250 }
251 
252 type_init(rx_cpu_register_types)
253