xref: /openbmc/qemu/target/riscv/xthead.decode (revision 49a7f3aa)
1#
2# Translation routines for the instructions of the XThead* ISA extensions
3#
4# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
5#
6# SPDX-License-Identifier: LGPL-2.1-or-later
7#
8# The documentation of the ISA extensions can be found here:
9#   https://github.com/T-head-Semi/thead-extension-spec/releases/latest
10
11# Fields:
12%rs1       15:5
13
14# Formats
15@sfence_vm  ....... ..... .....   ... ..... ....... %rs1
16
17# XTheadCmo
18th_dcache_call   0000000 00001 00000 000 00000 0001011
19th_dcache_ciall  0000000 00011 00000 000 00000 0001011
20th_dcache_iall   0000000 00010 00000 000 00000 0001011
21th_dcache_cpa    0000001 01001 ..... 000 00000 0001011 @sfence_vm
22th_dcache_cipa   0000001 01011 ..... 000 00000 0001011 @sfence_vm
23th_dcache_ipa    0000001 01010 ..... 000 00000 0001011 @sfence_vm
24th_dcache_cva    0000001 00101 ..... 000 00000 0001011 @sfence_vm
25th_dcache_civa   0000001 00111 ..... 000 00000 0001011 @sfence_vm
26th_dcache_iva    0000001 00110 ..... 000 00000 0001011 @sfence_vm
27th_dcache_csw    0000001 00001 ..... 000 00000 0001011 @sfence_vm
28th_dcache_cisw   0000001 00011 ..... 000 00000 0001011 @sfence_vm
29th_dcache_isw    0000001 00010 ..... 000 00000 0001011 @sfence_vm
30th_dcache_cpal1  0000001 01000 ..... 000 00000 0001011 @sfence_vm
31th_dcache_cval1  0000001 00100 ..... 000 00000 0001011 @sfence_vm
32th_icache_iall   0000000 10000 00000 000 00000 0001011
33th_icache_ialls  0000000 10001 00000 000 00000 0001011
34th_icache_ipa    0000001 11000 ..... 000 00000 0001011 @sfence_vm
35th_icache_iva    0000001 10000 ..... 000 00000 0001011 @sfence_vm
36th_l2cache_call  0000000 10101 00000 000 00000 0001011
37th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
38th_l2cache_iall  0000000 10110 00000 000 00000 0001011
39