1# 2# Translation routines for the instructions of the XThead* ISA extensions 3# 4# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu 5# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu 6# 7# SPDX-License-Identifier: LGPL-2.1-or-later 8# 9# The documentation of the ISA extensions can be found here: 10# https://github.com/T-head-Semi/thead-extension-spec/releases/latest 11 12# Fields: 13%rd 7:5 14%rs1 15:5 15%rs2 20:5 16%sh5 20:5 17%sh6 20:6 18 19# Argument sets 20&r rd rs1 rs2 !extern 21&r2 rd rs1 !extern 22&shift shamt rs1 rd !extern 23&th_bfext msb lsb rs1 rd 24 25# Formats 26@sfence_vm ....... ..... ..... ... ..... ....... %rs1 27@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 28@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd 29@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd 30@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd 31@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd 32@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd 33 34# XTheadBa 35# Instead of defining a new encoding, we simply use the decoder to 36# extract the imm[0:1] field and dispatch to separate translation 37# functions (mirroring the `sh[123]add` instructions from Zba and 38# the regular RVI `add` instruction. 39# 40# The only difference between sh[123]add and addsl is that the shift 41# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). 42# 43# Note that shift-by-0 is a valid operation according to the manual. 44# This will be equivalent to a regular add. 45add 0000000 ..... ..... 001 ..... 0001011 @r 46th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r 47th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r 48th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r 49 50# XTheadBb 51th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext 52th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext 53th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 54th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 55th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 56th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 57th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 58th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 59th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 60 61# XTheadBs 62th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 63 64# XTheadCmo 65th_dcache_call 0000000 00001 00000 000 00000 0001011 66th_dcache_ciall 0000000 00011 00000 000 00000 0001011 67th_dcache_iall 0000000 00010 00000 000 00000 0001011 68th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm 69th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm 70th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm 71th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm 72th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm 73th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm 74th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm 75th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm 76th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm 77th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm 78th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm 79th_icache_iall 0000000 10000 00000 000 00000 0001011 80th_icache_ialls 0000000 10001 00000 000 00000 0001011 81th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm 82th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm 83th_l2cache_call 0000000 10101 00000 000 00000 0001011 84th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 85th_l2cache_iall 0000000 10110 00000 000 00000 0001011 86 87# XTheadCondMov 88th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r 89th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r 90 91# XTheadSync 92th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s 93th_sync 0000000 11000 00000 000 00000 0001011 94th_sync_i 0000000 11010 00000 000 00000 0001011 95th_sync_is 0000000 11011 00000 000 00000 0001011 96th_sync_s 0000000 11001 00000 000 00000 0001011 97