1 /* 2 * RISC-V Vector Extension Helpers for QEMU. 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/memop.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "tcg/tcg-gvec-desc.h" 25 #include "internals.h" 26 #include <math.h> 27 28 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, 29 target_ulong s2) 30 { 31 int vlmax, vl; 32 RISCVCPU *cpu = env_archcpu(env); 33 uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW); 34 uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); 35 bool vill = FIELD_EX64(s2, VTYPE, VILL); 36 target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); 37 38 if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) { 39 /* only set vill bit. */ 40 env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); 41 env->vl = 0; 42 env->vstart = 0; 43 return 0; 44 } 45 46 vlmax = vext_get_vlmax(cpu, s2); 47 if (s1 <= vlmax) { 48 vl = s1; 49 } else { 50 vl = vlmax; 51 } 52 env->vl = vl; 53 env->vtype = s2; 54 env->vstart = 0; 55 return vl; 56 } 57 58 /* 59 * Note that vector data is stored in host-endian 64-bit chunks, 60 * so addressing units smaller than that needs a host-endian fixup. 61 */ 62 #ifdef HOST_WORDS_BIGENDIAN 63 #define H1(x) ((x) ^ 7) 64 #define H1_2(x) ((x) ^ 6) 65 #define H1_4(x) ((x) ^ 4) 66 #define H2(x) ((x) ^ 3) 67 #define H4(x) ((x) ^ 1) 68 #define H8(x) ((x)) 69 #else 70 #define H1(x) (x) 71 #define H1_2(x) (x) 72 #define H1_4(x) (x) 73 #define H2(x) (x) 74 #define H4(x) (x) 75 #define H8(x) (x) 76 #endif 77 78 static inline uint32_t vext_nf(uint32_t desc) 79 { 80 return FIELD_EX32(simd_data(desc), VDATA, NF); 81 } 82 83 static inline uint32_t vext_mlen(uint32_t desc) 84 { 85 return FIELD_EX32(simd_data(desc), VDATA, MLEN); 86 } 87 88 static inline uint32_t vext_vm(uint32_t desc) 89 { 90 return FIELD_EX32(simd_data(desc), VDATA, VM); 91 } 92 93 static inline uint32_t vext_lmul(uint32_t desc) 94 { 95 return FIELD_EX32(simd_data(desc), VDATA, LMUL); 96 } 97 98 static uint32_t vext_wd(uint32_t desc) 99 { 100 return (simd_data(desc) >> 11) & 0x1; 101 } 102 103 /* 104 * Get vector group length in bytes. Its range is [64, 2048]. 105 * 106 * As simd_desc support at most 256, the max vlen is 512 bits. 107 * So vlen in bytes is encoded as maxsz. 108 */ 109 static inline uint32_t vext_maxsz(uint32_t desc) 110 { 111 return simd_maxsz(desc) << vext_lmul(desc); 112 } 113 114 /* 115 * This function checks watchpoint before real load operation. 116 * 117 * In softmmu mode, the TLB API probe_access is enough for watchpoint check. 118 * In user mode, there is no watchpoint support now. 119 * 120 * It will trigger an exception if there is no mapping in TLB 121 * and page table walk can't fill the TLB entry. Then the guest 122 * software can return here after process the exception or never return. 123 */ 124 static void probe_pages(CPURISCVState *env, target_ulong addr, 125 target_ulong len, uintptr_t ra, 126 MMUAccessType access_type) 127 { 128 target_ulong pagelen = -(addr | TARGET_PAGE_MASK); 129 target_ulong curlen = MIN(pagelen, len); 130 131 probe_access(env, addr, curlen, access_type, 132 cpu_mmu_index(env, false), ra); 133 if (len > curlen) { 134 addr += curlen; 135 curlen = len - curlen; 136 probe_access(env, addr, curlen, access_type, 137 cpu_mmu_index(env, false), ra); 138 } 139 } 140 141 #ifdef HOST_WORDS_BIGENDIAN 142 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) 143 { 144 /* 145 * Split the remaining range to two parts. 146 * The first part is in the last uint64_t unit. 147 * The second part start from the next uint64_t unit. 148 */ 149 int part1 = 0, part2 = tot - cnt; 150 if (cnt % 8) { 151 part1 = 8 - (cnt % 8); 152 part2 = tot - cnt - part1; 153 memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); 154 memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); 155 } else { 156 memset(tail, 0, part2); 157 } 158 } 159 #else 160 static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) 161 { 162 memset(tail, 0, tot - cnt); 163 } 164 #endif 165 166 static void clearb(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) 167 { 168 int8_t *cur = ((int8_t *)vd + H1(idx)); 169 vext_clear(cur, cnt, tot); 170 } 171 172 static void clearh(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) 173 { 174 int16_t *cur = ((int16_t *)vd + H2(idx)); 175 vext_clear(cur, cnt, tot); 176 } 177 178 static void clearl(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) 179 { 180 int32_t *cur = ((int32_t *)vd + H4(idx)); 181 vext_clear(cur, cnt, tot); 182 } 183 184 static void clearq(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot) 185 { 186 int64_t *cur = (int64_t *)vd + idx; 187 vext_clear(cur, cnt, tot); 188 } 189 190 static inline void vext_set_elem_mask(void *v0, int mlen, int index, 191 uint8_t value) 192 { 193 int idx = (index * mlen) / 64; 194 int pos = (index * mlen) % 64; 195 uint64_t old = ((uint64_t *)v0)[idx]; 196 ((uint64_t *)v0)[idx] = deposit64(old, pos, mlen, value); 197 } 198 199 static inline int vext_elem_mask(void *v0, int mlen, int index) 200 { 201 int idx = (index * mlen) / 64; 202 int pos = (index * mlen) % 64; 203 return (((uint64_t *)v0)[idx] >> pos) & 1; 204 } 205 206 /* elements operations for load and store */ 207 typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, 208 uint32_t idx, void *vd, uintptr_t retaddr); 209 typedef void clear_fn(void *vd, uint32_t idx, uint32_t cnt, uint32_t tot); 210 211 #define GEN_VEXT_LD_ELEM(NAME, MTYPE, ETYPE, H, LDSUF) \ 212 static void NAME(CPURISCVState *env, abi_ptr addr, \ 213 uint32_t idx, void *vd, uintptr_t retaddr)\ 214 { \ 215 MTYPE data; \ 216 ETYPE *cur = ((ETYPE *)vd + H(idx)); \ 217 data = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ 218 *cur = data; \ 219 } \ 220 221 GEN_VEXT_LD_ELEM(ldb_b, int8_t, int8_t, H1, ldsb) 222 GEN_VEXT_LD_ELEM(ldb_h, int8_t, int16_t, H2, ldsb) 223 GEN_VEXT_LD_ELEM(ldb_w, int8_t, int32_t, H4, ldsb) 224 GEN_VEXT_LD_ELEM(ldb_d, int8_t, int64_t, H8, ldsb) 225 GEN_VEXT_LD_ELEM(ldh_h, int16_t, int16_t, H2, ldsw) 226 GEN_VEXT_LD_ELEM(ldh_w, int16_t, int32_t, H4, ldsw) 227 GEN_VEXT_LD_ELEM(ldh_d, int16_t, int64_t, H8, ldsw) 228 GEN_VEXT_LD_ELEM(ldw_w, int32_t, int32_t, H4, ldl) 229 GEN_VEXT_LD_ELEM(ldw_d, int32_t, int64_t, H8, ldl) 230 GEN_VEXT_LD_ELEM(lde_b, int8_t, int8_t, H1, ldsb) 231 GEN_VEXT_LD_ELEM(lde_h, int16_t, int16_t, H2, ldsw) 232 GEN_VEXT_LD_ELEM(lde_w, int32_t, int32_t, H4, ldl) 233 GEN_VEXT_LD_ELEM(lde_d, int64_t, int64_t, H8, ldq) 234 GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, uint8_t, H1, ldub) 235 GEN_VEXT_LD_ELEM(ldbu_h, uint8_t, uint16_t, H2, ldub) 236 GEN_VEXT_LD_ELEM(ldbu_w, uint8_t, uint32_t, H4, ldub) 237 GEN_VEXT_LD_ELEM(ldbu_d, uint8_t, uint64_t, H8, ldub) 238 GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, uint16_t, H2, lduw) 239 GEN_VEXT_LD_ELEM(ldhu_w, uint16_t, uint32_t, H4, lduw) 240 GEN_VEXT_LD_ELEM(ldhu_d, uint16_t, uint64_t, H8, lduw) 241 GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, uint32_t, H4, ldl) 242 GEN_VEXT_LD_ELEM(ldwu_d, uint32_t, uint64_t, H8, ldl) 243 244 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ 245 static void NAME(CPURISCVState *env, abi_ptr addr, \ 246 uint32_t idx, void *vd, uintptr_t retaddr)\ 247 { \ 248 ETYPE data = *((ETYPE *)vd + H(idx)); \ 249 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ 250 } 251 252 GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb) 253 GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb) 254 GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb) 255 GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb) 256 GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw) 257 GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw) 258 GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw) 259 GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl) 260 GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl) 261 GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) 262 GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) 263 GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) 264 GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq) 265 266 /* 267 *** stride: access vector element from strided memory 268 */ 269 static void 270 vext_ldst_stride(void *vd, void *v0, target_ulong base, 271 target_ulong stride, CPURISCVState *env, 272 uint32_t desc, uint32_t vm, 273 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, 274 uint32_t esz, uint32_t msz, uintptr_t ra, 275 MMUAccessType access_type) 276 { 277 uint32_t i, k; 278 uint32_t nf = vext_nf(desc); 279 uint32_t mlen = vext_mlen(desc); 280 uint32_t vlmax = vext_maxsz(desc) / esz; 281 282 /* probe every access*/ 283 for (i = 0; i < env->vl; i++) { 284 if (!vm && !vext_elem_mask(v0, mlen, i)) { 285 continue; 286 } 287 probe_pages(env, base + stride * i, nf * msz, ra, access_type); 288 } 289 /* do real access */ 290 for (i = 0; i < env->vl; i++) { 291 k = 0; 292 if (!vm && !vext_elem_mask(v0, mlen, i)) { 293 continue; 294 } 295 while (k < nf) { 296 target_ulong addr = base + stride * i + k * msz; 297 ldst_elem(env, addr, i + k * vlmax, vd, ra); 298 k++; 299 } 300 } 301 /* clear tail elements */ 302 if (clear_elem) { 303 for (k = 0; k < nf; k++) { 304 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); 305 } 306 } 307 } 308 309 #define GEN_VEXT_LD_STRIDE(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ 310 void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ 311 target_ulong stride, CPURISCVState *env, \ 312 uint32_t desc) \ 313 { \ 314 uint32_t vm = vext_vm(desc); \ 315 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ 316 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ 317 GETPC(), MMU_DATA_LOAD); \ 318 } 319 320 GEN_VEXT_LD_STRIDE(vlsb_v_b, int8_t, int8_t, ldb_b, clearb) 321 GEN_VEXT_LD_STRIDE(vlsb_v_h, int8_t, int16_t, ldb_h, clearh) 322 GEN_VEXT_LD_STRIDE(vlsb_v_w, int8_t, int32_t, ldb_w, clearl) 323 GEN_VEXT_LD_STRIDE(vlsb_v_d, int8_t, int64_t, ldb_d, clearq) 324 GEN_VEXT_LD_STRIDE(vlsh_v_h, int16_t, int16_t, ldh_h, clearh) 325 GEN_VEXT_LD_STRIDE(vlsh_v_w, int16_t, int32_t, ldh_w, clearl) 326 GEN_VEXT_LD_STRIDE(vlsh_v_d, int16_t, int64_t, ldh_d, clearq) 327 GEN_VEXT_LD_STRIDE(vlsw_v_w, int32_t, int32_t, ldw_w, clearl) 328 GEN_VEXT_LD_STRIDE(vlsw_v_d, int32_t, int64_t, ldw_d, clearq) 329 GEN_VEXT_LD_STRIDE(vlse_v_b, int8_t, int8_t, lde_b, clearb) 330 GEN_VEXT_LD_STRIDE(vlse_v_h, int16_t, int16_t, lde_h, clearh) 331 GEN_VEXT_LD_STRIDE(vlse_v_w, int32_t, int32_t, lde_w, clearl) 332 GEN_VEXT_LD_STRIDE(vlse_v_d, int64_t, int64_t, lde_d, clearq) 333 GEN_VEXT_LD_STRIDE(vlsbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) 334 GEN_VEXT_LD_STRIDE(vlsbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) 335 GEN_VEXT_LD_STRIDE(vlsbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) 336 GEN_VEXT_LD_STRIDE(vlsbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) 337 GEN_VEXT_LD_STRIDE(vlshu_v_h, uint16_t, uint16_t, ldhu_h, clearh) 338 GEN_VEXT_LD_STRIDE(vlshu_v_w, uint16_t, uint32_t, ldhu_w, clearl) 339 GEN_VEXT_LD_STRIDE(vlshu_v_d, uint16_t, uint64_t, ldhu_d, clearq) 340 GEN_VEXT_LD_STRIDE(vlswu_v_w, uint32_t, uint32_t, ldwu_w, clearl) 341 GEN_VEXT_LD_STRIDE(vlswu_v_d, uint32_t, uint64_t, ldwu_d, clearq) 342 343 #define GEN_VEXT_ST_STRIDE(NAME, MTYPE, ETYPE, STORE_FN) \ 344 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 345 target_ulong stride, CPURISCVState *env, \ 346 uint32_t desc) \ 347 { \ 348 uint32_t vm = vext_vm(desc); \ 349 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ 350 NULL, sizeof(ETYPE), sizeof(MTYPE), \ 351 GETPC(), MMU_DATA_STORE); \ 352 } 353 354 GEN_VEXT_ST_STRIDE(vssb_v_b, int8_t, int8_t, stb_b) 355 GEN_VEXT_ST_STRIDE(vssb_v_h, int8_t, int16_t, stb_h) 356 GEN_VEXT_ST_STRIDE(vssb_v_w, int8_t, int32_t, stb_w) 357 GEN_VEXT_ST_STRIDE(vssb_v_d, int8_t, int64_t, stb_d) 358 GEN_VEXT_ST_STRIDE(vssh_v_h, int16_t, int16_t, sth_h) 359 GEN_VEXT_ST_STRIDE(vssh_v_w, int16_t, int32_t, sth_w) 360 GEN_VEXT_ST_STRIDE(vssh_v_d, int16_t, int64_t, sth_d) 361 GEN_VEXT_ST_STRIDE(vssw_v_w, int32_t, int32_t, stw_w) 362 GEN_VEXT_ST_STRIDE(vssw_v_d, int32_t, int64_t, stw_d) 363 GEN_VEXT_ST_STRIDE(vsse_v_b, int8_t, int8_t, ste_b) 364 GEN_VEXT_ST_STRIDE(vsse_v_h, int16_t, int16_t, ste_h) 365 GEN_VEXT_ST_STRIDE(vsse_v_w, int32_t, int32_t, ste_w) 366 GEN_VEXT_ST_STRIDE(vsse_v_d, int64_t, int64_t, ste_d) 367 368 /* 369 *** unit-stride: access elements stored contiguously in memory 370 */ 371 372 /* unmasked unit-stride load and store operation*/ 373 static void 374 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, 375 vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem, 376 uint32_t esz, uint32_t msz, uintptr_t ra, 377 MMUAccessType access_type) 378 { 379 uint32_t i, k; 380 uint32_t nf = vext_nf(desc); 381 uint32_t vlmax = vext_maxsz(desc) / esz; 382 383 /* probe every access */ 384 probe_pages(env, base, env->vl * nf * msz, ra, access_type); 385 /* load bytes from guest memory */ 386 for (i = 0; i < env->vl; i++) { 387 k = 0; 388 while (k < nf) { 389 target_ulong addr = base + (i * nf + k) * msz; 390 ldst_elem(env, addr, i + k * vlmax, vd, ra); 391 k++; 392 } 393 } 394 /* clear tail elements */ 395 if (clear_elem) { 396 for (k = 0; k < nf; k++) { 397 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); 398 } 399 } 400 } 401 402 /* 403 * masked unit-stride load and store operation will be a special case of stride, 404 * stride = NF * sizeof (MTYPE) 405 */ 406 407 #define GEN_VEXT_LD_US(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ 408 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ 409 CPURISCVState *env, uint32_t desc) \ 410 { \ 411 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ 412 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ 413 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ 414 GETPC(), MMU_DATA_LOAD); \ 415 } \ 416 \ 417 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 418 CPURISCVState *env, uint32_t desc) \ 419 { \ 420 vext_ldst_us(vd, base, env, desc, LOAD_FN, CLEAR_FN, \ 421 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_LOAD); \ 422 } 423 424 GEN_VEXT_LD_US(vlb_v_b, int8_t, int8_t, ldb_b, clearb) 425 GEN_VEXT_LD_US(vlb_v_h, int8_t, int16_t, ldb_h, clearh) 426 GEN_VEXT_LD_US(vlb_v_w, int8_t, int32_t, ldb_w, clearl) 427 GEN_VEXT_LD_US(vlb_v_d, int8_t, int64_t, ldb_d, clearq) 428 GEN_VEXT_LD_US(vlh_v_h, int16_t, int16_t, ldh_h, clearh) 429 GEN_VEXT_LD_US(vlh_v_w, int16_t, int32_t, ldh_w, clearl) 430 GEN_VEXT_LD_US(vlh_v_d, int16_t, int64_t, ldh_d, clearq) 431 GEN_VEXT_LD_US(vlw_v_w, int32_t, int32_t, ldw_w, clearl) 432 GEN_VEXT_LD_US(vlw_v_d, int32_t, int64_t, ldw_d, clearq) 433 GEN_VEXT_LD_US(vle_v_b, int8_t, int8_t, lde_b, clearb) 434 GEN_VEXT_LD_US(vle_v_h, int16_t, int16_t, lde_h, clearh) 435 GEN_VEXT_LD_US(vle_v_w, int32_t, int32_t, lde_w, clearl) 436 GEN_VEXT_LD_US(vle_v_d, int64_t, int64_t, lde_d, clearq) 437 GEN_VEXT_LD_US(vlbu_v_b, uint8_t, uint8_t, ldbu_b, clearb) 438 GEN_VEXT_LD_US(vlbu_v_h, uint8_t, uint16_t, ldbu_h, clearh) 439 GEN_VEXT_LD_US(vlbu_v_w, uint8_t, uint32_t, ldbu_w, clearl) 440 GEN_VEXT_LD_US(vlbu_v_d, uint8_t, uint64_t, ldbu_d, clearq) 441 GEN_VEXT_LD_US(vlhu_v_h, uint16_t, uint16_t, ldhu_h, clearh) 442 GEN_VEXT_LD_US(vlhu_v_w, uint16_t, uint32_t, ldhu_w, clearl) 443 GEN_VEXT_LD_US(vlhu_v_d, uint16_t, uint64_t, ldhu_d, clearq) 444 GEN_VEXT_LD_US(vlwu_v_w, uint32_t, uint32_t, ldwu_w, clearl) 445 GEN_VEXT_LD_US(vlwu_v_d, uint32_t, uint64_t, ldwu_d, clearq) 446 447 #define GEN_VEXT_ST_US(NAME, MTYPE, ETYPE, STORE_FN) \ 448 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ 449 CPURISCVState *env, uint32_t desc) \ 450 { \ 451 uint32_t stride = vext_nf(desc) * sizeof(MTYPE); \ 452 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ 453 NULL, sizeof(ETYPE), sizeof(MTYPE), \ 454 GETPC(), MMU_DATA_STORE); \ 455 } \ 456 \ 457 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 458 CPURISCVState *env, uint32_t desc) \ 459 { \ 460 vext_ldst_us(vd, base, env, desc, STORE_FN, NULL, \ 461 sizeof(ETYPE), sizeof(MTYPE), GETPC(), MMU_DATA_STORE);\ 462 } 463 464 GEN_VEXT_ST_US(vsb_v_b, int8_t, int8_t , stb_b) 465 GEN_VEXT_ST_US(vsb_v_h, int8_t, int16_t, stb_h) 466 GEN_VEXT_ST_US(vsb_v_w, int8_t, int32_t, stb_w) 467 GEN_VEXT_ST_US(vsb_v_d, int8_t, int64_t, stb_d) 468 GEN_VEXT_ST_US(vsh_v_h, int16_t, int16_t, sth_h) 469 GEN_VEXT_ST_US(vsh_v_w, int16_t, int32_t, sth_w) 470 GEN_VEXT_ST_US(vsh_v_d, int16_t, int64_t, sth_d) 471 GEN_VEXT_ST_US(vsw_v_w, int32_t, int32_t, stw_w) 472 GEN_VEXT_ST_US(vsw_v_d, int32_t, int64_t, stw_d) 473 GEN_VEXT_ST_US(vse_v_b, int8_t, int8_t , ste_b) 474 GEN_VEXT_ST_US(vse_v_h, int16_t, int16_t, ste_h) 475 GEN_VEXT_ST_US(vse_v_w, int32_t, int32_t, ste_w) 476 GEN_VEXT_ST_US(vse_v_d, int64_t, int64_t, ste_d) 477 478 /* 479 *** index: access vector element from indexed memory 480 */ 481 typedef target_ulong vext_get_index_addr(target_ulong base, 482 uint32_t idx, void *vs2); 483 484 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \ 485 static target_ulong NAME(target_ulong base, \ 486 uint32_t idx, void *vs2) \ 487 { \ 488 return (base + *((ETYPE *)vs2 + H(idx))); \ 489 } 490 491 GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) 492 GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2) 493 GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4) 494 GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8) 495 496 static inline void 497 vext_ldst_index(void *vd, void *v0, target_ulong base, 498 void *vs2, CPURISCVState *env, uint32_t desc, 499 vext_get_index_addr get_index_addr, 500 vext_ldst_elem_fn *ldst_elem, 501 clear_fn *clear_elem, 502 uint32_t esz, uint32_t msz, uintptr_t ra, 503 MMUAccessType access_type) 504 { 505 uint32_t i, k; 506 uint32_t nf = vext_nf(desc); 507 uint32_t vm = vext_vm(desc); 508 uint32_t mlen = vext_mlen(desc); 509 uint32_t vlmax = vext_maxsz(desc) / esz; 510 511 /* probe every access*/ 512 for (i = 0; i < env->vl; i++) { 513 if (!vm && !vext_elem_mask(v0, mlen, i)) { 514 continue; 515 } 516 probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, 517 access_type); 518 } 519 /* load bytes from guest memory */ 520 for (i = 0; i < env->vl; i++) { 521 k = 0; 522 if (!vm && !vext_elem_mask(v0, mlen, i)) { 523 continue; 524 } 525 while (k < nf) { 526 abi_ptr addr = get_index_addr(base, i, vs2) + k * msz; 527 ldst_elem(env, addr, i + k * vlmax, vd, ra); 528 k++; 529 } 530 } 531 /* clear tail elements */ 532 if (clear_elem) { 533 for (k = 0; k < nf; k++) { 534 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); 535 } 536 } 537 } 538 539 #define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN, CLEAR_FN) \ 540 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 541 void *vs2, CPURISCVState *env, uint32_t desc) \ 542 { \ 543 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ 544 LOAD_FN, CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ 545 GETPC(), MMU_DATA_LOAD); \ 546 } 547 548 GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b, clearb) 549 GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h, clearh) 550 GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w, clearl) 551 GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d, clearq) 552 GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h, clearh) 553 GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w, clearl) 554 GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d, clearq) 555 GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w, clearl) 556 GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d, clearq) 557 GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b, clearb) 558 GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h, clearh) 559 GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w, clearl) 560 GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d, clearq) 561 GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b, clearb) 562 GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h, clearh) 563 GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w, clearl) 564 GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d, clearq) 565 GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h, clearh) 566 GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w, clearl) 567 GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d, clearq) 568 GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w, clearl) 569 GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d, clearq) 570 571 #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ 572 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 573 void *vs2, CPURISCVState *env, uint32_t desc) \ 574 { \ 575 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ 576 STORE_FN, NULL, sizeof(ETYPE), sizeof(MTYPE),\ 577 GETPC(), MMU_DATA_STORE); \ 578 } 579 580 GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b) 581 GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h) 582 GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w) 583 GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d) 584 GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h) 585 GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w) 586 GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d) 587 GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w) 588 GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d) 589 GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b) 590 GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h) 591 GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w) 592 GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d) 593 594 /* 595 *** unit-stride fault-only-fisrt load instructions 596 */ 597 static inline void 598 vext_ldff(void *vd, void *v0, target_ulong base, 599 CPURISCVState *env, uint32_t desc, 600 vext_ldst_elem_fn *ldst_elem, 601 clear_fn *clear_elem, 602 uint32_t esz, uint32_t msz, uintptr_t ra) 603 { 604 void *host; 605 uint32_t i, k, vl = 0; 606 uint32_t mlen = vext_mlen(desc); 607 uint32_t nf = vext_nf(desc); 608 uint32_t vm = vext_vm(desc); 609 uint32_t vlmax = vext_maxsz(desc) / esz; 610 target_ulong addr, offset, remain; 611 612 /* probe every access*/ 613 for (i = 0; i < env->vl; i++) { 614 if (!vm && !vext_elem_mask(v0, mlen, i)) { 615 continue; 616 } 617 addr = base + nf * i * msz; 618 if (i == 0) { 619 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); 620 } else { 621 /* if it triggers an exception, no need to check watchpoint */ 622 remain = nf * msz; 623 while (remain > 0) { 624 offset = -(addr | TARGET_PAGE_MASK); 625 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, 626 cpu_mmu_index(env, false)); 627 if (host) { 628 #ifdef CONFIG_USER_ONLY 629 if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { 630 vl = i; 631 goto ProbeSuccess; 632 } 633 #else 634 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); 635 #endif 636 } else { 637 vl = i; 638 goto ProbeSuccess; 639 } 640 if (remain <= offset) { 641 break; 642 } 643 remain -= offset; 644 addr += offset; 645 } 646 } 647 } 648 ProbeSuccess: 649 /* load bytes from guest memory */ 650 if (vl != 0) { 651 env->vl = vl; 652 } 653 for (i = 0; i < env->vl; i++) { 654 k = 0; 655 if (!vm && !vext_elem_mask(v0, mlen, i)) { 656 continue; 657 } 658 while (k < nf) { 659 target_ulong addr = base + (i * nf + k) * msz; 660 ldst_elem(env, addr, i + k * vlmax, vd, ra); 661 k++; 662 } 663 } 664 /* clear tail elements */ 665 if (vl != 0) { 666 return; 667 } 668 for (k = 0; k < nf; k++) { 669 clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); 670 } 671 } 672 673 #define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN, CLEAR_FN) \ 674 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 675 CPURISCVState *env, uint32_t desc) \ 676 { \ 677 vext_ldff(vd, v0, base, env, desc, LOAD_FN, CLEAR_FN, \ 678 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ 679 } 680 681 GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b, clearb) 682 GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h, clearh) 683 GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w, clearl) 684 GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d, clearq) 685 GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h, clearh) 686 GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w, clearl) 687 GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d, clearq) 688 GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w, clearl) 689 GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d, clearq) 690 GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b, clearb) 691 GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h, clearh) 692 GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w, clearl) 693 GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d, clearq) 694 GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b, clearb) 695 GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h, clearh) 696 GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w, clearl) 697 GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d, clearq) 698 GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h, clearh) 699 GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w, clearl) 700 GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d, clearq) 701 GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w, clearl) 702 GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d, clearq) 703 704 /* 705 *** Vector AMO Operations (Zvamo) 706 */ 707 typedef void vext_amo_noatomic_fn(void *vs3, target_ulong addr, 708 uint32_t wd, uint32_t idx, CPURISCVState *env, 709 uintptr_t retaddr); 710 711 /* no atomic opreation for vector atomic insructions */ 712 #define DO_SWAP(N, M) (M) 713 #define DO_AND(N, M) (N & M) 714 #define DO_XOR(N, M) (N ^ M) 715 #define DO_OR(N, M) (N | M) 716 #define DO_ADD(N, M) (N + M) 717 718 #define GEN_VEXT_AMO_NOATOMIC_OP(NAME, ESZ, MSZ, H, DO_OP, SUF) \ 719 static void \ 720 vext_##NAME##_noatomic_op(void *vs3, target_ulong addr, \ 721 uint32_t wd, uint32_t idx, \ 722 CPURISCVState *env, uintptr_t retaddr)\ 723 { \ 724 typedef int##ESZ##_t ETYPE; \ 725 typedef int##MSZ##_t MTYPE; \ 726 typedef uint##MSZ##_t UMTYPE __attribute__((unused)); \ 727 ETYPE *pe3 = (ETYPE *)vs3 + H(idx); \ 728 MTYPE a = cpu_ld##SUF##_data(env, addr), b = *pe3; \ 729 \ 730 cpu_st##SUF##_data(env, addr, DO_OP(a, b)); \ 731 if (wd) { \ 732 *pe3 = a; \ 733 } \ 734 } 735 736 /* Signed min/max */ 737 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 738 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 739 740 /* Unsigned min/max */ 741 #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) 742 #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) 743 744 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_w, 32, 32, H4, DO_SWAP, l) 745 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_w, 32, 32, H4, DO_ADD, l) 746 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_w, 32, 32, H4, DO_XOR, l) 747 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_w, 32, 32, H4, DO_AND, l) 748 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_w, 32, 32, H4, DO_OR, l) 749 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_w, 32, 32, H4, DO_MIN, l) 750 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_w, 32, 32, H4, DO_MAX, l) 751 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_w, 32, 32, H4, DO_MINU, l) 752 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_w, 32, 32, H4, DO_MAXU, l) 753 #ifdef TARGET_RISCV64 754 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapw_v_d, 64, 32, H8, DO_SWAP, l) 755 GEN_VEXT_AMO_NOATOMIC_OP(vamoswapd_v_d, 64, 64, H8, DO_SWAP, q) 756 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddw_v_d, 64, 32, H8, DO_ADD, l) 757 GEN_VEXT_AMO_NOATOMIC_OP(vamoaddd_v_d, 64, 64, H8, DO_ADD, q) 758 GEN_VEXT_AMO_NOATOMIC_OP(vamoxorw_v_d, 64, 32, H8, DO_XOR, l) 759 GEN_VEXT_AMO_NOATOMIC_OP(vamoxord_v_d, 64, 64, H8, DO_XOR, q) 760 GEN_VEXT_AMO_NOATOMIC_OP(vamoandw_v_d, 64, 32, H8, DO_AND, l) 761 GEN_VEXT_AMO_NOATOMIC_OP(vamoandd_v_d, 64, 64, H8, DO_AND, q) 762 GEN_VEXT_AMO_NOATOMIC_OP(vamoorw_v_d, 64, 32, H8, DO_OR, l) 763 GEN_VEXT_AMO_NOATOMIC_OP(vamoord_v_d, 64, 64, H8, DO_OR, q) 764 GEN_VEXT_AMO_NOATOMIC_OP(vamominw_v_d, 64, 32, H8, DO_MIN, l) 765 GEN_VEXT_AMO_NOATOMIC_OP(vamomind_v_d, 64, 64, H8, DO_MIN, q) 766 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxw_v_d, 64, 32, H8, DO_MAX, l) 767 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxd_v_d, 64, 64, H8, DO_MAX, q) 768 GEN_VEXT_AMO_NOATOMIC_OP(vamominuw_v_d, 64, 32, H8, DO_MINU, l) 769 GEN_VEXT_AMO_NOATOMIC_OP(vamominud_v_d, 64, 64, H8, DO_MINU, q) 770 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxuw_v_d, 64, 32, H8, DO_MAXU, l) 771 GEN_VEXT_AMO_NOATOMIC_OP(vamomaxud_v_d, 64, 64, H8, DO_MAXU, q) 772 #endif 773 774 static inline void 775 vext_amo_noatomic(void *vs3, void *v0, target_ulong base, 776 void *vs2, CPURISCVState *env, uint32_t desc, 777 vext_get_index_addr get_index_addr, 778 vext_amo_noatomic_fn *noatomic_op, 779 clear_fn *clear_elem, 780 uint32_t esz, uint32_t msz, uintptr_t ra) 781 { 782 uint32_t i; 783 target_long addr; 784 uint32_t wd = vext_wd(desc); 785 uint32_t vm = vext_vm(desc); 786 uint32_t mlen = vext_mlen(desc); 787 uint32_t vlmax = vext_maxsz(desc) / esz; 788 789 for (i = 0; i < env->vl; i++) { 790 if (!vm && !vext_elem_mask(v0, mlen, i)) { 791 continue; 792 } 793 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_LOAD); 794 probe_pages(env, get_index_addr(base, i, vs2), msz, ra, MMU_DATA_STORE); 795 } 796 for (i = 0; i < env->vl; i++) { 797 if (!vm && !vext_elem_mask(v0, mlen, i)) { 798 continue; 799 } 800 addr = get_index_addr(base, i, vs2); 801 noatomic_op(vs3, addr, wd, i, env, ra); 802 } 803 clear_elem(vs3, env->vl, env->vl * esz, vlmax * esz); 804 } 805 806 #define GEN_VEXT_AMO(NAME, MTYPE, ETYPE, INDEX_FN, CLEAR_FN) \ 807 void HELPER(NAME)(void *vs3, void *v0, target_ulong base, \ 808 void *vs2, CPURISCVState *env, uint32_t desc) \ 809 { \ 810 vext_amo_noatomic(vs3, v0, base, vs2, env, desc, \ 811 INDEX_FN, vext_##NAME##_noatomic_op, \ 812 CLEAR_FN, sizeof(ETYPE), sizeof(MTYPE), \ 813 GETPC()); \ 814 } 815 816 #ifdef TARGET_RISCV64 817 GEN_VEXT_AMO(vamoswapw_v_d, int32_t, int64_t, idx_d, clearq) 818 GEN_VEXT_AMO(vamoswapd_v_d, int64_t, int64_t, idx_d, clearq) 819 GEN_VEXT_AMO(vamoaddw_v_d, int32_t, int64_t, idx_d, clearq) 820 GEN_VEXT_AMO(vamoaddd_v_d, int64_t, int64_t, idx_d, clearq) 821 GEN_VEXT_AMO(vamoxorw_v_d, int32_t, int64_t, idx_d, clearq) 822 GEN_VEXT_AMO(vamoxord_v_d, int64_t, int64_t, idx_d, clearq) 823 GEN_VEXT_AMO(vamoandw_v_d, int32_t, int64_t, idx_d, clearq) 824 GEN_VEXT_AMO(vamoandd_v_d, int64_t, int64_t, idx_d, clearq) 825 GEN_VEXT_AMO(vamoorw_v_d, int32_t, int64_t, idx_d, clearq) 826 GEN_VEXT_AMO(vamoord_v_d, int64_t, int64_t, idx_d, clearq) 827 GEN_VEXT_AMO(vamominw_v_d, int32_t, int64_t, idx_d, clearq) 828 GEN_VEXT_AMO(vamomind_v_d, int64_t, int64_t, idx_d, clearq) 829 GEN_VEXT_AMO(vamomaxw_v_d, int32_t, int64_t, idx_d, clearq) 830 GEN_VEXT_AMO(vamomaxd_v_d, int64_t, int64_t, idx_d, clearq) 831 GEN_VEXT_AMO(vamominuw_v_d, uint32_t, uint64_t, idx_d, clearq) 832 GEN_VEXT_AMO(vamominud_v_d, uint64_t, uint64_t, idx_d, clearq) 833 GEN_VEXT_AMO(vamomaxuw_v_d, uint32_t, uint64_t, idx_d, clearq) 834 GEN_VEXT_AMO(vamomaxud_v_d, uint64_t, uint64_t, idx_d, clearq) 835 #endif 836 GEN_VEXT_AMO(vamoswapw_v_w, int32_t, int32_t, idx_w, clearl) 837 GEN_VEXT_AMO(vamoaddw_v_w, int32_t, int32_t, idx_w, clearl) 838 GEN_VEXT_AMO(vamoxorw_v_w, int32_t, int32_t, idx_w, clearl) 839 GEN_VEXT_AMO(vamoandw_v_w, int32_t, int32_t, idx_w, clearl) 840 GEN_VEXT_AMO(vamoorw_v_w, int32_t, int32_t, idx_w, clearl) 841 GEN_VEXT_AMO(vamominw_v_w, int32_t, int32_t, idx_w, clearl) 842 GEN_VEXT_AMO(vamomaxw_v_w, int32_t, int32_t, idx_w, clearl) 843 GEN_VEXT_AMO(vamominuw_v_w, uint32_t, uint32_t, idx_w, clearl) 844 GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) 845 846 /* 847 *** Vector Integer Arithmetic Instructions 848 */ 849 850 /* expand macro args before macro */ 851 #define RVVCALL(macro, ...) macro(__VA_ARGS__) 852 853 /* (TD, T1, T2, TX1, TX2) */ 854 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t 855 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t 856 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t 857 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t 858 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t 859 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t 860 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t 861 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 862 #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t 863 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t 864 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t 865 #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t 866 867 /* operation of two vector elements */ 868 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); 869 870 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 871 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ 872 { \ 873 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 874 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 875 *((TD *)vd + HD(i)) = OP(s2, s1); \ 876 } 877 #define DO_SUB(N, M) (N - M) 878 #define DO_RSUB(N, M) (M - N) 879 880 RVVCALL(OPIVV2, vadd_vv_b, OP_SSS_B, H1, H1, H1, DO_ADD) 881 RVVCALL(OPIVV2, vadd_vv_h, OP_SSS_H, H2, H2, H2, DO_ADD) 882 RVVCALL(OPIVV2, vadd_vv_w, OP_SSS_W, H4, H4, H4, DO_ADD) 883 RVVCALL(OPIVV2, vadd_vv_d, OP_SSS_D, H8, H8, H8, DO_ADD) 884 RVVCALL(OPIVV2, vsub_vv_b, OP_SSS_B, H1, H1, H1, DO_SUB) 885 RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB) 886 RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) 887 RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) 888 889 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, 890 CPURISCVState *env, uint32_t desc, 891 uint32_t esz, uint32_t dsz, 892 opivv2_fn *fn, clear_fn *clearfn) 893 { 894 uint32_t vlmax = vext_maxsz(desc) / esz; 895 uint32_t mlen = vext_mlen(desc); 896 uint32_t vm = vext_vm(desc); 897 uint32_t vl = env->vl; 898 uint32_t i; 899 900 for (i = 0; i < vl; i++) { 901 if (!vm && !vext_elem_mask(v0, mlen, i)) { 902 continue; 903 } 904 fn(vd, vs1, vs2, i); 905 } 906 clearfn(vd, vl, vl * dsz, vlmax * dsz); 907 } 908 909 /* generate the helpers for OPIVV */ 910 #define GEN_VEXT_VV(NAME, ESZ, DSZ, CLEAR_FN) \ 911 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 912 void *vs2, CPURISCVState *env, \ 913 uint32_t desc) \ 914 { \ 915 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ 916 do_##NAME, CLEAR_FN); \ 917 } 918 919 GEN_VEXT_VV(vadd_vv_b, 1, 1, clearb) 920 GEN_VEXT_VV(vadd_vv_h, 2, 2, clearh) 921 GEN_VEXT_VV(vadd_vv_w, 4, 4, clearl) 922 GEN_VEXT_VV(vadd_vv_d, 8, 8, clearq) 923 GEN_VEXT_VV(vsub_vv_b, 1, 1, clearb) 924 GEN_VEXT_VV(vsub_vv_h, 2, 2, clearh) 925 GEN_VEXT_VV(vsub_vv_w, 4, 4, clearl) 926 GEN_VEXT_VV(vsub_vv_d, 8, 8, clearq) 927 928 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); 929 930 /* 931 * (T1)s1 gives the real operator type. 932 * (TX1)(T1)s1 expands the operator type of widen or narrow operations. 933 */ 934 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 935 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ 936 { \ 937 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 938 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ 939 } 940 941 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) 942 RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) 943 RVVCALL(OPIVX2, vadd_vx_w, OP_SSS_W, H4, H4, DO_ADD) 944 RVVCALL(OPIVX2, vadd_vx_d, OP_SSS_D, H8, H8, DO_ADD) 945 RVVCALL(OPIVX2, vsub_vx_b, OP_SSS_B, H1, H1, DO_SUB) 946 RVVCALL(OPIVX2, vsub_vx_h, OP_SSS_H, H2, H2, DO_SUB) 947 RVVCALL(OPIVX2, vsub_vx_w, OP_SSS_W, H4, H4, DO_SUB) 948 RVVCALL(OPIVX2, vsub_vx_d, OP_SSS_D, H8, H8, DO_SUB) 949 RVVCALL(OPIVX2, vrsub_vx_b, OP_SSS_B, H1, H1, DO_RSUB) 950 RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) 951 RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) 952 RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) 953 954 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, 955 CPURISCVState *env, uint32_t desc, 956 uint32_t esz, uint32_t dsz, 957 opivx2_fn fn, clear_fn *clearfn) 958 { 959 uint32_t vlmax = vext_maxsz(desc) / esz; 960 uint32_t mlen = vext_mlen(desc); 961 uint32_t vm = vext_vm(desc); 962 uint32_t vl = env->vl; 963 uint32_t i; 964 965 for (i = 0; i < vl; i++) { 966 if (!vm && !vext_elem_mask(v0, mlen, i)) { 967 continue; 968 } 969 fn(vd, s1, vs2, i); 970 } 971 clearfn(vd, vl, vl * dsz, vlmax * dsz); 972 } 973 974 /* generate the helpers for OPIVX */ 975 #define GEN_VEXT_VX(NAME, ESZ, DSZ, CLEAR_FN) \ 976 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 977 void *vs2, CPURISCVState *env, \ 978 uint32_t desc) \ 979 { \ 980 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ 981 do_##NAME, CLEAR_FN); \ 982 } 983 984 GEN_VEXT_VX(vadd_vx_b, 1, 1, clearb) 985 GEN_VEXT_VX(vadd_vx_h, 2, 2, clearh) 986 GEN_VEXT_VX(vadd_vx_w, 4, 4, clearl) 987 GEN_VEXT_VX(vadd_vx_d, 8, 8, clearq) 988 GEN_VEXT_VX(vsub_vx_b, 1, 1, clearb) 989 GEN_VEXT_VX(vsub_vx_h, 2, 2, clearh) 990 GEN_VEXT_VX(vsub_vx_w, 4, 4, clearl) 991 GEN_VEXT_VX(vsub_vx_d, 8, 8, clearq) 992 GEN_VEXT_VX(vrsub_vx_b, 1, 1, clearb) 993 GEN_VEXT_VX(vrsub_vx_h, 2, 2, clearh) 994 GEN_VEXT_VX(vrsub_vx_w, 4, 4, clearl) 995 GEN_VEXT_VX(vrsub_vx_d, 8, 8, clearq) 996 997 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc) 998 { 999 intptr_t oprsz = simd_oprsz(desc); 1000 intptr_t i; 1001 1002 for (i = 0; i < oprsz; i += sizeof(uint8_t)) { 1003 *(uint8_t *)(d + i) = (uint8_t)b - *(uint8_t *)(a + i); 1004 } 1005 } 1006 1007 void HELPER(vec_rsubs16)(void *d, void *a, uint64_t b, uint32_t desc) 1008 { 1009 intptr_t oprsz = simd_oprsz(desc); 1010 intptr_t i; 1011 1012 for (i = 0; i < oprsz; i += sizeof(uint16_t)) { 1013 *(uint16_t *)(d + i) = (uint16_t)b - *(uint16_t *)(a + i); 1014 } 1015 } 1016 1017 void HELPER(vec_rsubs32)(void *d, void *a, uint64_t b, uint32_t desc) 1018 { 1019 intptr_t oprsz = simd_oprsz(desc); 1020 intptr_t i; 1021 1022 for (i = 0; i < oprsz; i += sizeof(uint32_t)) { 1023 *(uint32_t *)(d + i) = (uint32_t)b - *(uint32_t *)(a + i); 1024 } 1025 } 1026 1027 void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc) 1028 { 1029 intptr_t oprsz = simd_oprsz(desc); 1030 intptr_t i; 1031 1032 for (i = 0; i < oprsz; i += sizeof(uint64_t)) { 1033 *(uint64_t *)(d + i) = b - *(uint64_t *)(a + i); 1034 } 1035 } 1036 1037 /* Vector Widening Integer Add/Subtract */ 1038 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t 1039 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t 1040 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t 1041 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t 1042 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t 1043 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t 1044 #define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t 1045 #define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t 1046 #define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t 1047 #define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t 1048 #define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t 1049 #define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t 1050 RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD) 1051 RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD) 1052 RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD) 1053 RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB) 1054 RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB) 1055 RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB) 1056 RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD) 1057 RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD) 1058 RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD) 1059 RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB) 1060 RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB) 1061 RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB) 1062 RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD) 1063 RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD) 1064 RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD) 1065 RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB) 1066 RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB) 1067 RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB) 1068 RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD) 1069 RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD) 1070 RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD) 1071 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB) 1072 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB) 1073 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB) 1074 GEN_VEXT_VV(vwaddu_vv_b, 1, 2, clearh) 1075 GEN_VEXT_VV(vwaddu_vv_h, 2, 4, clearl) 1076 GEN_VEXT_VV(vwaddu_vv_w, 4, 8, clearq) 1077 GEN_VEXT_VV(vwsubu_vv_b, 1, 2, clearh) 1078 GEN_VEXT_VV(vwsubu_vv_h, 2, 4, clearl) 1079 GEN_VEXT_VV(vwsubu_vv_w, 4, 8, clearq) 1080 GEN_VEXT_VV(vwadd_vv_b, 1, 2, clearh) 1081 GEN_VEXT_VV(vwadd_vv_h, 2, 4, clearl) 1082 GEN_VEXT_VV(vwadd_vv_w, 4, 8, clearq) 1083 GEN_VEXT_VV(vwsub_vv_b, 1, 2, clearh) 1084 GEN_VEXT_VV(vwsub_vv_h, 2, 4, clearl) 1085 GEN_VEXT_VV(vwsub_vv_w, 4, 8, clearq) 1086 GEN_VEXT_VV(vwaddu_wv_b, 1, 2, clearh) 1087 GEN_VEXT_VV(vwaddu_wv_h, 2, 4, clearl) 1088 GEN_VEXT_VV(vwaddu_wv_w, 4, 8, clearq) 1089 GEN_VEXT_VV(vwsubu_wv_b, 1, 2, clearh) 1090 GEN_VEXT_VV(vwsubu_wv_h, 2, 4, clearl) 1091 GEN_VEXT_VV(vwsubu_wv_w, 4, 8, clearq) 1092 GEN_VEXT_VV(vwadd_wv_b, 1, 2, clearh) 1093 GEN_VEXT_VV(vwadd_wv_h, 2, 4, clearl) 1094 GEN_VEXT_VV(vwadd_wv_w, 4, 8, clearq) 1095 GEN_VEXT_VV(vwsub_wv_b, 1, 2, clearh) 1096 GEN_VEXT_VV(vwsub_wv_h, 2, 4, clearl) 1097 GEN_VEXT_VV(vwsub_wv_w, 4, 8, clearq) 1098 1099 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD) 1100 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD) 1101 RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD) 1102 RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB) 1103 RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB) 1104 RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB) 1105 RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD) 1106 RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD) 1107 RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD) 1108 RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB) 1109 RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB) 1110 RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB) 1111 RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD) 1112 RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD) 1113 RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD) 1114 RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB) 1115 RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB) 1116 RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB) 1117 RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD) 1118 RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD) 1119 RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD) 1120 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB) 1121 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB) 1122 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB) 1123 GEN_VEXT_VX(vwaddu_vx_b, 1, 2, clearh) 1124 GEN_VEXT_VX(vwaddu_vx_h, 2, 4, clearl) 1125 GEN_VEXT_VX(vwaddu_vx_w, 4, 8, clearq) 1126 GEN_VEXT_VX(vwsubu_vx_b, 1, 2, clearh) 1127 GEN_VEXT_VX(vwsubu_vx_h, 2, 4, clearl) 1128 GEN_VEXT_VX(vwsubu_vx_w, 4, 8, clearq) 1129 GEN_VEXT_VX(vwadd_vx_b, 1, 2, clearh) 1130 GEN_VEXT_VX(vwadd_vx_h, 2, 4, clearl) 1131 GEN_VEXT_VX(vwadd_vx_w, 4, 8, clearq) 1132 GEN_VEXT_VX(vwsub_vx_b, 1, 2, clearh) 1133 GEN_VEXT_VX(vwsub_vx_h, 2, 4, clearl) 1134 GEN_VEXT_VX(vwsub_vx_w, 4, 8, clearq) 1135 GEN_VEXT_VX(vwaddu_wx_b, 1, 2, clearh) 1136 GEN_VEXT_VX(vwaddu_wx_h, 2, 4, clearl) 1137 GEN_VEXT_VX(vwaddu_wx_w, 4, 8, clearq) 1138 GEN_VEXT_VX(vwsubu_wx_b, 1, 2, clearh) 1139 GEN_VEXT_VX(vwsubu_wx_h, 2, 4, clearl) 1140 GEN_VEXT_VX(vwsubu_wx_w, 4, 8, clearq) 1141 GEN_VEXT_VX(vwadd_wx_b, 1, 2, clearh) 1142 GEN_VEXT_VX(vwadd_wx_h, 2, 4, clearl) 1143 GEN_VEXT_VX(vwadd_wx_w, 4, 8, clearq) 1144 GEN_VEXT_VX(vwsub_wx_b, 1, 2, clearh) 1145 GEN_VEXT_VX(vwsub_wx_h, 2, 4, clearl) 1146 GEN_VEXT_VX(vwsub_wx_w, 4, 8, clearq) 1147 1148 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ 1149 #define DO_VADC(N, M, C) (N + M + C) 1150 #define DO_VSBC(N, M, C) (N - M - C) 1151 1152 #define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ 1153 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1154 CPURISCVState *env, uint32_t desc) \ 1155 { \ 1156 uint32_t mlen = vext_mlen(desc); \ 1157 uint32_t vl = env->vl; \ 1158 uint32_t esz = sizeof(ETYPE); \ 1159 uint32_t vlmax = vext_maxsz(desc) / esz; \ 1160 uint32_t i; \ 1161 \ 1162 for (i = 0; i < vl; i++) { \ 1163 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 1164 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1165 uint8_t carry = vext_elem_mask(v0, mlen, i); \ 1166 \ 1167 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ 1168 } \ 1169 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ 1170 } 1171 1172 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC, clearb) 1173 GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC, clearh) 1174 GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC, clearl) 1175 GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC, clearq) 1176 1177 GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC, clearb) 1178 GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC, clearh) 1179 GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC, clearl) 1180 GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC, clearq) 1181 1182 #define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP, CLEAR_FN) \ 1183 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 1184 CPURISCVState *env, uint32_t desc) \ 1185 { \ 1186 uint32_t mlen = vext_mlen(desc); \ 1187 uint32_t vl = env->vl; \ 1188 uint32_t esz = sizeof(ETYPE); \ 1189 uint32_t vlmax = vext_maxsz(desc) / esz; \ 1190 uint32_t i; \ 1191 \ 1192 for (i = 0; i < vl; i++) { \ 1193 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1194 uint8_t carry = vext_elem_mask(v0, mlen, i); \ 1195 \ 1196 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ 1197 } \ 1198 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ 1199 } 1200 1201 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC, clearb) 1202 GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC, clearh) 1203 GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC, clearl) 1204 GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC, clearq) 1205 1206 GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC, clearb) 1207 GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC, clearh) 1208 GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC, clearl) 1209 GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC, clearq) 1210 1211 #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \ 1212 (__typeof(N))(N + M) < N) 1213 #define DO_MSBC(N, M, C) (C ? N <= M : N < M) 1214 1215 #define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \ 1216 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1217 CPURISCVState *env, uint32_t desc) \ 1218 { \ 1219 uint32_t mlen = vext_mlen(desc); \ 1220 uint32_t vl = env->vl; \ 1221 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1222 uint32_t i; \ 1223 \ 1224 for (i = 0; i < vl; i++) { \ 1225 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 1226 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1227 uint8_t carry = vext_elem_mask(v0, mlen, i); \ 1228 \ 1229 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1, carry));\ 1230 } \ 1231 for (; i < vlmax; i++) { \ 1232 vext_set_elem_mask(vd, mlen, i, 0); \ 1233 } \ 1234 } 1235 1236 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) 1237 GEN_VEXT_VMADC_VVM(vmadc_vvm_h, uint16_t, H2, DO_MADC) 1238 GEN_VEXT_VMADC_VVM(vmadc_vvm_w, uint32_t, H4, DO_MADC) 1239 GEN_VEXT_VMADC_VVM(vmadc_vvm_d, uint64_t, H8, DO_MADC) 1240 1241 GEN_VEXT_VMADC_VVM(vmsbc_vvm_b, uint8_t, H1, DO_MSBC) 1242 GEN_VEXT_VMADC_VVM(vmsbc_vvm_h, uint16_t, H2, DO_MSBC) 1243 GEN_VEXT_VMADC_VVM(vmsbc_vvm_w, uint32_t, H4, DO_MSBC) 1244 GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC) 1245 1246 #define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \ 1247 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 1248 void *vs2, CPURISCVState *env, uint32_t desc) \ 1249 { \ 1250 uint32_t mlen = vext_mlen(desc); \ 1251 uint32_t vl = env->vl; \ 1252 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1253 uint32_t i; \ 1254 \ 1255 for (i = 0; i < vl; i++) { \ 1256 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1257 uint8_t carry = vext_elem_mask(v0, mlen, i); \ 1258 \ 1259 vext_set_elem_mask(vd, mlen, i, \ 1260 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ 1261 } \ 1262 for (; i < vlmax; i++) { \ 1263 vext_set_elem_mask(vd, mlen, i, 0); \ 1264 } \ 1265 } 1266 1267 GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC) 1268 GEN_VEXT_VMADC_VXM(vmadc_vxm_h, uint16_t, H2, DO_MADC) 1269 GEN_VEXT_VMADC_VXM(vmadc_vxm_w, uint32_t, H4, DO_MADC) 1270 GEN_VEXT_VMADC_VXM(vmadc_vxm_d, uint64_t, H8, DO_MADC) 1271 1272 GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC) 1273 GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC) 1274 GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC) 1275 GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC) 1276 1277 /* Vector Bitwise Logical Instructions */ 1278 RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND) 1279 RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND) 1280 RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND) 1281 RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND) 1282 RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR) 1283 RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR) 1284 RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR) 1285 RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR) 1286 RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) 1287 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) 1288 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) 1289 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) 1290 GEN_VEXT_VV(vand_vv_b, 1, 1, clearb) 1291 GEN_VEXT_VV(vand_vv_h, 2, 2, clearh) 1292 GEN_VEXT_VV(vand_vv_w, 4, 4, clearl) 1293 GEN_VEXT_VV(vand_vv_d, 8, 8, clearq) 1294 GEN_VEXT_VV(vor_vv_b, 1, 1, clearb) 1295 GEN_VEXT_VV(vor_vv_h, 2, 2, clearh) 1296 GEN_VEXT_VV(vor_vv_w, 4, 4, clearl) 1297 GEN_VEXT_VV(vor_vv_d, 8, 8, clearq) 1298 GEN_VEXT_VV(vxor_vv_b, 1, 1, clearb) 1299 GEN_VEXT_VV(vxor_vv_h, 2, 2, clearh) 1300 GEN_VEXT_VV(vxor_vv_w, 4, 4, clearl) 1301 GEN_VEXT_VV(vxor_vv_d, 8, 8, clearq) 1302 1303 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) 1304 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) 1305 RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND) 1306 RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND) 1307 RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR) 1308 RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR) 1309 RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR) 1310 RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR) 1311 RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) 1312 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) 1313 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) 1314 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) 1315 GEN_VEXT_VX(vand_vx_b, 1, 1, clearb) 1316 GEN_VEXT_VX(vand_vx_h, 2, 2, clearh) 1317 GEN_VEXT_VX(vand_vx_w, 4, 4, clearl) 1318 GEN_VEXT_VX(vand_vx_d, 8, 8, clearq) 1319 GEN_VEXT_VX(vor_vx_b, 1, 1, clearb) 1320 GEN_VEXT_VX(vor_vx_h, 2, 2, clearh) 1321 GEN_VEXT_VX(vor_vx_w, 4, 4, clearl) 1322 GEN_VEXT_VX(vor_vx_d, 8, 8, clearq) 1323 GEN_VEXT_VX(vxor_vx_b, 1, 1, clearb) 1324 GEN_VEXT_VX(vxor_vx_h, 2, 2, clearh) 1325 GEN_VEXT_VX(vxor_vx_w, 4, 4, clearl) 1326 GEN_VEXT_VX(vxor_vx_d, 8, 8, clearq) 1327 1328 /* Vector Single-Width Bit Shift Instructions */ 1329 #define DO_SLL(N, M) (N << (M)) 1330 #define DO_SRL(N, M) (N >> (M)) 1331 1332 /* generate the helpers for shift instructions with two vector operators */ 1333 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK, CLEAR_FN) \ 1334 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 1335 void *vs2, CPURISCVState *env, uint32_t desc) \ 1336 { \ 1337 uint32_t mlen = vext_mlen(desc); \ 1338 uint32_t vm = vext_vm(desc); \ 1339 uint32_t vl = env->vl; \ 1340 uint32_t esz = sizeof(TS1); \ 1341 uint32_t vlmax = vext_maxsz(desc) / esz; \ 1342 uint32_t i; \ 1343 \ 1344 for (i = 0; i < vl; i++) { \ 1345 if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 1346 continue; \ 1347 } \ 1348 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \ 1349 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 1350 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ 1351 } \ 1352 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ 1353 } 1354 1355 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7, clearb) 1356 GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf, clearh) 1357 GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f, clearl) 1358 GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f, clearq) 1359 1360 GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) 1361 GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) 1362 GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) 1363 GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) 1364 1365 GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) 1366 GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) 1367 GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) 1368 GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) 1369 1370 /* generate the helpers for shift instructions with one vector and one scalar */ 1371 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK, CLEAR_FN) \ 1372 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 1373 void *vs2, CPURISCVState *env, uint32_t desc) \ 1374 { \ 1375 uint32_t mlen = vext_mlen(desc); \ 1376 uint32_t vm = vext_vm(desc); \ 1377 uint32_t vl = env->vl; \ 1378 uint32_t esz = sizeof(TD); \ 1379 uint32_t vlmax = vext_maxsz(desc) / esz; \ 1380 uint32_t i; \ 1381 \ 1382 for (i = 0; i < vl; i++) { \ 1383 if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 1384 continue; \ 1385 } \ 1386 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 1387 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ 1388 } \ 1389 CLEAR_FN(vd, vl, vl * esz, vlmax * esz); \ 1390 } 1391 1392 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7, clearb) 1393 GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf, clearh) 1394 GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f, clearl) 1395 GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f, clearq) 1396 1397 GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7, clearb) 1398 GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf, clearh) 1399 GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f, clearl) 1400 GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f, clearq) 1401 1402 GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb) 1403 GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh) 1404 GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl) 1405 GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq) 1406 1407 /* Vector Narrowing Integer Right Shift Instructions */ 1408 GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) 1409 GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) 1410 GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) 1411 GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) 1412 GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) 1413 GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) 1414 GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb) 1415 GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh) 1416 GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl) 1417 GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb) 1418 GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh) 1419 GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl) 1420 1421 /* Vector Integer Comparison Instructions */ 1422 #define DO_MSEQ(N, M) (N == M) 1423 #define DO_MSNE(N, M) (N != M) 1424 #define DO_MSLT(N, M) (N < M) 1425 #define DO_MSLE(N, M) (N <= M) 1426 #define DO_MSGT(N, M) (N > M) 1427 1428 #define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \ 1429 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1430 CPURISCVState *env, uint32_t desc) \ 1431 { \ 1432 uint32_t mlen = vext_mlen(desc); \ 1433 uint32_t vm = vext_vm(desc); \ 1434 uint32_t vl = env->vl; \ 1435 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1436 uint32_t i; \ 1437 \ 1438 for (i = 0; i < vl; i++) { \ 1439 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 1440 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1441 if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 1442 continue; \ 1443 } \ 1444 vext_set_elem_mask(vd, mlen, i, DO_OP(s2, s1)); \ 1445 } \ 1446 for (; i < vlmax; i++) { \ 1447 vext_set_elem_mask(vd, mlen, i, 0); \ 1448 } \ 1449 } 1450 1451 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) 1452 GEN_VEXT_CMP_VV(vmseq_vv_h, uint16_t, H2, DO_MSEQ) 1453 GEN_VEXT_CMP_VV(vmseq_vv_w, uint32_t, H4, DO_MSEQ) 1454 GEN_VEXT_CMP_VV(vmseq_vv_d, uint64_t, H8, DO_MSEQ) 1455 1456 GEN_VEXT_CMP_VV(vmsne_vv_b, uint8_t, H1, DO_MSNE) 1457 GEN_VEXT_CMP_VV(vmsne_vv_h, uint16_t, H2, DO_MSNE) 1458 GEN_VEXT_CMP_VV(vmsne_vv_w, uint32_t, H4, DO_MSNE) 1459 GEN_VEXT_CMP_VV(vmsne_vv_d, uint64_t, H8, DO_MSNE) 1460 1461 GEN_VEXT_CMP_VV(vmsltu_vv_b, uint8_t, H1, DO_MSLT) 1462 GEN_VEXT_CMP_VV(vmsltu_vv_h, uint16_t, H2, DO_MSLT) 1463 GEN_VEXT_CMP_VV(vmsltu_vv_w, uint32_t, H4, DO_MSLT) 1464 GEN_VEXT_CMP_VV(vmsltu_vv_d, uint64_t, H8, DO_MSLT) 1465 1466 GEN_VEXT_CMP_VV(vmslt_vv_b, int8_t, H1, DO_MSLT) 1467 GEN_VEXT_CMP_VV(vmslt_vv_h, int16_t, H2, DO_MSLT) 1468 GEN_VEXT_CMP_VV(vmslt_vv_w, int32_t, H4, DO_MSLT) 1469 GEN_VEXT_CMP_VV(vmslt_vv_d, int64_t, H8, DO_MSLT) 1470 1471 GEN_VEXT_CMP_VV(vmsleu_vv_b, uint8_t, H1, DO_MSLE) 1472 GEN_VEXT_CMP_VV(vmsleu_vv_h, uint16_t, H2, DO_MSLE) 1473 GEN_VEXT_CMP_VV(vmsleu_vv_w, uint32_t, H4, DO_MSLE) 1474 GEN_VEXT_CMP_VV(vmsleu_vv_d, uint64_t, H8, DO_MSLE) 1475 1476 GEN_VEXT_CMP_VV(vmsle_vv_b, int8_t, H1, DO_MSLE) 1477 GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE) 1478 GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE) 1479 GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) 1480 1481 #define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \ 1482 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 1483 CPURISCVState *env, uint32_t desc) \ 1484 { \ 1485 uint32_t mlen = vext_mlen(desc); \ 1486 uint32_t vm = vext_vm(desc); \ 1487 uint32_t vl = env->vl; \ 1488 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1489 uint32_t i; \ 1490 \ 1491 for (i = 0; i < vl; i++) { \ 1492 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1493 if (!vm && !vext_elem_mask(v0, mlen, i)) { \ 1494 continue; \ 1495 } \ 1496 vext_set_elem_mask(vd, mlen, i, \ 1497 DO_OP(s2, (ETYPE)(target_long)s1)); \ 1498 } \ 1499 for (; i < vlmax; i++) { \ 1500 vext_set_elem_mask(vd, mlen, i, 0); \ 1501 } \ 1502 } 1503 1504 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) 1505 GEN_VEXT_CMP_VX(vmseq_vx_h, uint16_t, H2, DO_MSEQ) 1506 GEN_VEXT_CMP_VX(vmseq_vx_w, uint32_t, H4, DO_MSEQ) 1507 GEN_VEXT_CMP_VX(vmseq_vx_d, uint64_t, H8, DO_MSEQ) 1508 1509 GEN_VEXT_CMP_VX(vmsne_vx_b, uint8_t, H1, DO_MSNE) 1510 GEN_VEXT_CMP_VX(vmsne_vx_h, uint16_t, H2, DO_MSNE) 1511 GEN_VEXT_CMP_VX(vmsne_vx_w, uint32_t, H4, DO_MSNE) 1512 GEN_VEXT_CMP_VX(vmsne_vx_d, uint64_t, H8, DO_MSNE) 1513 1514 GEN_VEXT_CMP_VX(vmsltu_vx_b, uint8_t, H1, DO_MSLT) 1515 GEN_VEXT_CMP_VX(vmsltu_vx_h, uint16_t, H2, DO_MSLT) 1516 GEN_VEXT_CMP_VX(vmsltu_vx_w, uint32_t, H4, DO_MSLT) 1517 GEN_VEXT_CMP_VX(vmsltu_vx_d, uint64_t, H8, DO_MSLT) 1518 1519 GEN_VEXT_CMP_VX(vmslt_vx_b, int8_t, H1, DO_MSLT) 1520 GEN_VEXT_CMP_VX(vmslt_vx_h, int16_t, H2, DO_MSLT) 1521 GEN_VEXT_CMP_VX(vmslt_vx_w, int32_t, H4, DO_MSLT) 1522 GEN_VEXT_CMP_VX(vmslt_vx_d, int64_t, H8, DO_MSLT) 1523 1524 GEN_VEXT_CMP_VX(vmsleu_vx_b, uint8_t, H1, DO_MSLE) 1525 GEN_VEXT_CMP_VX(vmsleu_vx_h, uint16_t, H2, DO_MSLE) 1526 GEN_VEXT_CMP_VX(vmsleu_vx_w, uint32_t, H4, DO_MSLE) 1527 GEN_VEXT_CMP_VX(vmsleu_vx_d, uint64_t, H8, DO_MSLE) 1528 1529 GEN_VEXT_CMP_VX(vmsle_vx_b, int8_t, H1, DO_MSLE) 1530 GEN_VEXT_CMP_VX(vmsle_vx_h, int16_t, H2, DO_MSLE) 1531 GEN_VEXT_CMP_VX(vmsle_vx_w, int32_t, H4, DO_MSLE) 1532 GEN_VEXT_CMP_VX(vmsle_vx_d, int64_t, H8, DO_MSLE) 1533 1534 GEN_VEXT_CMP_VX(vmsgtu_vx_b, uint8_t, H1, DO_MSGT) 1535 GEN_VEXT_CMP_VX(vmsgtu_vx_h, uint16_t, H2, DO_MSGT) 1536 GEN_VEXT_CMP_VX(vmsgtu_vx_w, uint32_t, H4, DO_MSGT) 1537 GEN_VEXT_CMP_VX(vmsgtu_vx_d, uint64_t, H8, DO_MSGT) 1538 1539 GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT) 1540 GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT) 1541 GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT) 1542 GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT) 1543 1544 /* Vector Integer Min/Max Instructions */ 1545 RVVCALL(OPIVV2, vminu_vv_b, OP_UUU_B, H1, H1, H1, DO_MIN) 1546 RVVCALL(OPIVV2, vminu_vv_h, OP_UUU_H, H2, H2, H2, DO_MIN) 1547 RVVCALL(OPIVV2, vminu_vv_w, OP_UUU_W, H4, H4, H4, DO_MIN) 1548 RVVCALL(OPIVV2, vminu_vv_d, OP_UUU_D, H8, H8, H8, DO_MIN) 1549 RVVCALL(OPIVV2, vmin_vv_b, OP_SSS_B, H1, H1, H1, DO_MIN) 1550 RVVCALL(OPIVV2, vmin_vv_h, OP_SSS_H, H2, H2, H2, DO_MIN) 1551 RVVCALL(OPIVV2, vmin_vv_w, OP_SSS_W, H4, H4, H4, DO_MIN) 1552 RVVCALL(OPIVV2, vmin_vv_d, OP_SSS_D, H8, H8, H8, DO_MIN) 1553 RVVCALL(OPIVV2, vmaxu_vv_b, OP_UUU_B, H1, H1, H1, DO_MAX) 1554 RVVCALL(OPIVV2, vmaxu_vv_h, OP_UUU_H, H2, H2, H2, DO_MAX) 1555 RVVCALL(OPIVV2, vmaxu_vv_w, OP_UUU_W, H4, H4, H4, DO_MAX) 1556 RVVCALL(OPIVV2, vmaxu_vv_d, OP_UUU_D, H8, H8, H8, DO_MAX) 1557 RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX) 1558 RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX) 1559 RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX) 1560 RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX) 1561 GEN_VEXT_VV(vminu_vv_b, 1, 1, clearb) 1562 GEN_VEXT_VV(vminu_vv_h, 2, 2, clearh) 1563 GEN_VEXT_VV(vminu_vv_w, 4, 4, clearl) 1564 GEN_VEXT_VV(vminu_vv_d, 8, 8, clearq) 1565 GEN_VEXT_VV(vmin_vv_b, 1, 1, clearb) 1566 GEN_VEXT_VV(vmin_vv_h, 2, 2, clearh) 1567 GEN_VEXT_VV(vmin_vv_w, 4, 4, clearl) 1568 GEN_VEXT_VV(vmin_vv_d, 8, 8, clearq) 1569 GEN_VEXT_VV(vmaxu_vv_b, 1, 1, clearb) 1570 GEN_VEXT_VV(vmaxu_vv_h, 2, 2, clearh) 1571 GEN_VEXT_VV(vmaxu_vv_w, 4, 4, clearl) 1572 GEN_VEXT_VV(vmaxu_vv_d, 8, 8, clearq) 1573 GEN_VEXT_VV(vmax_vv_b, 1, 1, clearb) 1574 GEN_VEXT_VV(vmax_vv_h, 2, 2, clearh) 1575 GEN_VEXT_VV(vmax_vv_w, 4, 4, clearl) 1576 GEN_VEXT_VV(vmax_vv_d, 8, 8, clearq) 1577 1578 RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN) 1579 RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN) 1580 RVVCALL(OPIVX2, vminu_vx_w, OP_UUU_W, H4, H4, DO_MIN) 1581 RVVCALL(OPIVX2, vminu_vx_d, OP_UUU_D, H8, H8, DO_MIN) 1582 RVVCALL(OPIVX2, vmin_vx_b, OP_SSS_B, H1, H1, DO_MIN) 1583 RVVCALL(OPIVX2, vmin_vx_h, OP_SSS_H, H2, H2, DO_MIN) 1584 RVVCALL(OPIVX2, vmin_vx_w, OP_SSS_W, H4, H4, DO_MIN) 1585 RVVCALL(OPIVX2, vmin_vx_d, OP_SSS_D, H8, H8, DO_MIN) 1586 RVVCALL(OPIVX2, vmaxu_vx_b, OP_UUU_B, H1, H1, DO_MAX) 1587 RVVCALL(OPIVX2, vmaxu_vx_h, OP_UUU_H, H2, H2, DO_MAX) 1588 RVVCALL(OPIVX2, vmaxu_vx_w, OP_UUU_W, H4, H4, DO_MAX) 1589 RVVCALL(OPIVX2, vmaxu_vx_d, OP_UUU_D, H8, H8, DO_MAX) 1590 RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX) 1591 RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX) 1592 RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX) 1593 RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX) 1594 GEN_VEXT_VX(vminu_vx_b, 1, 1, clearb) 1595 GEN_VEXT_VX(vminu_vx_h, 2, 2, clearh) 1596 GEN_VEXT_VX(vminu_vx_w, 4, 4, clearl) 1597 GEN_VEXT_VX(vminu_vx_d, 8, 8, clearq) 1598 GEN_VEXT_VX(vmin_vx_b, 1, 1, clearb) 1599 GEN_VEXT_VX(vmin_vx_h, 2, 2, clearh) 1600 GEN_VEXT_VX(vmin_vx_w, 4, 4, clearl) 1601 GEN_VEXT_VX(vmin_vx_d, 8, 8, clearq) 1602 GEN_VEXT_VX(vmaxu_vx_b, 1, 1, clearb) 1603 GEN_VEXT_VX(vmaxu_vx_h, 2, 2, clearh) 1604 GEN_VEXT_VX(vmaxu_vx_w, 4, 4, clearl) 1605 GEN_VEXT_VX(vmaxu_vx_d, 8, 8, clearq) 1606 GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb) 1607 GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh) 1608 GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl) 1609 GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq) 1610 1611 /* Vector Single-Width Integer Multiply Instructions */ 1612 #define DO_MUL(N, M) (N * M) 1613 RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL) 1614 RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL) 1615 RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL) 1616 RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL) 1617 GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb) 1618 GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh) 1619 GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl) 1620 GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq) 1621 1622 static int8_t do_mulh_b(int8_t s2, int8_t s1) 1623 { 1624 return (int16_t)s2 * (int16_t)s1 >> 8; 1625 } 1626 1627 static int16_t do_mulh_h(int16_t s2, int16_t s1) 1628 { 1629 return (int32_t)s2 * (int32_t)s1 >> 16; 1630 } 1631 1632 static int32_t do_mulh_w(int32_t s2, int32_t s1) 1633 { 1634 return (int64_t)s2 * (int64_t)s1 >> 32; 1635 } 1636 1637 static int64_t do_mulh_d(int64_t s2, int64_t s1) 1638 { 1639 uint64_t hi_64, lo_64; 1640 1641 muls64(&lo_64, &hi_64, s1, s2); 1642 return hi_64; 1643 } 1644 1645 static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1) 1646 { 1647 return (uint16_t)s2 * (uint16_t)s1 >> 8; 1648 } 1649 1650 static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1) 1651 { 1652 return (uint32_t)s2 * (uint32_t)s1 >> 16; 1653 } 1654 1655 static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1) 1656 { 1657 return (uint64_t)s2 * (uint64_t)s1 >> 32; 1658 } 1659 1660 static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1) 1661 { 1662 uint64_t hi_64, lo_64; 1663 1664 mulu64(&lo_64, &hi_64, s2, s1); 1665 return hi_64; 1666 } 1667 1668 static int8_t do_mulhsu_b(int8_t s2, uint8_t s1) 1669 { 1670 return (int16_t)s2 * (uint16_t)s1 >> 8; 1671 } 1672 1673 static int16_t do_mulhsu_h(int16_t s2, uint16_t s1) 1674 { 1675 return (int32_t)s2 * (uint32_t)s1 >> 16; 1676 } 1677 1678 static int32_t do_mulhsu_w(int32_t s2, uint32_t s1) 1679 { 1680 return (int64_t)s2 * (uint64_t)s1 >> 32; 1681 } 1682 1683 /* 1684 * Let A = signed operand, 1685 * B = unsigned operand 1686 * P = mulu64(A, B), unsigned product 1687 * 1688 * LET X = 2 ** 64 - A, 2's complement of A 1689 * SP = signed product 1690 * THEN 1691 * IF A < 0 1692 * SP = -X * B 1693 * = -(2 ** 64 - A) * B 1694 * = A * B - 2 ** 64 * B 1695 * = P - 2 ** 64 * B 1696 * ELSE 1697 * SP = P 1698 * THEN 1699 * HI_P -= (A < 0 ? B : 0) 1700 */ 1701 1702 static int64_t do_mulhsu_d(int64_t s2, uint64_t s1) 1703 { 1704 uint64_t hi_64, lo_64; 1705 1706 mulu64(&lo_64, &hi_64, s2, s1); 1707 1708 hi_64 -= s2 < 0 ? s1 : 0; 1709 return hi_64; 1710 } 1711 1712 RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b) 1713 RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h) 1714 RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w) 1715 RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d) 1716 RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b) 1717 RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h) 1718 RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w) 1719 RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d) 1720 RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b) 1721 RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h) 1722 RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w) 1723 RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d) 1724 GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb) 1725 GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh) 1726 GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl) 1727 GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq) 1728 GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb) 1729 GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh) 1730 GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl) 1731 GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq) 1732 GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb) 1733 GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh) 1734 GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl) 1735 GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq) 1736 1737 RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL) 1738 RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL) 1739 RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL) 1740 RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL) 1741 RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b) 1742 RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h) 1743 RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w) 1744 RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d) 1745 RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b) 1746 RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h) 1747 RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w) 1748 RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d) 1749 RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b) 1750 RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h) 1751 RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w) 1752 RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d) 1753 GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb) 1754 GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh) 1755 GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl) 1756 GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq) 1757 GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb) 1758 GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh) 1759 GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl) 1760 GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq) 1761 GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb) 1762 GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh) 1763 GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl) 1764 GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq) 1765 GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb) 1766 GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh) 1767 GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl) 1768 GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq) 1769 1770 /* Vector Integer Divide Instructions */ 1771 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M) 1772 #define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M) 1773 #define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\ 1774 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M) 1775 #define DO_REM(N, M) (unlikely(M == 0) ? N :\ 1776 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M) 1777 1778 RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU) 1779 RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU) 1780 RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU) 1781 RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU) 1782 RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV) 1783 RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV) 1784 RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV) 1785 RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV) 1786 RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU) 1787 RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU) 1788 RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU) 1789 RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU) 1790 RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM) 1791 RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM) 1792 RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM) 1793 RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM) 1794 GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb) 1795 GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh) 1796 GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl) 1797 GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq) 1798 GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb) 1799 GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh) 1800 GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl) 1801 GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq) 1802 GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb) 1803 GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh) 1804 GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl) 1805 GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq) 1806 GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb) 1807 GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh) 1808 GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl) 1809 GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq) 1810 1811 RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU) 1812 RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU) 1813 RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU) 1814 RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU) 1815 RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV) 1816 RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV) 1817 RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV) 1818 RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV) 1819 RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU) 1820 RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU) 1821 RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU) 1822 RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU) 1823 RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM) 1824 RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM) 1825 RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM) 1826 RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM) 1827 GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb) 1828 GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh) 1829 GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl) 1830 GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq) 1831 GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb) 1832 GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh) 1833 GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl) 1834 GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq) 1835 GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb) 1836 GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh) 1837 GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl) 1838 GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq) 1839 GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb) 1840 GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh) 1841 GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl) 1842 GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq) 1843