1 /* 2 * RISC-V Vector Extension Helpers for QEMU. 3 * 4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "cpu.h" 21 #include "exec/memop.h" 22 #include "exec/exec-all.h" 23 #include "exec/helper-proto.h" 24 #include "fpu/softfloat.h" 25 #include "tcg/tcg-gvec-desc.h" 26 #include "internals.h" 27 #include <math.h> 28 29 target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, 30 target_ulong s2) 31 { 32 int vlmax, vl; 33 RISCVCPU *cpu = env_archcpu(env); 34 uint64_t lmul = FIELD_EX64(s2, VTYPE, VLMUL); 35 uint16_t sew = 8 << FIELD_EX64(s2, VTYPE, VSEW); 36 uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV); 37 bool vill = FIELD_EX64(s2, VTYPE, VILL); 38 target_ulong reserved = FIELD_EX64(s2, VTYPE, RESERVED); 39 40 if (lmul & 4) { 41 /* Fractional LMUL. */ 42 if (lmul == 4 || 43 cpu->cfg.elen >> (8 - lmul) < sew) { 44 vill = true; 45 } 46 } 47 48 if ((sew > cpu->cfg.elen) 49 || vill 50 || (ediv != 0) 51 || (reserved != 0)) { 52 /* only set vill bit. */ 53 env->vtype = FIELD_DP64(0, VTYPE, VILL, 1); 54 env->vl = 0; 55 env->vstart = 0; 56 return 0; 57 } 58 59 vlmax = vext_get_vlmax(cpu, s2); 60 if (s1 <= vlmax) { 61 vl = s1; 62 } else { 63 vl = vlmax; 64 } 65 env->vl = vl; 66 env->vtype = s2; 67 env->vstart = 0; 68 return vl; 69 } 70 71 /* 72 * Note that vector data is stored in host-endian 64-bit chunks, 73 * so addressing units smaller than that needs a host-endian fixup. 74 */ 75 #ifdef HOST_WORDS_BIGENDIAN 76 #define H1(x) ((x) ^ 7) 77 #define H1_2(x) ((x) ^ 6) 78 #define H1_4(x) ((x) ^ 4) 79 #define H2(x) ((x) ^ 3) 80 #define H4(x) ((x) ^ 1) 81 #define H8(x) ((x)) 82 #else 83 #define H1(x) (x) 84 #define H1_2(x) (x) 85 #define H1_4(x) (x) 86 #define H2(x) (x) 87 #define H4(x) (x) 88 #define H8(x) (x) 89 #endif 90 91 static inline uint32_t vext_nf(uint32_t desc) 92 { 93 return FIELD_EX32(simd_data(desc), VDATA, NF); 94 } 95 96 static inline uint32_t vext_vm(uint32_t desc) 97 { 98 return FIELD_EX32(simd_data(desc), VDATA, VM); 99 } 100 101 /* 102 * Encode LMUL to lmul as following: 103 * LMUL vlmul lmul 104 * 1 000 0 105 * 2 001 1 106 * 4 010 2 107 * 8 011 3 108 * - 100 - 109 * 1/8 101 -3 110 * 1/4 110 -2 111 * 1/2 111 -1 112 */ 113 static inline int32_t vext_lmul(uint32_t desc) 114 { 115 return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); 116 } 117 118 /* 119 * Get vector group length in bytes. Its range is [64, 2048]. 120 * 121 * As simd_desc support at most 256, the max vlen is 512 bits. 122 * So vlen in bytes is encoded as maxsz. 123 */ 124 static inline uint32_t vext_maxsz(uint32_t desc) 125 { 126 return simd_maxsz(desc) << vext_lmul(desc); 127 } 128 129 /* 130 * This function checks watchpoint before real load operation. 131 * 132 * In softmmu mode, the TLB API probe_access is enough for watchpoint check. 133 * In user mode, there is no watchpoint support now. 134 * 135 * It will trigger an exception if there is no mapping in TLB 136 * and page table walk can't fill the TLB entry. Then the guest 137 * software can return here after process the exception or never return. 138 */ 139 static void probe_pages(CPURISCVState *env, target_ulong addr, 140 target_ulong len, uintptr_t ra, 141 MMUAccessType access_type) 142 { 143 target_ulong pagelen = -(addr | TARGET_PAGE_MASK); 144 target_ulong curlen = MIN(pagelen, len); 145 146 probe_access(env, addr, curlen, access_type, 147 cpu_mmu_index(env, false), ra); 148 if (len > curlen) { 149 addr += curlen; 150 curlen = len - curlen; 151 probe_access(env, addr, curlen, access_type, 152 cpu_mmu_index(env, false), ra); 153 } 154 } 155 156 static inline void vext_set_elem_mask(void *v0, int index, 157 uint8_t value) 158 { 159 int idx = index / 64; 160 int pos = index % 64; 161 uint64_t old = ((uint64_t *)v0)[idx]; 162 ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value); 163 } 164 165 /* 166 * Earlier designs (pre-0.9) had a varying number of bits 167 * per mask value (MLEN). In the 0.9 design, MLEN=1. 168 * (Section 4.5) 169 */ 170 static inline int vext_elem_mask(void *v0, int index) 171 { 172 int idx = index / 64; 173 int pos = index % 64; 174 return (((uint64_t *)v0)[idx] >> pos) & 1; 175 } 176 177 /* elements operations for load and store */ 178 typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, 179 uint32_t idx, void *vd, uintptr_t retaddr); 180 181 #define GEN_VEXT_LD_ELEM(NAME, ETYPE, H, LDSUF) \ 182 static void NAME(CPURISCVState *env, abi_ptr addr, \ 183 uint32_t idx, void *vd, uintptr_t retaddr)\ 184 { \ 185 ETYPE *cur = ((ETYPE *)vd + H(idx)); \ 186 *cur = cpu_##LDSUF##_data_ra(env, addr, retaddr); \ 187 } \ 188 189 GEN_VEXT_LD_ELEM(ldb_b, int8_t, H1, ldsb) 190 GEN_VEXT_LD_ELEM(ldb_h, int16_t, H2, ldsb) 191 GEN_VEXT_LD_ELEM(ldb_w, int32_t, H4, ldsb) 192 GEN_VEXT_LD_ELEM(ldb_d, int64_t, H8, ldsb) 193 GEN_VEXT_LD_ELEM(ldh_h, int16_t, H2, ldsw) 194 GEN_VEXT_LD_ELEM(ldh_w, int32_t, H4, ldsw) 195 GEN_VEXT_LD_ELEM(ldh_d, int64_t, H8, ldsw) 196 GEN_VEXT_LD_ELEM(ldw_w, int32_t, H4, ldl) 197 GEN_VEXT_LD_ELEM(ldw_d, int64_t, H8, ldl) 198 GEN_VEXT_LD_ELEM(lde_b, int8_t, H1, ldsb) 199 GEN_VEXT_LD_ELEM(lde_h, int16_t, H2, ldsw) 200 GEN_VEXT_LD_ELEM(lde_w, int32_t, H4, ldl) 201 GEN_VEXT_LD_ELEM(lde_d, int64_t, H8, ldq) 202 GEN_VEXT_LD_ELEM(ldbu_b, uint8_t, H1, ldub) 203 GEN_VEXT_LD_ELEM(ldbu_h, uint16_t, H2, ldub) 204 GEN_VEXT_LD_ELEM(ldbu_w, uint32_t, H4, ldub) 205 GEN_VEXT_LD_ELEM(ldbu_d, uint64_t, H8, ldub) 206 GEN_VEXT_LD_ELEM(ldhu_h, uint16_t, H2, lduw) 207 GEN_VEXT_LD_ELEM(ldhu_w, uint32_t, H4, lduw) 208 GEN_VEXT_LD_ELEM(ldhu_d, uint64_t, H8, lduw) 209 GEN_VEXT_LD_ELEM(ldwu_w, uint32_t, H4, ldl) 210 GEN_VEXT_LD_ELEM(ldwu_d, uint64_t, H8, ldl) 211 212 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ 213 static void NAME(CPURISCVState *env, abi_ptr addr, \ 214 uint32_t idx, void *vd, uintptr_t retaddr)\ 215 { \ 216 ETYPE data = *((ETYPE *)vd + H(idx)); \ 217 cpu_##STSUF##_data_ra(env, addr, data, retaddr); \ 218 } 219 220 GEN_VEXT_ST_ELEM(stb_b, int8_t, H1, stb) 221 GEN_VEXT_ST_ELEM(stb_h, int16_t, H2, stb) 222 GEN_VEXT_ST_ELEM(stb_w, int32_t, H4, stb) 223 GEN_VEXT_ST_ELEM(stb_d, int64_t, H8, stb) 224 GEN_VEXT_ST_ELEM(sth_h, int16_t, H2, stw) 225 GEN_VEXT_ST_ELEM(sth_w, int32_t, H4, stw) 226 GEN_VEXT_ST_ELEM(sth_d, int64_t, H8, stw) 227 GEN_VEXT_ST_ELEM(stw_w, int32_t, H4, stl) 228 GEN_VEXT_ST_ELEM(stw_d, int64_t, H8, stl) 229 GEN_VEXT_ST_ELEM(ste_b, int8_t, H1, stb) 230 GEN_VEXT_ST_ELEM(ste_h, int16_t, H2, stw) 231 GEN_VEXT_ST_ELEM(ste_w, int32_t, H4, stl) 232 GEN_VEXT_ST_ELEM(ste_d, int64_t, H8, stq) 233 234 /* 235 *** stride: access vector element from strided memory 236 */ 237 static void 238 vext_ldst_stride(void *vd, void *v0, target_ulong base, 239 target_ulong stride, CPURISCVState *env, 240 uint32_t desc, uint32_t vm, 241 vext_ldst_elem_fn *ldst_elem, 242 uint32_t esz, uintptr_t ra, MMUAccessType access_type) 243 { 244 uint32_t i, k; 245 uint32_t nf = vext_nf(desc); 246 uint32_t vlmax = vext_maxsz(desc) / esz; 247 248 /* probe every access*/ 249 for (i = 0; i < env->vl; i++) { 250 if (!vm && !vext_elem_mask(v0, i)) { 251 continue; 252 } 253 probe_pages(env, base + stride * i, nf * esz, ra, access_type); 254 } 255 /* do real access */ 256 for (i = 0; i < env->vl; i++) { 257 k = 0; 258 if (!vm && !vext_elem_mask(v0, i)) { 259 continue; 260 } 261 while (k < nf) { 262 target_ulong addr = base + stride * i + k * esz; 263 ldst_elem(env, addr, i + k * vlmax, vd, ra); 264 k++; 265 } 266 } 267 } 268 269 #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) \ 270 void HELPER(NAME)(void *vd, void * v0, target_ulong base, \ 271 target_ulong stride, CPURISCVState *env, \ 272 uint32_t desc) \ 273 { \ 274 uint32_t vm = vext_vm(desc); \ 275 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, LOAD_FN, \ 276 sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ 277 } 278 279 GEN_VEXT_LD_STRIDE(vlse8_v, int8_t, lde_b) 280 GEN_VEXT_LD_STRIDE(vlse16_v, int16_t, lde_h) 281 GEN_VEXT_LD_STRIDE(vlse32_v, int32_t, lde_w) 282 GEN_VEXT_LD_STRIDE(vlse64_v, int64_t, lde_d) 283 284 #define GEN_VEXT_ST_STRIDE(NAME, ETYPE, STORE_FN) \ 285 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 286 target_ulong stride, CPURISCVState *env, \ 287 uint32_t desc) \ 288 { \ 289 uint32_t vm = vext_vm(desc); \ 290 vext_ldst_stride(vd, v0, base, stride, env, desc, vm, STORE_FN, \ 291 sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ 292 } 293 294 GEN_VEXT_ST_STRIDE(vsse8_v, int8_t, ste_b) 295 GEN_VEXT_ST_STRIDE(vsse16_v, int16_t, ste_h) 296 GEN_VEXT_ST_STRIDE(vsse32_v, int32_t, ste_w) 297 GEN_VEXT_ST_STRIDE(vsse64_v, int64_t, ste_d) 298 299 /* 300 *** unit-stride: access elements stored contiguously in memory 301 */ 302 303 /* unmasked unit-stride load and store operation*/ 304 static void 305 vext_ldst_us(void *vd, target_ulong base, CPURISCVState *env, uint32_t desc, 306 vext_ldst_elem_fn *ldst_elem, 307 uint32_t esz, uintptr_t ra, MMUAccessType access_type) 308 { 309 uint32_t i, k; 310 uint32_t nf = vext_nf(desc); 311 uint32_t vlmax = vext_maxsz(desc) / esz; 312 313 /* probe every access */ 314 probe_pages(env, base, env->vl * nf * esz, ra, access_type); 315 /* load bytes from guest memory */ 316 for (i = 0; i < env->vl; i++) { 317 k = 0; 318 while (k < nf) { 319 target_ulong addr = base + (i * nf + k) * esz; 320 ldst_elem(env, addr, i + k * vlmax, vd, ra); 321 k++; 322 } 323 } 324 } 325 326 /* 327 * masked unit-stride load and store operation will be a special case of stride, 328 * stride = NF * sizeof (MTYPE) 329 */ 330 331 #define GEN_VEXT_LD_US(NAME, ETYPE, LOAD_FN) \ 332 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ 333 CPURISCVState *env, uint32_t desc) \ 334 { \ 335 uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ 336 vext_ldst_stride(vd, v0, base, stride, env, desc, false, LOAD_FN, \ 337 sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ 338 } \ 339 \ 340 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 341 CPURISCVState *env, uint32_t desc) \ 342 { \ 343 vext_ldst_us(vd, base, env, desc, LOAD_FN, \ 344 sizeof(ETYPE), GETPC(), MMU_DATA_LOAD); \ 345 } 346 347 GEN_VEXT_LD_US(vle8_v, int8_t, lde_b) 348 GEN_VEXT_LD_US(vle16_v, int16_t, lde_h) 349 GEN_VEXT_LD_US(vle32_v, int32_t, lde_w) 350 GEN_VEXT_LD_US(vle64_v, int64_t, lde_d) 351 352 #define GEN_VEXT_ST_US(NAME, ETYPE, STORE_FN) \ 353 void HELPER(NAME##_mask)(void *vd, void *v0, target_ulong base, \ 354 CPURISCVState *env, uint32_t desc) \ 355 { \ 356 uint32_t stride = vext_nf(desc) * sizeof(ETYPE); \ 357 vext_ldst_stride(vd, v0, base, stride, env, desc, false, STORE_FN, \ 358 sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ 359 } \ 360 \ 361 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 362 CPURISCVState *env, uint32_t desc) \ 363 { \ 364 vext_ldst_us(vd, base, env, desc, STORE_FN, \ 365 sizeof(ETYPE), GETPC(), MMU_DATA_STORE); \ 366 } 367 368 GEN_VEXT_ST_US(vse8_v, int8_t, ste_b) 369 GEN_VEXT_ST_US(vse16_v, int16_t, ste_h) 370 GEN_VEXT_ST_US(vse32_v, int32_t, ste_w) 371 GEN_VEXT_ST_US(vse64_v, int64_t, ste_d) 372 373 /* 374 *** index: access vector element from indexed memory 375 */ 376 typedef target_ulong vext_get_index_addr(target_ulong base, 377 uint32_t idx, void *vs2); 378 379 #define GEN_VEXT_GET_INDEX_ADDR(NAME, ETYPE, H) \ 380 static target_ulong NAME(target_ulong base, \ 381 uint32_t idx, void *vs2) \ 382 { \ 383 return (base + *((ETYPE *)vs2 + H(idx))); \ 384 } 385 386 GEN_VEXT_GET_INDEX_ADDR(idx_b, int8_t, H1) 387 GEN_VEXT_GET_INDEX_ADDR(idx_h, int16_t, H2) 388 GEN_VEXT_GET_INDEX_ADDR(idx_w, int32_t, H4) 389 GEN_VEXT_GET_INDEX_ADDR(idx_d, int64_t, H8) 390 391 static inline void 392 vext_ldst_index(void *vd, void *v0, target_ulong base, 393 void *vs2, CPURISCVState *env, uint32_t desc, 394 vext_get_index_addr get_index_addr, 395 vext_ldst_elem_fn *ldst_elem, 396 uint32_t esz, uint32_t msz, uintptr_t ra, 397 MMUAccessType access_type) 398 { 399 uint32_t i, k; 400 uint32_t nf = vext_nf(desc); 401 uint32_t vm = vext_vm(desc); 402 uint32_t vlmax = vext_maxsz(desc) / esz; 403 404 /* probe every access*/ 405 for (i = 0; i < env->vl; i++) { 406 if (!vm && !vext_elem_mask(v0, i)) { 407 continue; 408 } 409 probe_pages(env, get_index_addr(base, i, vs2), nf * msz, ra, 410 access_type); 411 } 412 /* load bytes from guest memory */ 413 for (i = 0; i < env->vl; i++) { 414 k = 0; 415 if (!vm && !vext_elem_mask(v0, i)) { 416 continue; 417 } 418 while (k < nf) { 419 abi_ptr addr = get_index_addr(base, i, vs2) + k * msz; 420 ldst_elem(env, addr, i + k * vlmax, vd, ra); 421 k++; 422 } 423 } 424 } 425 426 #define GEN_VEXT_LD_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, LOAD_FN) \ 427 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 428 void *vs2, CPURISCVState *env, uint32_t desc) \ 429 { \ 430 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ 431 LOAD_FN, sizeof(ETYPE), sizeof(MTYPE), \ 432 GETPC(), MMU_DATA_LOAD); \ 433 } 434 435 GEN_VEXT_LD_INDEX(vlxb_v_b, int8_t, int8_t, idx_b, ldb_b) 436 GEN_VEXT_LD_INDEX(vlxb_v_h, int8_t, int16_t, idx_h, ldb_h) 437 GEN_VEXT_LD_INDEX(vlxb_v_w, int8_t, int32_t, idx_w, ldb_w) 438 GEN_VEXT_LD_INDEX(vlxb_v_d, int8_t, int64_t, idx_d, ldb_d) 439 GEN_VEXT_LD_INDEX(vlxh_v_h, int16_t, int16_t, idx_h, ldh_h) 440 GEN_VEXT_LD_INDEX(vlxh_v_w, int16_t, int32_t, idx_w, ldh_w) 441 GEN_VEXT_LD_INDEX(vlxh_v_d, int16_t, int64_t, idx_d, ldh_d) 442 GEN_VEXT_LD_INDEX(vlxw_v_w, int32_t, int32_t, idx_w, ldw_w) 443 GEN_VEXT_LD_INDEX(vlxw_v_d, int32_t, int64_t, idx_d, ldw_d) 444 GEN_VEXT_LD_INDEX(vlxe_v_b, int8_t, int8_t, idx_b, lde_b) 445 GEN_VEXT_LD_INDEX(vlxe_v_h, int16_t, int16_t, idx_h, lde_h) 446 GEN_VEXT_LD_INDEX(vlxe_v_w, int32_t, int32_t, idx_w, lde_w) 447 GEN_VEXT_LD_INDEX(vlxe_v_d, int64_t, int64_t, idx_d, lde_d) 448 GEN_VEXT_LD_INDEX(vlxbu_v_b, uint8_t, uint8_t, idx_b, ldbu_b) 449 GEN_VEXT_LD_INDEX(vlxbu_v_h, uint8_t, uint16_t, idx_h, ldbu_h) 450 GEN_VEXT_LD_INDEX(vlxbu_v_w, uint8_t, uint32_t, idx_w, ldbu_w) 451 GEN_VEXT_LD_INDEX(vlxbu_v_d, uint8_t, uint64_t, idx_d, ldbu_d) 452 GEN_VEXT_LD_INDEX(vlxhu_v_h, uint16_t, uint16_t, idx_h, ldhu_h) 453 GEN_VEXT_LD_INDEX(vlxhu_v_w, uint16_t, uint32_t, idx_w, ldhu_w) 454 GEN_VEXT_LD_INDEX(vlxhu_v_d, uint16_t, uint64_t, idx_d, ldhu_d) 455 GEN_VEXT_LD_INDEX(vlxwu_v_w, uint32_t, uint32_t, idx_w, ldwu_w) 456 GEN_VEXT_LD_INDEX(vlxwu_v_d, uint32_t, uint64_t, idx_d, ldwu_d) 457 458 #define GEN_VEXT_ST_INDEX(NAME, MTYPE, ETYPE, INDEX_FN, STORE_FN)\ 459 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 460 void *vs2, CPURISCVState *env, uint32_t desc) \ 461 { \ 462 vext_ldst_index(vd, v0, base, vs2, env, desc, INDEX_FN, \ 463 STORE_FN, sizeof(ETYPE), sizeof(MTYPE), \ 464 GETPC(), MMU_DATA_STORE); \ 465 } 466 467 GEN_VEXT_ST_INDEX(vsxb_v_b, int8_t, int8_t, idx_b, stb_b) 468 GEN_VEXT_ST_INDEX(vsxb_v_h, int8_t, int16_t, idx_h, stb_h) 469 GEN_VEXT_ST_INDEX(vsxb_v_w, int8_t, int32_t, idx_w, stb_w) 470 GEN_VEXT_ST_INDEX(vsxb_v_d, int8_t, int64_t, idx_d, stb_d) 471 GEN_VEXT_ST_INDEX(vsxh_v_h, int16_t, int16_t, idx_h, sth_h) 472 GEN_VEXT_ST_INDEX(vsxh_v_w, int16_t, int32_t, idx_w, sth_w) 473 GEN_VEXT_ST_INDEX(vsxh_v_d, int16_t, int64_t, idx_d, sth_d) 474 GEN_VEXT_ST_INDEX(vsxw_v_w, int32_t, int32_t, idx_w, stw_w) 475 GEN_VEXT_ST_INDEX(vsxw_v_d, int32_t, int64_t, idx_d, stw_d) 476 GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t, idx_b, ste_b) 477 GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t, idx_h, ste_h) 478 GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t, idx_w, ste_w) 479 GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t, idx_d, ste_d) 480 481 /* 482 *** unit-stride fault-only-fisrt load instructions 483 */ 484 static inline void 485 vext_ldff(void *vd, void *v0, target_ulong base, 486 CPURISCVState *env, uint32_t desc, 487 vext_ldst_elem_fn *ldst_elem, 488 uint32_t esz, uint32_t msz, uintptr_t ra) 489 { 490 void *host; 491 uint32_t i, k, vl = 0; 492 uint32_t nf = vext_nf(desc); 493 uint32_t vm = vext_vm(desc); 494 uint32_t vlmax = vext_maxsz(desc) / esz; 495 target_ulong addr, offset, remain; 496 497 /* probe every access*/ 498 for (i = 0; i < env->vl; i++) { 499 if (!vm && !vext_elem_mask(v0, i)) { 500 continue; 501 } 502 addr = base + nf * i * msz; 503 if (i == 0) { 504 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); 505 } else { 506 /* if it triggers an exception, no need to check watchpoint */ 507 remain = nf * msz; 508 while (remain > 0) { 509 offset = -(addr | TARGET_PAGE_MASK); 510 host = tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, 511 cpu_mmu_index(env, false)); 512 if (host) { 513 #ifdef CONFIG_USER_ONLY 514 if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { 515 vl = i; 516 goto ProbeSuccess; 517 } 518 #else 519 probe_pages(env, addr, nf * msz, ra, MMU_DATA_LOAD); 520 #endif 521 } else { 522 vl = i; 523 goto ProbeSuccess; 524 } 525 if (remain <= offset) { 526 break; 527 } 528 remain -= offset; 529 addr += offset; 530 } 531 } 532 } 533 ProbeSuccess: 534 /* load bytes from guest memory */ 535 if (vl != 0) { 536 env->vl = vl; 537 } 538 for (i = 0; i < env->vl; i++) { 539 k = 0; 540 if (!vm && !vext_elem_mask(v0, i)) { 541 continue; 542 } 543 while (k < nf) { 544 target_ulong addr = base + (i * nf + k) * msz; 545 ldst_elem(env, addr, i + k * vlmax, vd, ra); 546 k++; 547 } 548 } 549 } 550 551 #define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, LOAD_FN) \ 552 void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ 553 CPURISCVState *env, uint32_t desc) \ 554 { \ 555 vext_ldff(vd, v0, base, env, desc, LOAD_FN, \ 556 sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ 557 } 558 559 GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, ldb_b) 560 GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, ldb_h) 561 GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, ldb_w) 562 GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, ldb_d) 563 GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, ldh_h) 564 GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, ldh_w) 565 GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, ldh_d) 566 GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, ldw_w) 567 GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, ldw_d) 568 GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, lde_b) 569 GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, lde_h) 570 GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, lde_w) 571 GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, lde_d) 572 GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, ldbu_b) 573 GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, ldbu_h) 574 GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, ldbu_w) 575 GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, ldbu_d) 576 GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, ldhu_h) 577 GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, ldhu_w) 578 GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, ldhu_d) 579 GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, ldwu_w) 580 GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, ldwu_d) 581 582 #define DO_SWAP(N, M) (M) 583 #define DO_AND(N, M) (N & M) 584 #define DO_XOR(N, M) (N ^ M) 585 #define DO_OR(N, M) (N | M) 586 #define DO_ADD(N, M) (N + M) 587 588 /* Signed min/max */ 589 #define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) 590 #define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) 591 592 /* Unsigned min/max */ 593 #define DO_MAXU(N, M) DO_MAX((UMTYPE)N, (UMTYPE)M) 594 #define DO_MINU(N, M) DO_MIN((UMTYPE)N, (UMTYPE)M) 595 596 /* 597 *** Vector Integer Arithmetic Instructions 598 */ 599 600 /* expand macro args before macro */ 601 #define RVVCALL(macro, ...) macro(__VA_ARGS__) 602 603 /* (TD, T1, T2, TX1, TX2) */ 604 #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t 605 #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t 606 #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t 607 #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t 608 #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t 609 #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t 610 #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t 611 #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t 612 #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t 613 #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t 614 #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t 615 #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t 616 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t 617 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t 618 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t 619 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t 620 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t 621 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t 622 #define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t 623 #define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t 624 #define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t 625 #define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t 626 #define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t 627 #define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t 628 #define NOP_SSS_B int8_t, int8_t, int16_t, int8_t, int16_t 629 #define NOP_SSS_H int16_t, int16_t, int32_t, int16_t, int32_t 630 #define NOP_SSS_W int32_t, int32_t, int64_t, int32_t, int64_t 631 #define NOP_UUU_B uint8_t, uint8_t, uint16_t, uint8_t, uint16_t 632 #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t 633 #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t 634 635 /* operation of two vector elements */ 636 typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); 637 638 #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 639 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ 640 { \ 641 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 642 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 643 *((TD *)vd + HD(i)) = OP(s2, s1); \ 644 } 645 #define DO_SUB(N, M) (N - M) 646 #define DO_RSUB(N, M) (M - N) 647 648 RVVCALL(OPIVV2, vadd_vv_b, OP_SSS_B, H1, H1, H1, DO_ADD) 649 RVVCALL(OPIVV2, vadd_vv_h, OP_SSS_H, H2, H2, H2, DO_ADD) 650 RVVCALL(OPIVV2, vadd_vv_w, OP_SSS_W, H4, H4, H4, DO_ADD) 651 RVVCALL(OPIVV2, vadd_vv_d, OP_SSS_D, H8, H8, H8, DO_ADD) 652 RVVCALL(OPIVV2, vsub_vv_b, OP_SSS_B, H1, H1, H1, DO_SUB) 653 RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB) 654 RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) 655 RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) 656 657 static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, 658 CPURISCVState *env, uint32_t desc, 659 uint32_t esz, uint32_t dsz, 660 opivv2_fn *fn) 661 { 662 uint32_t vm = vext_vm(desc); 663 uint32_t vl = env->vl; 664 uint32_t i; 665 666 for (i = 0; i < vl; i++) { 667 if (!vm && !vext_elem_mask(v0, i)) { 668 continue; 669 } 670 fn(vd, vs1, vs2, i); 671 } 672 } 673 674 /* generate the helpers for OPIVV */ 675 #define GEN_VEXT_VV(NAME, ESZ, DSZ) \ 676 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 677 void *vs2, CPURISCVState *env, \ 678 uint32_t desc) \ 679 { \ 680 do_vext_vv(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ 681 do_##NAME); \ 682 } 683 684 GEN_VEXT_VV(vadd_vv_b, 1, 1) 685 GEN_VEXT_VV(vadd_vv_h, 2, 2) 686 GEN_VEXT_VV(vadd_vv_w, 4, 4) 687 GEN_VEXT_VV(vadd_vv_d, 8, 8) 688 GEN_VEXT_VV(vsub_vv_b, 1, 1) 689 GEN_VEXT_VV(vsub_vv_h, 2, 2) 690 GEN_VEXT_VV(vsub_vv_w, 4, 4) 691 GEN_VEXT_VV(vsub_vv_d, 8, 8) 692 693 typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); 694 695 /* 696 * (T1)s1 gives the real operator type. 697 * (TX1)(T1)s1 expands the operator type of widen or narrow operations. 698 */ 699 #define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 700 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ 701 { \ 702 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 703 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ 704 } 705 706 RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) 707 RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) 708 RVVCALL(OPIVX2, vadd_vx_w, OP_SSS_W, H4, H4, DO_ADD) 709 RVVCALL(OPIVX2, vadd_vx_d, OP_SSS_D, H8, H8, DO_ADD) 710 RVVCALL(OPIVX2, vsub_vx_b, OP_SSS_B, H1, H1, DO_SUB) 711 RVVCALL(OPIVX2, vsub_vx_h, OP_SSS_H, H2, H2, DO_SUB) 712 RVVCALL(OPIVX2, vsub_vx_w, OP_SSS_W, H4, H4, DO_SUB) 713 RVVCALL(OPIVX2, vsub_vx_d, OP_SSS_D, H8, H8, DO_SUB) 714 RVVCALL(OPIVX2, vrsub_vx_b, OP_SSS_B, H1, H1, DO_RSUB) 715 RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) 716 RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) 717 RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) 718 719 static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, 720 CPURISCVState *env, uint32_t desc, 721 uint32_t esz, uint32_t dsz, 722 opivx2_fn fn) 723 { 724 uint32_t vm = vext_vm(desc); 725 uint32_t vl = env->vl; 726 uint32_t i; 727 728 for (i = 0; i < vl; i++) { 729 if (!vm && !vext_elem_mask(v0, i)) { 730 continue; 731 } 732 fn(vd, s1, vs2, i); 733 } 734 } 735 736 /* generate the helpers for OPIVX */ 737 #define GEN_VEXT_VX(NAME, ESZ, DSZ) \ 738 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 739 void *vs2, CPURISCVState *env, \ 740 uint32_t desc) \ 741 { \ 742 do_vext_vx(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ 743 do_##NAME); \ 744 } 745 746 GEN_VEXT_VX(vadd_vx_b, 1, 1) 747 GEN_VEXT_VX(vadd_vx_h, 2, 2) 748 GEN_VEXT_VX(vadd_vx_w, 4, 4) 749 GEN_VEXT_VX(vadd_vx_d, 8, 8) 750 GEN_VEXT_VX(vsub_vx_b, 1, 1) 751 GEN_VEXT_VX(vsub_vx_h, 2, 2) 752 GEN_VEXT_VX(vsub_vx_w, 4, 4) 753 GEN_VEXT_VX(vsub_vx_d, 8, 8) 754 GEN_VEXT_VX(vrsub_vx_b, 1, 1) 755 GEN_VEXT_VX(vrsub_vx_h, 2, 2) 756 GEN_VEXT_VX(vrsub_vx_w, 4, 4) 757 GEN_VEXT_VX(vrsub_vx_d, 8, 8) 758 759 void HELPER(vec_rsubs8)(void *d, void *a, uint64_t b, uint32_t desc) 760 { 761 intptr_t oprsz = simd_oprsz(desc); 762 intptr_t i; 763 764 for (i = 0; i < oprsz; i += sizeof(uint8_t)) { 765 *(uint8_t *)(d + i) = (uint8_t)b - *(uint8_t *)(a + i); 766 } 767 } 768 769 void HELPER(vec_rsubs16)(void *d, void *a, uint64_t b, uint32_t desc) 770 { 771 intptr_t oprsz = simd_oprsz(desc); 772 intptr_t i; 773 774 for (i = 0; i < oprsz; i += sizeof(uint16_t)) { 775 *(uint16_t *)(d + i) = (uint16_t)b - *(uint16_t *)(a + i); 776 } 777 } 778 779 void HELPER(vec_rsubs32)(void *d, void *a, uint64_t b, uint32_t desc) 780 { 781 intptr_t oprsz = simd_oprsz(desc); 782 intptr_t i; 783 784 for (i = 0; i < oprsz; i += sizeof(uint32_t)) { 785 *(uint32_t *)(d + i) = (uint32_t)b - *(uint32_t *)(a + i); 786 } 787 } 788 789 void HELPER(vec_rsubs64)(void *d, void *a, uint64_t b, uint32_t desc) 790 { 791 intptr_t oprsz = simd_oprsz(desc); 792 intptr_t i; 793 794 for (i = 0; i < oprsz; i += sizeof(uint64_t)) { 795 *(uint64_t *)(d + i) = b - *(uint64_t *)(a + i); 796 } 797 } 798 799 /* Vector Widening Integer Add/Subtract */ 800 #define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t 801 #define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t 802 #define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t 803 #define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t 804 #define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t 805 #define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t 806 #define WOP_WUUU_B uint16_t, uint8_t, uint16_t, uint16_t, uint16_t 807 #define WOP_WUUU_H uint32_t, uint16_t, uint32_t, uint32_t, uint32_t 808 #define WOP_WUUU_W uint64_t, uint32_t, uint64_t, uint64_t, uint64_t 809 #define WOP_WSSS_B int16_t, int8_t, int16_t, int16_t, int16_t 810 #define WOP_WSSS_H int32_t, int16_t, int32_t, int32_t, int32_t 811 #define WOP_WSSS_W int64_t, int32_t, int64_t, int64_t, int64_t 812 RVVCALL(OPIVV2, vwaddu_vv_b, WOP_UUU_B, H2, H1, H1, DO_ADD) 813 RVVCALL(OPIVV2, vwaddu_vv_h, WOP_UUU_H, H4, H2, H2, DO_ADD) 814 RVVCALL(OPIVV2, vwaddu_vv_w, WOP_UUU_W, H8, H4, H4, DO_ADD) 815 RVVCALL(OPIVV2, vwsubu_vv_b, WOP_UUU_B, H2, H1, H1, DO_SUB) 816 RVVCALL(OPIVV2, vwsubu_vv_h, WOP_UUU_H, H4, H2, H2, DO_SUB) 817 RVVCALL(OPIVV2, vwsubu_vv_w, WOP_UUU_W, H8, H4, H4, DO_SUB) 818 RVVCALL(OPIVV2, vwadd_vv_b, WOP_SSS_B, H2, H1, H1, DO_ADD) 819 RVVCALL(OPIVV2, vwadd_vv_h, WOP_SSS_H, H4, H2, H2, DO_ADD) 820 RVVCALL(OPIVV2, vwadd_vv_w, WOP_SSS_W, H8, H4, H4, DO_ADD) 821 RVVCALL(OPIVV2, vwsub_vv_b, WOP_SSS_B, H2, H1, H1, DO_SUB) 822 RVVCALL(OPIVV2, vwsub_vv_h, WOP_SSS_H, H4, H2, H2, DO_SUB) 823 RVVCALL(OPIVV2, vwsub_vv_w, WOP_SSS_W, H8, H4, H4, DO_SUB) 824 RVVCALL(OPIVV2, vwaddu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_ADD) 825 RVVCALL(OPIVV2, vwaddu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_ADD) 826 RVVCALL(OPIVV2, vwaddu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_ADD) 827 RVVCALL(OPIVV2, vwsubu_wv_b, WOP_WUUU_B, H2, H1, H1, DO_SUB) 828 RVVCALL(OPIVV2, vwsubu_wv_h, WOP_WUUU_H, H4, H2, H2, DO_SUB) 829 RVVCALL(OPIVV2, vwsubu_wv_w, WOP_WUUU_W, H8, H4, H4, DO_SUB) 830 RVVCALL(OPIVV2, vwadd_wv_b, WOP_WSSS_B, H2, H1, H1, DO_ADD) 831 RVVCALL(OPIVV2, vwadd_wv_h, WOP_WSSS_H, H4, H2, H2, DO_ADD) 832 RVVCALL(OPIVV2, vwadd_wv_w, WOP_WSSS_W, H8, H4, H4, DO_ADD) 833 RVVCALL(OPIVV2, vwsub_wv_b, WOP_WSSS_B, H2, H1, H1, DO_SUB) 834 RVVCALL(OPIVV2, vwsub_wv_h, WOP_WSSS_H, H4, H2, H2, DO_SUB) 835 RVVCALL(OPIVV2, vwsub_wv_w, WOP_WSSS_W, H8, H4, H4, DO_SUB) 836 GEN_VEXT_VV(vwaddu_vv_b, 1, 2) 837 GEN_VEXT_VV(vwaddu_vv_h, 2, 4) 838 GEN_VEXT_VV(vwaddu_vv_w, 4, 8) 839 GEN_VEXT_VV(vwsubu_vv_b, 1, 2) 840 GEN_VEXT_VV(vwsubu_vv_h, 2, 4) 841 GEN_VEXT_VV(vwsubu_vv_w, 4, 8) 842 GEN_VEXT_VV(vwadd_vv_b, 1, 2) 843 GEN_VEXT_VV(vwadd_vv_h, 2, 4) 844 GEN_VEXT_VV(vwadd_vv_w, 4, 8) 845 GEN_VEXT_VV(vwsub_vv_b, 1, 2) 846 GEN_VEXT_VV(vwsub_vv_h, 2, 4) 847 GEN_VEXT_VV(vwsub_vv_w, 4, 8) 848 GEN_VEXT_VV(vwaddu_wv_b, 1, 2) 849 GEN_VEXT_VV(vwaddu_wv_h, 2, 4) 850 GEN_VEXT_VV(vwaddu_wv_w, 4, 8) 851 GEN_VEXT_VV(vwsubu_wv_b, 1, 2) 852 GEN_VEXT_VV(vwsubu_wv_h, 2, 4) 853 GEN_VEXT_VV(vwsubu_wv_w, 4, 8) 854 GEN_VEXT_VV(vwadd_wv_b, 1, 2) 855 GEN_VEXT_VV(vwadd_wv_h, 2, 4) 856 GEN_VEXT_VV(vwadd_wv_w, 4, 8) 857 GEN_VEXT_VV(vwsub_wv_b, 1, 2) 858 GEN_VEXT_VV(vwsub_wv_h, 2, 4) 859 GEN_VEXT_VV(vwsub_wv_w, 4, 8) 860 861 RVVCALL(OPIVX2, vwaddu_vx_b, WOP_UUU_B, H2, H1, DO_ADD) 862 RVVCALL(OPIVX2, vwaddu_vx_h, WOP_UUU_H, H4, H2, DO_ADD) 863 RVVCALL(OPIVX2, vwaddu_vx_w, WOP_UUU_W, H8, H4, DO_ADD) 864 RVVCALL(OPIVX2, vwsubu_vx_b, WOP_UUU_B, H2, H1, DO_SUB) 865 RVVCALL(OPIVX2, vwsubu_vx_h, WOP_UUU_H, H4, H2, DO_SUB) 866 RVVCALL(OPIVX2, vwsubu_vx_w, WOP_UUU_W, H8, H4, DO_SUB) 867 RVVCALL(OPIVX2, vwadd_vx_b, WOP_SSS_B, H2, H1, DO_ADD) 868 RVVCALL(OPIVX2, vwadd_vx_h, WOP_SSS_H, H4, H2, DO_ADD) 869 RVVCALL(OPIVX2, vwadd_vx_w, WOP_SSS_W, H8, H4, DO_ADD) 870 RVVCALL(OPIVX2, vwsub_vx_b, WOP_SSS_B, H2, H1, DO_SUB) 871 RVVCALL(OPIVX2, vwsub_vx_h, WOP_SSS_H, H4, H2, DO_SUB) 872 RVVCALL(OPIVX2, vwsub_vx_w, WOP_SSS_W, H8, H4, DO_SUB) 873 RVVCALL(OPIVX2, vwaddu_wx_b, WOP_WUUU_B, H2, H1, DO_ADD) 874 RVVCALL(OPIVX2, vwaddu_wx_h, WOP_WUUU_H, H4, H2, DO_ADD) 875 RVVCALL(OPIVX2, vwaddu_wx_w, WOP_WUUU_W, H8, H4, DO_ADD) 876 RVVCALL(OPIVX2, vwsubu_wx_b, WOP_WUUU_B, H2, H1, DO_SUB) 877 RVVCALL(OPIVX2, vwsubu_wx_h, WOP_WUUU_H, H4, H2, DO_SUB) 878 RVVCALL(OPIVX2, vwsubu_wx_w, WOP_WUUU_W, H8, H4, DO_SUB) 879 RVVCALL(OPIVX2, vwadd_wx_b, WOP_WSSS_B, H2, H1, DO_ADD) 880 RVVCALL(OPIVX2, vwadd_wx_h, WOP_WSSS_H, H4, H2, DO_ADD) 881 RVVCALL(OPIVX2, vwadd_wx_w, WOP_WSSS_W, H8, H4, DO_ADD) 882 RVVCALL(OPIVX2, vwsub_wx_b, WOP_WSSS_B, H2, H1, DO_SUB) 883 RVVCALL(OPIVX2, vwsub_wx_h, WOP_WSSS_H, H4, H2, DO_SUB) 884 RVVCALL(OPIVX2, vwsub_wx_w, WOP_WSSS_W, H8, H4, DO_SUB) 885 GEN_VEXT_VX(vwaddu_vx_b, 1, 2) 886 GEN_VEXT_VX(vwaddu_vx_h, 2, 4) 887 GEN_VEXT_VX(vwaddu_vx_w, 4, 8) 888 GEN_VEXT_VX(vwsubu_vx_b, 1, 2) 889 GEN_VEXT_VX(vwsubu_vx_h, 2, 4) 890 GEN_VEXT_VX(vwsubu_vx_w, 4, 8) 891 GEN_VEXT_VX(vwadd_vx_b, 1, 2) 892 GEN_VEXT_VX(vwadd_vx_h, 2, 4) 893 GEN_VEXT_VX(vwadd_vx_w, 4, 8) 894 GEN_VEXT_VX(vwsub_vx_b, 1, 2) 895 GEN_VEXT_VX(vwsub_vx_h, 2, 4) 896 GEN_VEXT_VX(vwsub_vx_w, 4, 8) 897 GEN_VEXT_VX(vwaddu_wx_b, 1, 2) 898 GEN_VEXT_VX(vwaddu_wx_h, 2, 4) 899 GEN_VEXT_VX(vwaddu_wx_w, 4, 8) 900 GEN_VEXT_VX(vwsubu_wx_b, 1, 2) 901 GEN_VEXT_VX(vwsubu_wx_h, 2, 4) 902 GEN_VEXT_VX(vwsubu_wx_w, 4, 8) 903 GEN_VEXT_VX(vwadd_wx_b, 1, 2) 904 GEN_VEXT_VX(vwadd_wx_h, 2, 4) 905 GEN_VEXT_VX(vwadd_wx_w, 4, 8) 906 GEN_VEXT_VX(vwsub_wx_b, 1, 2) 907 GEN_VEXT_VX(vwsub_wx_h, 2, 4) 908 GEN_VEXT_VX(vwsub_wx_w, 4, 8) 909 910 /* Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions */ 911 #define DO_VADC(N, M, C) (N + M + C) 912 #define DO_VSBC(N, M, C) (N - M - C) 913 914 #define GEN_VEXT_VADC_VVM(NAME, ETYPE, H, DO_OP) \ 915 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 916 CPURISCVState *env, uint32_t desc) \ 917 { \ 918 uint32_t vl = env->vl; \ 919 uint32_t i; \ 920 \ 921 for (i = 0; i < vl; i++) { \ 922 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 923 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 924 uint8_t carry = vext_elem_mask(v0, i); \ 925 \ 926 *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \ 927 } \ 928 } 929 930 GEN_VEXT_VADC_VVM(vadc_vvm_b, uint8_t, H1, DO_VADC) 931 GEN_VEXT_VADC_VVM(vadc_vvm_h, uint16_t, H2, DO_VADC) 932 GEN_VEXT_VADC_VVM(vadc_vvm_w, uint32_t, H4, DO_VADC) 933 GEN_VEXT_VADC_VVM(vadc_vvm_d, uint64_t, H8, DO_VADC) 934 935 GEN_VEXT_VADC_VVM(vsbc_vvm_b, uint8_t, H1, DO_VSBC) 936 GEN_VEXT_VADC_VVM(vsbc_vvm_h, uint16_t, H2, DO_VSBC) 937 GEN_VEXT_VADC_VVM(vsbc_vvm_w, uint32_t, H4, DO_VSBC) 938 GEN_VEXT_VADC_VVM(vsbc_vvm_d, uint64_t, H8, DO_VSBC) 939 940 #define GEN_VEXT_VADC_VXM(NAME, ETYPE, H, DO_OP) \ 941 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 942 CPURISCVState *env, uint32_t desc) \ 943 { \ 944 uint32_t vl = env->vl; \ 945 uint32_t i; \ 946 \ 947 for (i = 0; i < vl; i++) { \ 948 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 949 uint8_t carry = vext_elem_mask(v0, i); \ 950 \ 951 *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\ 952 } \ 953 } 954 955 GEN_VEXT_VADC_VXM(vadc_vxm_b, uint8_t, H1, DO_VADC) 956 GEN_VEXT_VADC_VXM(vadc_vxm_h, uint16_t, H2, DO_VADC) 957 GEN_VEXT_VADC_VXM(vadc_vxm_w, uint32_t, H4, DO_VADC) 958 GEN_VEXT_VADC_VXM(vadc_vxm_d, uint64_t, H8, DO_VADC) 959 960 GEN_VEXT_VADC_VXM(vsbc_vxm_b, uint8_t, H1, DO_VSBC) 961 GEN_VEXT_VADC_VXM(vsbc_vxm_h, uint16_t, H2, DO_VSBC) 962 GEN_VEXT_VADC_VXM(vsbc_vxm_w, uint32_t, H4, DO_VSBC) 963 GEN_VEXT_VADC_VXM(vsbc_vxm_d, uint64_t, H8, DO_VSBC) 964 965 #define DO_MADC(N, M, C) (C ? (__typeof(N))(N + M + 1) <= N : \ 966 (__typeof(N))(N + M) < N) 967 #define DO_MSBC(N, M, C) (C ? N <= M : N < M) 968 969 #define GEN_VEXT_VMADC_VVM(NAME, ETYPE, H, DO_OP) \ 970 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 971 CPURISCVState *env, uint32_t desc) \ 972 { \ 973 uint32_t vl = env->vl; \ 974 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 975 uint32_t i; \ 976 \ 977 for (i = 0; i < vl; i++) { \ 978 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 979 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 980 uint8_t carry = vext_elem_mask(v0, i); \ 981 \ 982 vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \ 983 } \ 984 for (; i < vlmax; i++) { \ 985 vext_set_elem_mask(vd, i, 0); \ 986 } \ 987 } 988 989 GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC) 990 GEN_VEXT_VMADC_VVM(vmadc_vvm_h, uint16_t, H2, DO_MADC) 991 GEN_VEXT_VMADC_VVM(vmadc_vvm_w, uint32_t, H4, DO_MADC) 992 GEN_VEXT_VMADC_VVM(vmadc_vvm_d, uint64_t, H8, DO_MADC) 993 994 GEN_VEXT_VMADC_VVM(vmsbc_vvm_b, uint8_t, H1, DO_MSBC) 995 GEN_VEXT_VMADC_VVM(vmsbc_vvm_h, uint16_t, H2, DO_MSBC) 996 GEN_VEXT_VMADC_VVM(vmsbc_vvm_w, uint32_t, H4, DO_MSBC) 997 GEN_VEXT_VMADC_VVM(vmsbc_vvm_d, uint64_t, H8, DO_MSBC) 998 999 #define GEN_VEXT_VMADC_VXM(NAME, ETYPE, H, DO_OP) \ 1000 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 1001 void *vs2, CPURISCVState *env, uint32_t desc) \ 1002 { \ 1003 uint32_t vl = env->vl; \ 1004 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1005 uint32_t i; \ 1006 \ 1007 for (i = 0; i < vl; i++) { \ 1008 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1009 uint8_t carry = vext_elem_mask(v0, i); \ 1010 \ 1011 vext_set_elem_mask(vd, i, \ 1012 DO_OP(s2, (ETYPE)(target_long)s1, carry)); \ 1013 } \ 1014 for (; i < vlmax; i++) { \ 1015 vext_set_elem_mask(vd, i, 0); \ 1016 } \ 1017 } 1018 1019 GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC) 1020 GEN_VEXT_VMADC_VXM(vmadc_vxm_h, uint16_t, H2, DO_MADC) 1021 GEN_VEXT_VMADC_VXM(vmadc_vxm_w, uint32_t, H4, DO_MADC) 1022 GEN_VEXT_VMADC_VXM(vmadc_vxm_d, uint64_t, H8, DO_MADC) 1023 1024 GEN_VEXT_VMADC_VXM(vmsbc_vxm_b, uint8_t, H1, DO_MSBC) 1025 GEN_VEXT_VMADC_VXM(vmsbc_vxm_h, uint16_t, H2, DO_MSBC) 1026 GEN_VEXT_VMADC_VXM(vmsbc_vxm_w, uint32_t, H4, DO_MSBC) 1027 GEN_VEXT_VMADC_VXM(vmsbc_vxm_d, uint64_t, H8, DO_MSBC) 1028 1029 /* Vector Bitwise Logical Instructions */ 1030 RVVCALL(OPIVV2, vand_vv_b, OP_SSS_B, H1, H1, H1, DO_AND) 1031 RVVCALL(OPIVV2, vand_vv_h, OP_SSS_H, H2, H2, H2, DO_AND) 1032 RVVCALL(OPIVV2, vand_vv_w, OP_SSS_W, H4, H4, H4, DO_AND) 1033 RVVCALL(OPIVV2, vand_vv_d, OP_SSS_D, H8, H8, H8, DO_AND) 1034 RVVCALL(OPIVV2, vor_vv_b, OP_SSS_B, H1, H1, H1, DO_OR) 1035 RVVCALL(OPIVV2, vor_vv_h, OP_SSS_H, H2, H2, H2, DO_OR) 1036 RVVCALL(OPIVV2, vor_vv_w, OP_SSS_W, H4, H4, H4, DO_OR) 1037 RVVCALL(OPIVV2, vor_vv_d, OP_SSS_D, H8, H8, H8, DO_OR) 1038 RVVCALL(OPIVV2, vxor_vv_b, OP_SSS_B, H1, H1, H1, DO_XOR) 1039 RVVCALL(OPIVV2, vxor_vv_h, OP_SSS_H, H2, H2, H2, DO_XOR) 1040 RVVCALL(OPIVV2, vxor_vv_w, OP_SSS_W, H4, H4, H4, DO_XOR) 1041 RVVCALL(OPIVV2, vxor_vv_d, OP_SSS_D, H8, H8, H8, DO_XOR) 1042 GEN_VEXT_VV(vand_vv_b, 1, 1) 1043 GEN_VEXT_VV(vand_vv_h, 2, 2) 1044 GEN_VEXT_VV(vand_vv_w, 4, 4) 1045 GEN_VEXT_VV(vand_vv_d, 8, 8) 1046 GEN_VEXT_VV(vor_vv_b, 1, 1) 1047 GEN_VEXT_VV(vor_vv_h, 2, 2) 1048 GEN_VEXT_VV(vor_vv_w, 4, 4) 1049 GEN_VEXT_VV(vor_vv_d, 8, 8) 1050 GEN_VEXT_VV(vxor_vv_b, 1, 1) 1051 GEN_VEXT_VV(vxor_vv_h, 2, 2) 1052 GEN_VEXT_VV(vxor_vv_w, 4, 4) 1053 GEN_VEXT_VV(vxor_vv_d, 8, 8) 1054 1055 RVVCALL(OPIVX2, vand_vx_b, OP_SSS_B, H1, H1, DO_AND) 1056 RVVCALL(OPIVX2, vand_vx_h, OP_SSS_H, H2, H2, DO_AND) 1057 RVVCALL(OPIVX2, vand_vx_w, OP_SSS_W, H4, H4, DO_AND) 1058 RVVCALL(OPIVX2, vand_vx_d, OP_SSS_D, H8, H8, DO_AND) 1059 RVVCALL(OPIVX2, vor_vx_b, OP_SSS_B, H1, H1, DO_OR) 1060 RVVCALL(OPIVX2, vor_vx_h, OP_SSS_H, H2, H2, DO_OR) 1061 RVVCALL(OPIVX2, vor_vx_w, OP_SSS_W, H4, H4, DO_OR) 1062 RVVCALL(OPIVX2, vor_vx_d, OP_SSS_D, H8, H8, DO_OR) 1063 RVVCALL(OPIVX2, vxor_vx_b, OP_SSS_B, H1, H1, DO_XOR) 1064 RVVCALL(OPIVX2, vxor_vx_h, OP_SSS_H, H2, H2, DO_XOR) 1065 RVVCALL(OPIVX2, vxor_vx_w, OP_SSS_W, H4, H4, DO_XOR) 1066 RVVCALL(OPIVX2, vxor_vx_d, OP_SSS_D, H8, H8, DO_XOR) 1067 GEN_VEXT_VX(vand_vx_b, 1, 1) 1068 GEN_VEXT_VX(vand_vx_h, 2, 2) 1069 GEN_VEXT_VX(vand_vx_w, 4, 4) 1070 GEN_VEXT_VX(vand_vx_d, 8, 8) 1071 GEN_VEXT_VX(vor_vx_b, 1, 1) 1072 GEN_VEXT_VX(vor_vx_h, 2, 2) 1073 GEN_VEXT_VX(vor_vx_w, 4, 4) 1074 GEN_VEXT_VX(vor_vx_d, 8, 8) 1075 GEN_VEXT_VX(vxor_vx_b, 1, 1) 1076 GEN_VEXT_VX(vxor_vx_h, 2, 2) 1077 GEN_VEXT_VX(vxor_vx_w, 4, 4) 1078 GEN_VEXT_VX(vxor_vx_d, 8, 8) 1079 1080 /* Vector Single-Width Bit Shift Instructions */ 1081 #define DO_SLL(N, M) (N << (M)) 1082 #define DO_SRL(N, M) (N >> (M)) 1083 1084 /* generate the helpers for shift instructions with two vector operators */ 1085 #define GEN_VEXT_SHIFT_VV(NAME, TS1, TS2, HS1, HS2, OP, MASK) \ 1086 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 1087 void *vs2, CPURISCVState *env, uint32_t desc) \ 1088 { \ 1089 uint32_t vm = vext_vm(desc); \ 1090 uint32_t vl = env->vl; \ 1091 uint32_t i; \ 1092 \ 1093 for (i = 0; i < vl; i++) { \ 1094 if (!vm && !vext_elem_mask(v0, i)) { \ 1095 continue; \ 1096 } \ 1097 TS1 s1 = *((TS1 *)vs1 + HS1(i)); \ 1098 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 1099 *((TS1 *)vd + HS1(i)) = OP(s2, s1 & MASK); \ 1100 } \ 1101 } 1102 1103 GEN_VEXT_SHIFT_VV(vsll_vv_b, uint8_t, uint8_t, H1, H1, DO_SLL, 0x7) 1104 GEN_VEXT_SHIFT_VV(vsll_vv_h, uint16_t, uint16_t, H2, H2, DO_SLL, 0xf) 1105 GEN_VEXT_SHIFT_VV(vsll_vv_w, uint32_t, uint32_t, H4, H4, DO_SLL, 0x1f) 1106 GEN_VEXT_SHIFT_VV(vsll_vv_d, uint64_t, uint64_t, H8, H8, DO_SLL, 0x3f) 1107 1108 GEN_VEXT_SHIFT_VV(vsrl_vv_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) 1109 GEN_VEXT_SHIFT_VV(vsrl_vv_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) 1110 GEN_VEXT_SHIFT_VV(vsrl_vv_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) 1111 GEN_VEXT_SHIFT_VV(vsrl_vv_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) 1112 1113 GEN_VEXT_SHIFT_VV(vsra_vv_b, uint8_t, int8_t, H1, H1, DO_SRL, 0x7) 1114 GEN_VEXT_SHIFT_VV(vsra_vv_h, uint16_t, int16_t, H2, H2, DO_SRL, 0xf) 1115 GEN_VEXT_SHIFT_VV(vsra_vv_w, uint32_t, int32_t, H4, H4, DO_SRL, 0x1f) 1116 GEN_VEXT_SHIFT_VV(vsra_vv_d, uint64_t, int64_t, H8, H8, DO_SRL, 0x3f) 1117 1118 /* generate the helpers for shift instructions with one vector and one scalar */ 1119 #define GEN_VEXT_SHIFT_VX(NAME, TD, TS2, HD, HS2, OP, MASK) \ 1120 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 1121 void *vs2, CPURISCVState *env, uint32_t desc) \ 1122 { \ 1123 uint32_t vm = vext_vm(desc); \ 1124 uint32_t vl = env->vl; \ 1125 uint32_t i; \ 1126 \ 1127 for (i = 0; i < vl; i++) { \ 1128 if (!vm && !vext_elem_mask(v0, i)) { \ 1129 continue; \ 1130 } \ 1131 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 1132 *((TD *)vd + HD(i)) = OP(s2, s1 & MASK); \ 1133 } \ 1134 } 1135 1136 GEN_VEXT_SHIFT_VX(vsll_vx_b, uint8_t, int8_t, H1, H1, DO_SLL, 0x7) 1137 GEN_VEXT_SHIFT_VX(vsll_vx_h, uint16_t, int16_t, H2, H2, DO_SLL, 0xf) 1138 GEN_VEXT_SHIFT_VX(vsll_vx_w, uint32_t, int32_t, H4, H4, DO_SLL, 0x1f) 1139 GEN_VEXT_SHIFT_VX(vsll_vx_d, uint64_t, int64_t, H8, H8, DO_SLL, 0x3f) 1140 1141 GEN_VEXT_SHIFT_VX(vsrl_vx_b, uint8_t, uint8_t, H1, H1, DO_SRL, 0x7) 1142 GEN_VEXT_SHIFT_VX(vsrl_vx_h, uint16_t, uint16_t, H2, H2, DO_SRL, 0xf) 1143 GEN_VEXT_SHIFT_VX(vsrl_vx_w, uint32_t, uint32_t, H4, H4, DO_SRL, 0x1f) 1144 GEN_VEXT_SHIFT_VX(vsrl_vx_d, uint64_t, uint64_t, H8, H8, DO_SRL, 0x3f) 1145 1146 GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7) 1147 GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf) 1148 GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f) 1149 GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f) 1150 1151 /* Vector Narrowing Integer Right Shift Instructions */ 1152 GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) 1153 GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) 1154 GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) 1155 GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf) 1156 GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f) 1157 GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f) 1158 GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf) 1159 GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f) 1160 GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f) 1161 GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf) 1162 GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f) 1163 GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f) 1164 1165 /* Vector Integer Comparison Instructions */ 1166 #define DO_MSEQ(N, M) (N == M) 1167 #define DO_MSNE(N, M) (N != M) 1168 #define DO_MSLT(N, M) (N < M) 1169 #define DO_MSLE(N, M) (N <= M) 1170 #define DO_MSGT(N, M) (N > M) 1171 1172 #define GEN_VEXT_CMP_VV(NAME, ETYPE, H, DO_OP) \ 1173 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1174 CPURISCVState *env, uint32_t desc) \ 1175 { \ 1176 uint32_t vm = vext_vm(desc); \ 1177 uint32_t vl = env->vl; \ 1178 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1179 uint32_t i; \ 1180 \ 1181 for (i = 0; i < vl; i++) { \ 1182 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 1183 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1184 if (!vm && !vext_elem_mask(v0, i)) { \ 1185 continue; \ 1186 } \ 1187 vext_set_elem_mask(vd, i, DO_OP(s2, s1)); \ 1188 } \ 1189 for (; i < vlmax; i++) { \ 1190 vext_set_elem_mask(vd, i, 0); \ 1191 } \ 1192 } 1193 1194 GEN_VEXT_CMP_VV(vmseq_vv_b, uint8_t, H1, DO_MSEQ) 1195 GEN_VEXT_CMP_VV(vmseq_vv_h, uint16_t, H2, DO_MSEQ) 1196 GEN_VEXT_CMP_VV(vmseq_vv_w, uint32_t, H4, DO_MSEQ) 1197 GEN_VEXT_CMP_VV(vmseq_vv_d, uint64_t, H8, DO_MSEQ) 1198 1199 GEN_VEXT_CMP_VV(vmsne_vv_b, uint8_t, H1, DO_MSNE) 1200 GEN_VEXT_CMP_VV(vmsne_vv_h, uint16_t, H2, DO_MSNE) 1201 GEN_VEXT_CMP_VV(vmsne_vv_w, uint32_t, H4, DO_MSNE) 1202 GEN_VEXT_CMP_VV(vmsne_vv_d, uint64_t, H8, DO_MSNE) 1203 1204 GEN_VEXT_CMP_VV(vmsltu_vv_b, uint8_t, H1, DO_MSLT) 1205 GEN_VEXT_CMP_VV(vmsltu_vv_h, uint16_t, H2, DO_MSLT) 1206 GEN_VEXT_CMP_VV(vmsltu_vv_w, uint32_t, H4, DO_MSLT) 1207 GEN_VEXT_CMP_VV(vmsltu_vv_d, uint64_t, H8, DO_MSLT) 1208 1209 GEN_VEXT_CMP_VV(vmslt_vv_b, int8_t, H1, DO_MSLT) 1210 GEN_VEXT_CMP_VV(vmslt_vv_h, int16_t, H2, DO_MSLT) 1211 GEN_VEXT_CMP_VV(vmslt_vv_w, int32_t, H4, DO_MSLT) 1212 GEN_VEXT_CMP_VV(vmslt_vv_d, int64_t, H8, DO_MSLT) 1213 1214 GEN_VEXT_CMP_VV(vmsleu_vv_b, uint8_t, H1, DO_MSLE) 1215 GEN_VEXT_CMP_VV(vmsleu_vv_h, uint16_t, H2, DO_MSLE) 1216 GEN_VEXT_CMP_VV(vmsleu_vv_w, uint32_t, H4, DO_MSLE) 1217 GEN_VEXT_CMP_VV(vmsleu_vv_d, uint64_t, H8, DO_MSLE) 1218 1219 GEN_VEXT_CMP_VV(vmsle_vv_b, int8_t, H1, DO_MSLE) 1220 GEN_VEXT_CMP_VV(vmsle_vv_h, int16_t, H2, DO_MSLE) 1221 GEN_VEXT_CMP_VV(vmsle_vv_w, int32_t, H4, DO_MSLE) 1222 GEN_VEXT_CMP_VV(vmsle_vv_d, int64_t, H8, DO_MSLE) 1223 1224 #define GEN_VEXT_CMP_VX(NAME, ETYPE, H, DO_OP) \ 1225 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 1226 CPURISCVState *env, uint32_t desc) \ 1227 { \ 1228 uint32_t vm = vext_vm(desc); \ 1229 uint32_t vl = env->vl; \ 1230 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 1231 uint32_t i; \ 1232 \ 1233 for (i = 0; i < vl; i++) { \ 1234 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1235 if (!vm && !vext_elem_mask(v0, i)) { \ 1236 continue; \ 1237 } \ 1238 vext_set_elem_mask(vd, i, \ 1239 DO_OP(s2, (ETYPE)(target_long)s1)); \ 1240 } \ 1241 for (; i < vlmax; i++) { \ 1242 vext_set_elem_mask(vd, i, 0); \ 1243 } \ 1244 } 1245 1246 GEN_VEXT_CMP_VX(vmseq_vx_b, uint8_t, H1, DO_MSEQ) 1247 GEN_VEXT_CMP_VX(vmseq_vx_h, uint16_t, H2, DO_MSEQ) 1248 GEN_VEXT_CMP_VX(vmseq_vx_w, uint32_t, H4, DO_MSEQ) 1249 GEN_VEXT_CMP_VX(vmseq_vx_d, uint64_t, H8, DO_MSEQ) 1250 1251 GEN_VEXT_CMP_VX(vmsne_vx_b, uint8_t, H1, DO_MSNE) 1252 GEN_VEXT_CMP_VX(vmsne_vx_h, uint16_t, H2, DO_MSNE) 1253 GEN_VEXT_CMP_VX(vmsne_vx_w, uint32_t, H4, DO_MSNE) 1254 GEN_VEXT_CMP_VX(vmsne_vx_d, uint64_t, H8, DO_MSNE) 1255 1256 GEN_VEXT_CMP_VX(vmsltu_vx_b, uint8_t, H1, DO_MSLT) 1257 GEN_VEXT_CMP_VX(vmsltu_vx_h, uint16_t, H2, DO_MSLT) 1258 GEN_VEXT_CMP_VX(vmsltu_vx_w, uint32_t, H4, DO_MSLT) 1259 GEN_VEXT_CMP_VX(vmsltu_vx_d, uint64_t, H8, DO_MSLT) 1260 1261 GEN_VEXT_CMP_VX(vmslt_vx_b, int8_t, H1, DO_MSLT) 1262 GEN_VEXT_CMP_VX(vmslt_vx_h, int16_t, H2, DO_MSLT) 1263 GEN_VEXT_CMP_VX(vmslt_vx_w, int32_t, H4, DO_MSLT) 1264 GEN_VEXT_CMP_VX(vmslt_vx_d, int64_t, H8, DO_MSLT) 1265 1266 GEN_VEXT_CMP_VX(vmsleu_vx_b, uint8_t, H1, DO_MSLE) 1267 GEN_VEXT_CMP_VX(vmsleu_vx_h, uint16_t, H2, DO_MSLE) 1268 GEN_VEXT_CMP_VX(vmsleu_vx_w, uint32_t, H4, DO_MSLE) 1269 GEN_VEXT_CMP_VX(vmsleu_vx_d, uint64_t, H8, DO_MSLE) 1270 1271 GEN_VEXT_CMP_VX(vmsle_vx_b, int8_t, H1, DO_MSLE) 1272 GEN_VEXT_CMP_VX(vmsle_vx_h, int16_t, H2, DO_MSLE) 1273 GEN_VEXT_CMP_VX(vmsle_vx_w, int32_t, H4, DO_MSLE) 1274 GEN_VEXT_CMP_VX(vmsle_vx_d, int64_t, H8, DO_MSLE) 1275 1276 GEN_VEXT_CMP_VX(vmsgtu_vx_b, uint8_t, H1, DO_MSGT) 1277 GEN_VEXT_CMP_VX(vmsgtu_vx_h, uint16_t, H2, DO_MSGT) 1278 GEN_VEXT_CMP_VX(vmsgtu_vx_w, uint32_t, H4, DO_MSGT) 1279 GEN_VEXT_CMP_VX(vmsgtu_vx_d, uint64_t, H8, DO_MSGT) 1280 1281 GEN_VEXT_CMP_VX(vmsgt_vx_b, int8_t, H1, DO_MSGT) 1282 GEN_VEXT_CMP_VX(vmsgt_vx_h, int16_t, H2, DO_MSGT) 1283 GEN_VEXT_CMP_VX(vmsgt_vx_w, int32_t, H4, DO_MSGT) 1284 GEN_VEXT_CMP_VX(vmsgt_vx_d, int64_t, H8, DO_MSGT) 1285 1286 /* Vector Integer Min/Max Instructions */ 1287 RVVCALL(OPIVV2, vminu_vv_b, OP_UUU_B, H1, H1, H1, DO_MIN) 1288 RVVCALL(OPIVV2, vminu_vv_h, OP_UUU_H, H2, H2, H2, DO_MIN) 1289 RVVCALL(OPIVV2, vminu_vv_w, OP_UUU_W, H4, H4, H4, DO_MIN) 1290 RVVCALL(OPIVV2, vminu_vv_d, OP_UUU_D, H8, H8, H8, DO_MIN) 1291 RVVCALL(OPIVV2, vmin_vv_b, OP_SSS_B, H1, H1, H1, DO_MIN) 1292 RVVCALL(OPIVV2, vmin_vv_h, OP_SSS_H, H2, H2, H2, DO_MIN) 1293 RVVCALL(OPIVV2, vmin_vv_w, OP_SSS_W, H4, H4, H4, DO_MIN) 1294 RVVCALL(OPIVV2, vmin_vv_d, OP_SSS_D, H8, H8, H8, DO_MIN) 1295 RVVCALL(OPIVV2, vmaxu_vv_b, OP_UUU_B, H1, H1, H1, DO_MAX) 1296 RVVCALL(OPIVV2, vmaxu_vv_h, OP_UUU_H, H2, H2, H2, DO_MAX) 1297 RVVCALL(OPIVV2, vmaxu_vv_w, OP_UUU_W, H4, H4, H4, DO_MAX) 1298 RVVCALL(OPIVV2, vmaxu_vv_d, OP_UUU_D, H8, H8, H8, DO_MAX) 1299 RVVCALL(OPIVV2, vmax_vv_b, OP_SSS_B, H1, H1, H1, DO_MAX) 1300 RVVCALL(OPIVV2, vmax_vv_h, OP_SSS_H, H2, H2, H2, DO_MAX) 1301 RVVCALL(OPIVV2, vmax_vv_w, OP_SSS_W, H4, H4, H4, DO_MAX) 1302 RVVCALL(OPIVV2, vmax_vv_d, OP_SSS_D, H8, H8, H8, DO_MAX) 1303 GEN_VEXT_VV(vminu_vv_b, 1, 1) 1304 GEN_VEXT_VV(vminu_vv_h, 2, 2) 1305 GEN_VEXT_VV(vminu_vv_w, 4, 4) 1306 GEN_VEXT_VV(vminu_vv_d, 8, 8) 1307 GEN_VEXT_VV(vmin_vv_b, 1, 1) 1308 GEN_VEXT_VV(vmin_vv_h, 2, 2) 1309 GEN_VEXT_VV(vmin_vv_w, 4, 4) 1310 GEN_VEXT_VV(vmin_vv_d, 8, 8) 1311 GEN_VEXT_VV(vmaxu_vv_b, 1, 1) 1312 GEN_VEXT_VV(vmaxu_vv_h, 2, 2) 1313 GEN_VEXT_VV(vmaxu_vv_w, 4, 4) 1314 GEN_VEXT_VV(vmaxu_vv_d, 8, 8) 1315 GEN_VEXT_VV(vmax_vv_b, 1, 1) 1316 GEN_VEXT_VV(vmax_vv_h, 2, 2) 1317 GEN_VEXT_VV(vmax_vv_w, 4, 4) 1318 GEN_VEXT_VV(vmax_vv_d, 8, 8) 1319 1320 RVVCALL(OPIVX2, vminu_vx_b, OP_UUU_B, H1, H1, DO_MIN) 1321 RVVCALL(OPIVX2, vminu_vx_h, OP_UUU_H, H2, H2, DO_MIN) 1322 RVVCALL(OPIVX2, vminu_vx_w, OP_UUU_W, H4, H4, DO_MIN) 1323 RVVCALL(OPIVX2, vminu_vx_d, OP_UUU_D, H8, H8, DO_MIN) 1324 RVVCALL(OPIVX2, vmin_vx_b, OP_SSS_B, H1, H1, DO_MIN) 1325 RVVCALL(OPIVX2, vmin_vx_h, OP_SSS_H, H2, H2, DO_MIN) 1326 RVVCALL(OPIVX2, vmin_vx_w, OP_SSS_W, H4, H4, DO_MIN) 1327 RVVCALL(OPIVX2, vmin_vx_d, OP_SSS_D, H8, H8, DO_MIN) 1328 RVVCALL(OPIVX2, vmaxu_vx_b, OP_UUU_B, H1, H1, DO_MAX) 1329 RVVCALL(OPIVX2, vmaxu_vx_h, OP_UUU_H, H2, H2, DO_MAX) 1330 RVVCALL(OPIVX2, vmaxu_vx_w, OP_UUU_W, H4, H4, DO_MAX) 1331 RVVCALL(OPIVX2, vmaxu_vx_d, OP_UUU_D, H8, H8, DO_MAX) 1332 RVVCALL(OPIVX2, vmax_vx_b, OP_SSS_B, H1, H1, DO_MAX) 1333 RVVCALL(OPIVX2, vmax_vx_h, OP_SSS_H, H2, H2, DO_MAX) 1334 RVVCALL(OPIVX2, vmax_vx_w, OP_SSS_W, H4, H4, DO_MAX) 1335 RVVCALL(OPIVX2, vmax_vx_d, OP_SSS_D, H8, H8, DO_MAX) 1336 GEN_VEXT_VX(vminu_vx_b, 1, 1) 1337 GEN_VEXT_VX(vminu_vx_h, 2, 2) 1338 GEN_VEXT_VX(vminu_vx_w, 4, 4) 1339 GEN_VEXT_VX(vminu_vx_d, 8, 8) 1340 GEN_VEXT_VX(vmin_vx_b, 1, 1) 1341 GEN_VEXT_VX(vmin_vx_h, 2, 2) 1342 GEN_VEXT_VX(vmin_vx_w, 4, 4) 1343 GEN_VEXT_VX(vmin_vx_d, 8, 8) 1344 GEN_VEXT_VX(vmaxu_vx_b, 1, 1) 1345 GEN_VEXT_VX(vmaxu_vx_h, 2, 2) 1346 GEN_VEXT_VX(vmaxu_vx_w, 4, 4) 1347 GEN_VEXT_VX(vmaxu_vx_d, 8, 8) 1348 GEN_VEXT_VX(vmax_vx_b, 1, 1) 1349 GEN_VEXT_VX(vmax_vx_h, 2, 2) 1350 GEN_VEXT_VX(vmax_vx_w, 4, 4) 1351 GEN_VEXT_VX(vmax_vx_d, 8, 8) 1352 1353 /* Vector Single-Width Integer Multiply Instructions */ 1354 #define DO_MUL(N, M) (N * M) 1355 RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL) 1356 RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL) 1357 RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL) 1358 RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL) 1359 GEN_VEXT_VV(vmul_vv_b, 1, 1) 1360 GEN_VEXT_VV(vmul_vv_h, 2, 2) 1361 GEN_VEXT_VV(vmul_vv_w, 4, 4) 1362 GEN_VEXT_VV(vmul_vv_d, 8, 8) 1363 1364 static int8_t do_mulh_b(int8_t s2, int8_t s1) 1365 { 1366 return (int16_t)s2 * (int16_t)s1 >> 8; 1367 } 1368 1369 static int16_t do_mulh_h(int16_t s2, int16_t s1) 1370 { 1371 return (int32_t)s2 * (int32_t)s1 >> 16; 1372 } 1373 1374 static int32_t do_mulh_w(int32_t s2, int32_t s1) 1375 { 1376 return (int64_t)s2 * (int64_t)s1 >> 32; 1377 } 1378 1379 static int64_t do_mulh_d(int64_t s2, int64_t s1) 1380 { 1381 uint64_t hi_64, lo_64; 1382 1383 muls64(&lo_64, &hi_64, s1, s2); 1384 return hi_64; 1385 } 1386 1387 static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1) 1388 { 1389 return (uint16_t)s2 * (uint16_t)s1 >> 8; 1390 } 1391 1392 static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1) 1393 { 1394 return (uint32_t)s2 * (uint32_t)s1 >> 16; 1395 } 1396 1397 static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1) 1398 { 1399 return (uint64_t)s2 * (uint64_t)s1 >> 32; 1400 } 1401 1402 static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1) 1403 { 1404 uint64_t hi_64, lo_64; 1405 1406 mulu64(&lo_64, &hi_64, s2, s1); 1407 return hi_64; 1408 } 1409 1410 static int8_t do_mulhsu_b(int8_t s2, uint8_t s1) 1411 { 1412 return (int16_t)s2 * (uint16_t)s1 >> 8; 1413 } 1414 1415 static int16_t do_mulhsu_h(int16_t s2, uint16_t s1) 1416 { 1417 return (int32_t)s2 * (uint32_t)s1 >> 16; 1418 } 1419 1420 static int32_t do_mulhsu_w(int32_t s2, uint32_t s1) 1421 { 1422 return (int64_t)s2 * (uint64_t)s1 >> 32; 1423 } 1424 1425 /* 1426 * Let A = signed operand, 1427 * B = unsigned operand 1428 * P = mulu64(A, B), unsigned product 1429 * 1430 * LET X = 2 ** 64 - A, 2's complement of A 1431 * SP = signed product 1432 * THEN 1433 * IF A < 0 1434 * SP = -X * B 1435 * = -(2 ** 64 - A) * B 1436 * = A * B - 2 ** 64 * B 1437 * = P - 2 ** 64 * B 1438 * ELSE 1439 * SP = P 1440 * THEN 1441 * HI_P -= (A < 0 ? B : 0) 1442 */ 1443 1444 static int64_t do_mulhsu_d(int64_t s2, uint64_t s1) 1445 { 1446 uint64_t hi_64, lo_64; 1447 1448 mulu64(&lo_64, &hi_64, s2, s1); 1449 1450 hi_64 -= s2 < 0 ? s1 : 0; 1451 return hi_64; 1452 } 1453 1454 RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b) 1455 RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h) 1456 RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w) 1457 RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d) 1458 RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b) 1459 RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h) 1460 RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w) 1461 RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d) 1462 RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b) 1463 RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h) 1464 RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w) 1465 RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d) 1466 GEN_VEXT_VV(vmulh_vv_b, 1, 1) 1467 GEN_VEXT_VV(vmulh_vv_h, 2, 2) 1468 GEN_VEXT_VV(vmulh_vv_w, 4, 4) 1469 GEN_VEXT_VV(vmulh_vv_d, 8, 8) 1470 GEN_VEXT_VV(vmulhu_vv_b, 1, 1) 1471 GEN_VEXT_VV(vmulhu_vv_h, 2, 2) 1472 GEN_VEXT_VV(vmulhu_vv_w, 4, 4) 1473 GEN_VEXT_VV(vmulhu_vv_d, 8, 8) 1474 GEN_VEXT_VV(vmulhsu_vv_b, 1, 1) 1475 GEN_VEXT_VV(vmulhsu_vv_h, 2, 2) 1476 GEN_VEXT_VV(vmulhsu_vv_w, 4, 4) 1477 GEN_VEXT_VV(vmulhsu_vv_d, 8, 8) 1478 1479 RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL) 1480 RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL) 1481 RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL) 1482 RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL) 1483 RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b) 1484 RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h) 1485 RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w) 1486 RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d) 1487 RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b) 1488 RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h) 1489 RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w) 1490 RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d) 1491 RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b) 1492 RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h) 1493 RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w) 1494 RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d) 1495 GEN_VEXT_VX(vmul_vx_b, 1, 1) 1496 GEN_VEXT_VX(vmul_vx_h, 2, 2) 1497 GEN_VEXT_VX(vmul_vx_w, 4, 4) 1498 GEN_VEXT_VX(vmul_vx_d, 8, 8) 1499 GEN_VEXT_VX(vmulh_vx_b, 1, 1) 1500 GEN_VEXT_VX(vmulh_vx_h, 2, 2) 1501 GEN_VEXT_VX(vmulh_vx_w, 4, 4) 1502 GEN_VEXT_VX(vmulh_vx_d, 8, 8) 1503 GEN_VEXT_VX(vmulhu_vx_b, 1, 1) 1504 GEN_VEXT_VX(vmulhu_vx_h, 2, 2) 1505 GEN_VEXT_VX(vmulhu_vx_w, 4, 4) 1506 GEN_VEXT_VX(vmulhu_vx_d, 8, 8) 1507 GEN_VEXT_VX(vmulhsu_vx_b, 1, 1) 1508 GEN_VEXT_VX(vmulhsu_vx_h, 2, 2) 1509 GEN_VEXT_VX(vmulhsu_vx_w, 4, 4) 1510 GEN_VEXT_VX(vmulhsu_vx_d, 8, 8) 1511 1512 /* Vector Integer Divide Instructions */ 1513 #define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M) 1514 #define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M) 1515 #define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\ 1516 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M) 1517 #define DO_REM(N, M) (unlikely(M == 0) ? N :\ 1518 unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M) 1519 1520 RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU) 1521 RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU) 1522 RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU) 1523 RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU) 1524 RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV) 1525 RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV) 1526 RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV) 1527 RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV) 1528 RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU) 1529 RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU) 1530 RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU) 1531 RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU) 1532 RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM) 1533 RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM) 1534 RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM) 1535 RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM) 1536 GEN_VEXT_VV(vdivu_vv_b, 1, 1) 1537 GEN_VEXT_VV(vdivu_vv_h, 2, 2) 1538 GEN_VEXT_VV(vdivu_vv_w, 4, 4) 1539 GEN_VEXT_VV(vdivu_vv_d, 8, 8) 1540 GEN_VEXT_VV(vdiv_vv_b, 1, 1) 1541 GEN_VEXT_VV(vdiv_vv_h, 2, 2) 1542 GEN_VEXT_VV(vdiv_vv_w, 4, 4) 1543 GEN_VEXT_VV(vdiv_vv_d, 8, 8) 1544 GEN_VEXT_VV(vremu_vv_b, 1, 1) 1545 GEN_VEXT_VV(vremu_vv_h, 2, 2) 1546 GEN_VEXT_VV(vremu_vv_w, 4, 4) 1547 GEN_VEXT_VV(vremu_vv_d, 8, 8) 1548 GEN_VEXT_VV(vrem_vv_b, 1, 1) 1549 GEN_VEXT_VV(vrem_vv_h, 2, 2) 1550 GEN_VEXT_VV(vrem_vv_w, 4, 4) 1551 GEN_VEXT_VV(vrem_vv_d, 8, 8) 1552 1553 RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU) 1554 RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU) 1555 RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU) 1556 RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU) 1557 RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV) 1558 RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV) 1559 RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV) 1560 RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV) 1561 RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU) 1562 RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU) 1563 RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU) 1564 RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU) 1565 RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM) 1566 RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM) 1567 RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM) 1568 RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM) 1569 GEN_VEXT_VX(vdivu_vx_b, 1, 1) 1570 GEN_VEXT_VX(vdivu_vx_h, 2, 2) 1571 GEN_VEXT_VX(vdivu_vx_w, 4, 4) 1572 GEN_VEXT_VX(vdivu_vx_d, 8, 8) 1573 GEN_VEXT_VX(vdiv_vx_b, 1, 1) 1574 GEN_VEXT_VX(vdiv_vx_h, 2, 2) 1575 GEN_VEXT_VX(vdiv_vx_w, 4, 4) 1576 GEN_VEXT_VX(vdiv_vx_d, 8, 8) 1577 GEN_VEXT_VX(vremu_vx_b, 1, 1) 1578 GEN_VEXT_VX(vremu_vx_h, 2, 2) 1579 GEN_VEXT_VX(vremu_vx_w, 4, 4) 1580 GEN_VEXT_VX(vremu_vx_d, 8, 8) 1581 GEN_VEXT_VX(vrem_vx_b, 1, 1) 1582 GEN_VEXT_VX(vrem_vx_h, 2, 2) 1583 GEN_VEXT_VX(vrem_vx_w, 4, 4) 1584 GEN_VEXT_VX(vrem_vx_d, 8, 8) 1585 1586 /* Vector Widening Integer Multiply Instructions */ 1587 RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL) 1588 RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL) 1589 RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL) 1590 RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL) 1591 RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL) 1592 RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL) 1593 RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL) 1594 RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL) 1595 RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL) 1596 GEN_VEXT_VV(vwmul_vv_b, 1, 2) 1597 GEN_VEXT_VV(vwmul_vv_h, 2, 4) 1598 GEN_VEXT_VV(vwmul_vv_w, 4, 8) 1599 GEN_VEXT_VV(vwmulu_vv_b, 1, 2) 1600 GEN_VEXT_VV(vwmulu_vv_h, 2, 4) 1601 GEN_VEXT_VV(vwmulu_vv_w, 4, 8) 1602 GEN_VEXT_VV(vwmulsu_vv_b, 1, 2) 1603 GEN_VEXT_VV(vwmulsu_vv_h, 2, 4) 1604 GEN_VEXT_VV(vwmulsu_vv_w, 4, 8) 1605 1606 RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL) 1607 RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL) 1608 RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL) 1609 RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL) 1610 RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL) 1611 RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL) 1612 RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL) 1613 RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL) 1614 RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL) 1615 GEN_VEXT_VX(vwmul_vx_b, 1, 2) 1616 GEN_VEXT_VX(vwmul_vx_h, 2, 4) 1617 GEN_VEXT_VX(vwmul_vx_w, 4, 8) 1618 GEN_VEXT_VX(vwmulu_vx_b, 1, 2) 1619 GEN_VEXT_VX(vwmulu_vx_h, 2, 4) 1620 GEN_VEXT_VX(vwmulu_vx_w, 4, 8) 1621 GEN_VEXT_VX(vwmulsu_vx_b, 1, 2) 1622 GEN_VEXT_VX(vwmulsu_vx_h, 2, 4) 1623 GEN_VEXT_VX(vwmulsu_vx_w, 4, 8) 1624 1625 /* Vector Single-Width Integer Multiply-Add Instructions */ 1626 #define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 1627 static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ 1628 { \ 1629 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 1630 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 1631 TD d = *((TD *)vd + HD(i)); \ 1632 *((TD *)vd + HD(i)) = OP(s2, s1, d); \ 1633 } 1634 1635 #define DO_MACC(N, M, D) (M * N + D) 1636 #define DO_NMSAC(N, M, D) (-(M * N) + D) 1637 #define DO_MADD(N, M, D) (M * D + N) 1638 #define DO_NMSUB(N, M, D) (-(M * D) + N) 1639 RVVCALL(OPIVV3, vmacc_vv_b, OP_SSS_B, H1, H1, H1, DO_MACC) 1640 RVVCALL(OPIVV3, vmacc_vv_h, OP_SSS_H, H2, H2, H2, DO_MACC) 1641 RVVCALL(OPIVV3, vmacc_vv_w, OP_SSS_W, H4, H4, H4, DO_MACC) 1642 RVVCALL(OPIVV3, vmacc_vv_d, OP_SSS_D, H8, H8, H8, DO_MACC) 1643 RVVCALL(OPIVV3, vnmsac_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSAC) 1644 RVVCALL(OPIVV3, vnmsac_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSAC) 1645 RVVCALL(OPIVV3, vnmsac_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSAC) 1646 RVVCALL(OPIVV3, vnmsac_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSAC) 1647 RVVCALL(OPIVV3, vmadd_vv_b, OP_SSS_B, H1, H1, H1, DO_MADD) 1648 RVVCALL(OPIVV3, vmadd_vv_h, OP_SSS_H, H2, H2, H2, DO_MADD) 1649 RVVCALL(OPIVV3, vmadd_vv_w, OP_SSS_W, H4, H4, H4, DO_MADD) 1650 RVVCALL(OPIVV3, vmadd_vv_d, OP_SSS_D, H8, H8, H8, DO_MADD) 1651 RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB) 1652 RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB) 1653 RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB) 1654 RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB) 1655 GEN_VEXT_VV(vmacc_vv_b, 1, 1) 1656 GEN_VEXT_VV(vmacc_vv_h, 2, 2) 1657 GEN_VEXT_VV(vmacc_vv_w, 4, 4) 1658 GEN_VEXT_VV(vmacc_vv_d, 8, 8) 1659 GEN_VEXT_VV(vnmsac_vv_b, 1, 1) 1660 GEN_VEXT_VV(vnmsac_vv_h, 2, 2) 1661 GEN_VEXT_VV(vnmsac_vv_w, 4, 4) 1662 GEN_VEXT_VV(vnmsac_vv_d, 8, 8) 1663 GEN_VEXT_VV(vmadd_vv_b, 1, 1) 1664 GEN_VEXT_VV(vmadd_vv_h, 2, 2) 1665 GEN_VEXT_VV(vmadd_vv_w, 4, 4) 1666 GEN_VEXT_VV(vmadd_vv_d, 8, 8) 1667 GEN_VEXT_VV(vnmsub_vv_b, 1, 1) 1668 GEN_VEXT_VV(vnmsub_vv_h, 2, 2) 1669 GEN_VEXT_VV(vnmsub_vv_w, 4, 4) 1670 GEN_VEXT_VV(vnmsub_vv_d, 8, 8) 1671 1672 #define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 1673 static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ 1674 { \ 1675 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 1676 TD d = *((TD *)vd + HD(i)); \ 1677 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \ 1678 } 1679 1680 RVVCALL(OPIVX3, vmacc_vx_b, OP_SSS_B, H1, H1, DO_MACC) 1681 RVVCALL(OPIVX3, vmacc_vx_h, OP_SSS_H, H2, H2, DO_MACC) 1682 RVVCALL(OPIVX3, vmacc_vx_w, OP_SSS_W, H4, H4, DO_MACC) 1683 RVVCALL(OPIVX3, vmacc_vx_d, OP_SSS_D, H8, H8, DO_MACC) 1684 RVVCALL(OPIVX3, vnmsac_vx_b, OP_SSS_B, H1, H1, DO_NMSAC) 1685 RVVCALL(OPIVX3, vnmsac_vx_h, OP_SSS_H, H2, H2, DO_NMSAC) 1686 RVVCALL(OPIVX3, vnmsac_vx_w, OP_SSS_W, H4, H4, DO_NMSAC) 1687 RVVCALL(OPIVX3, vnmsac_vx_d, OP_SSS_D, H8, H8, DO_NMSAC) 1688 RVVCALL(OPIVX3, vmadd_vx_b, OP_SSS_B, H1, H1, DO_MADD) 1689 RVVCALL(OPIVX3, vmadd_vx_h, OP_SSS_H, H2, H2, DO_MADD) 1690 RVVCALL(OPIVX3, vmadd_vx_w, OP_SSS_W, H4, H4, DO_MADD) 1691 RVVCALL(OPIVX3, vmadd_vx_d, OP_SSS_D, H8, H8, DO_MADD) 1692 RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB) 1693 RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB) 1694 RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB) 1695 RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB) 1696 GEN_VEXT_VX(vmacc_vx_b, 1, 1) 1697 GEN_VEXT_VX(vmacc_vx_h, 2, 2) 1698 GEN_VEXT_VX(vmacc_vx_w, 4, 4) 1699 GEN_VEXT_VX(vmacc_vx_d, 8, 8) 1700 GEN_VEXT_VX(vnmsac_vx_b, 1, 1) 1701 GEN_VEXT_VX(vnmsac_vx_h, 2, 2) 1702 GEN_VEXT_VX(vnmsac_vx_w, 4, 4) 1703 GEN_VEXT_VX(vnmsac_vx_d, 8, 8) 1704 GEN_VEXT_VX(vmadd_vx_b, 1, 1) 1705 GEN_VEXT_VX(vmadd_vx_h, 2, 2) 1706 GEN_VEXT_VX(vmadd_vx_w, 4, 4) 1707 GEN_VEXT_VX(vmadd_vx_d, 8, 8) 1708 GEN_VEXT_VX(vnmsub_vx_b, 1, 1) 1709 GEN_VEXT_VX(vnmsub_vx_h, 2, 2) 1710 GEN_VEXT_VX(vnmsub_vx_w, 4, 4) 1711 GEN_VEXT_VX(vnmsub_vx_d, 8, 8) 1712 1713 /* Vector Widening Integer Multiply-Add Instructions */ 1714 RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) 1715 RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC) 1716 RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC) 1717 RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC) 1718 RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC) 1719 RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) 1720 RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) 1721 RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) 1722 RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) 1723 GEN_VEXT_VV(vwmaccu_vv_b, 1, 2) 1724 GEN_VEXT_VV(vwmaccu_vv_h, 2, 4) 1725 GEN_VEXT_VV(vwmaccu_vv_w, 4, 8) 1726 GEN_VEXT_VV(vwmacc_vv_b, 1, 2) 1727 GEN_VEXT_VV(vwmacc_vv_h, 2, 4) 1728 GEN_VEXT_VV(vwmacc_vv_w, 4, 8) 1729 GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2) 1730 GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4) 1731 GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8) 1732 1733 RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC) 1734 RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC) 1735 RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC) 1736 RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC) 1737 RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC) 1738 RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC) 1739 RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC) 1740 RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC) 1741 RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC) 1742 RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC) 1743 RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC) 1744 RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC) 1745 GEN_VEXT_VX(vwmaccu_vx_b, 1, 2) 1746 GEN_VEXT_VX(vwmaccu_vx_h, 2, 4) 1747 GEN_VEXT_VX(vwmaccu_vx_w, 4, 8) 1748 GEN_VEXT_VX(vwmacc_vx_b, 1, 2) 1749 GEN_VEXT_VX(vwmacc_vx_h, 2, 4) 1750 GEN_VEXT_VX(vwmacc_vx_w, 4, 8) 1751 GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2) 1752 GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4) 1753 GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8) 1754 GEN_VEXT_VX(vwmaccus_vx_b, 1, 2) 1755 GEN_VEXT_VX(vwmaccus_vx_h, 2, 4) 1756 GEN_VEXT_VX(vwmaccus_vx_w, 4, 8) 1757 1758 /* Vector Integer Merge and Move Instructions */ 1759 #define GEN_VEXT_VMV_VV(NAME, ETYPE, H) \ 1760 void HELPER(NAME)(void *vd, void *vs1, CPURISCVState *env, \ 1761 uint32_t desc) \ 1762 { \ 1763 uint32_t vl = env->vl; \ 1764 uint32_t i; \ 1765 \ 1766 for (i = 0; i < vl; i++) { \ 1767 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 1768 *((ETYPE *)vd + H(i)) = s1; \ 1769 } \ 1770 } 1771 1772 GEN_VEXT_VMV_VV(vmv_v_v_b, int8_t, H1) 1773 GEN_VEXT_VMV_VV(vmv_v_v_h, int16_t, H2) 1774 GEN_VEXT_VMV_VV(vmv_v_v_w, int32_t, H4) 1775 GEN_VEXT_VMV_VV(vmv_v_v_d, int64_t, H8) 1776 1777 #define GEN_VEXT_VMV_VX(NAME, ETYPE, H) \ 1778 void HELPER(NAME)(void *vd, uint64_t s1, CPURISCVState *env, \ 1779 uint32_t desc) \ 1780 { \ 1781 uint32_t vl = env->vl; \ 1782 uint32_t i; \ 1783 \ 1784 for (i = 0; i < vl; i++) { \ 1785 *((ETYPE *)vd + H(i)) = (ETYPE)s1; \ 1786 } \ 1787 } 1788 1789 GEN_VEXT_VMV_VX(vmv_v_x_b, int8_t, H1) 1790 GEN_VEXT_VMV_VX(vmv_v_x_h, int16_t, H2) 1791 GEN_VEXT_VMV_VX(vmv_v_x_w, int32_t, H4) 1792 GEN_VEXT_VMV_VX(vmv_v_x_d, int64_t, H8) 1793 1794 #define GEN_VEXT_VMERGE_VV(NAME, ETYPE, H) \ 1795 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1796 CPURISCVState *env, uint32_t desc) \ 1797 { \ 1798 uint32_t vl = env->vl; \ 1799 uint32_t i; \ 1800 \ 1801 for (i = 0; i < vl; i++) { \ 1802 ETYPE *vt = (!vext_elem_mask(v0, i) ? vs2 : vs1); \ 1803 *((ETYPE *)vd + H(i)) = *(vt + H(i)); \ 1804 } \ 1805 } 1806 1807 GEN_VEXT_VMERGE_VV(vmerge_vvm_b, int8_t, H1) 1808 GEN_VEXT_VMERGE_VV(vmerge_vvm_h, int16_t, H2) 1809 GEN_VEXT_VMERGE_VV(vmerge_vvm_w, int32_t, H4) 1810 GEN_VEXT_VMERGE_VV(vmerge_vvm_d, int64_t, H8) 1811 1812 #define GEN_VEXT_VMERGE_VX(NAME, ETYPE, H) \ 1813 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 1814 void *vs2, CPURISCVState *env, uint32_t desc) \ 1815 { \ 1816 uint32_t vl = env->vl; \ 1817 uint32_t i; \ 1818 \ 1819 for (i = 0; i < vl; i++) { \ 1820 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 1821 ETYPE d = (!vext_elem_mask(v0, i) ? s2 : \ 1822 (ETYPE)(target_long)s1); \ 1823 *((ETYPE *)vd + H(i)) = d; \ 1824 } \ 1825 } 1826 1827 GEN_VEXT_VMERGE_VX(vmerge_vxm_b, int8_t, H1) 1828 GEN_VEXT_VMERGE_VX(vmerge_vxm_h, int16_t, H2) 1829 GEN_VEXT_VMERGE_VX(vmerge_vxm_w, int32_t, H4) 1830 GEN_VEXT_VMERGE_VX(vmerge_vxm_d, int64_t, H8) 1831 1832 /* 1833 *** Vector Fixed-Point Arithmetic Instructions 1834 */ 1835 1836 /* Vector Single-Width Saturating Add and Subtract */ 1837 1838 /* 1839 * As fixed point instructions probably have round mode and saturation, 1840 * define common macros for fixed point here. 1841 */ 1842 typedef void opivv2_rm_fn(void *vd, void *vs1, void *vs2, int i, 1843 CPURISCVState *env, int vxrm); 1844 1845 #define OPIVV2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 1846 static inline void \ 1847 do_##NAME(void *vd, void *vs1, void *vs2, int i, \ 1848 CPURISCVState *env, int vxrm) \ 1849 { \ 1850 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 1851 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 1852 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1); \ 1853 } 1854 1855 static inline void 1856 vext_vv_rm_1(void *vd, void *v0, void *vs1, void *vs2, 1857 CPURISCVState *env, 1858 uint32_t vl, uint32_t vm, int vxrm, 1859 opivv2_rm_fn *fn) 1860 { 1861 for (uint32_t i = 0; i < vl; i++) { 1862 if (!vm && !vext_elem_mask(v0, i)) { 1863 continue; 1864 } 1865 fn(vd, vs1, vs2, i, env, vxrm); 1866 } 1867 } 1868 1869 static inline void 1870 vext_vv_rm_2(void *vd, void *v0, void *vs1, void *vs2, 1871 CPURISCVState *env, 1872 uint32_t desc, uint32_t esz, uint32_t dsz, 1873 opivv2_rm_fn *fn) 1874 { 1875 uint32_t vm = vext_vm(desc); 1876 uint32_t vl = env->vl; 1877 1878 switch (env->vxrm) { 1879 case 0: /* rnu */ 1880 vext_vv_rm_1(vd, v0, vs1, vs2, 1881 env, vl, vm, 0, fn); 1882 break; 1883 case 1: /* rne */ 1884 vext_vv_rm_1(vd, v0, vs1, vs2, 1885 env, vl, vm, 1, fn); 1886 break; 1887 case 2: /* rdn */ 1888 vext_vv_rm_1(vd, v0, vs1, vs2, 1889 env, vl, vm, 2, fn); 1890 break; 1891 default: /* rod */ 1892 vext_vv_rm_1(vd, v0, vs1, vs2, 1893 env, vl, vm, 3, fn); 1894 break; 1895 } 1896 } 1897 1898 /* generate helpers for fixed point instructions with OPIVV format */ 1899 #define GEN_VEXT_VV_RM(NAME, ESZ, DSZ) \ 1900 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 1901 CPURISCVState *env, uint32_t desc) \ 1902 { \ 1903 vext_vv_rm_2(vd, v0, vs1, vs2, env, desc, ESZ, DSZ, \ 1904 do_##NAME); \ 1905 } 1906 1907 static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) 1908 { 1909 uint8_t res = a + b; 1910 if (res < a) { 1911 res = UINT8_MAX; 1912 env->vxsat = 0x1; 1913 } 1914 return res; 1915 } 1916 1917 static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, 1918 uint16_t b) 1919 { 1920 uint16_t res = a + b; 1921 if (res < a) { 1922 res = UINT16_MAX; 1923 env->vxsat = 0x1; 1924 } 1925 return res; 1926 } 1927 1928 static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, 1929 uint32_t b) 1930 { 1931 uint32_t res = a + b; 1932 if (res < a) { 1933 res = UINT32_MAX; 1934 env->vxsat = 0x1; 1935 } 1936 return res; 1937 } 1938 1939 static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a, 1940 uint64_t b) 1941 { 1942 uint64_t res = a + b; 1943 if (res < a) { 1944 res = UINT64_MAX; 1945 env->vxsat = 0x1; 1946 } 1947 return res; 1948 } 1949 1950 RVVCALL(OPIVV2_RM, vsaddu_vv_b, OP_UUU_B, H1, H1, H1, saddu8) 1951 RVVCALL(OPIVV2_RM, vsaddu_vv_h, OP_UUU_H, H2, H2, H2, saddu16) 1952 RVVCALL(OPIVV2_RM, vsaddu_vv_w, OP_UUU_W, H4, H4, H4, saddu32) 1953 RVVCALL(OPIVV2_RM, vsaddu_vv_d, OP_UUU_D, H8, H8, H8, saddu64) 1954 GEN_VEXT_VV_RM(vsaddu_vv_b, 1, 1) 1955 GEN_VEXT_VV_RM(vsaddu_vv_h, 2, 2) 1956 GEN_VEXT_VV_RM(vsaddu_vv_w, 4, 4) 1957 GEN_VEXT_VV_RM(vsaddu_vv_d, 8, 8) 1958 1959 typedef void opivx2_rm_fn(void *vd, target_long s1, void *vs2, int i, 1960 CPURISCVState *env, int vxrm); 1961 1962 #define OPIVX2_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 1963 static inline void \ 1964 do_##NAME(void *vd, target_long s1, void *vs2, int i, \ 1965 CPURISCVState *env, int vxrm) \ 1966 { \ 1967 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 1968 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1); \ 1969 } 1970 1971 static inline void 1972 vext_vx_rm_1(void *vd, void *v0, target_long s1, void *vs2, 1973 CPURISCVState *env, 1974 uint32_t vl, uint32_t vm, int vxrm, 1975 opivx2_rm_fn *fn) 1976 { 1977 for (uint32_t i = 0; i < vl; i++) { 1978 if (!vm && !vext_elem_mask(v0, i)) { 1979 continue; 1980 } 1981 fn(vd, s1, vs2, i, env, vxrm); 1982 } 1983 } 1984 1985 static inline void 1986 vext_vx_rm_2(void *vd, void *v0, target_long s1, void *vs2, 1987 CPURISCVState *env, 1988 uint32_t desc, uint32_t esz, uint32_t dsz, 1989 opivx2_rm_fn *fn) 1990 { 1991 uint32_t vm = vext_vm(desc); 1992 uint32_t vl = env->vl; 1993 1994 switch (env->vxrm) { 1995 case 0: /* rnu */ 1996 vext_vx_rm_1(vd, v0, s1, vs2, 1997 env, vl, vm, 0, fn); 1998 break; 1999 case 1: /* rne */ 2000 vext_vx_rm_1(vd, v0, s1, vs2, 2001 env, vl, vm, 1, fn); 2002 break; 2003 case 2: /* rdn */ 2004 vext_vx_rm_1(vd, v0, s1, vs2, 2005 env, vl, vm, 2, fn); 2006 break; 2007 default: /* rod */ 2008 vext_vx_rm_1(vd, v0, s1, vs2, 2009 env, vl, vm, 3, fn); 2010 break; 2011 } 2012 } 2013 2014 /* generate helpers for fixed point instructions with OPIVX format */ 2015 #define GEN_VEXT_VX_RM(NAME, ESZ, DSZ) \ 2016 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ 2017 void *vs2, CPURISCVState *env, uint32_t desc) \ 2018 { \ 2019 vext_vx_rm_2(vd, v0, s1, vs2, env, desc, ESZ, DSZ, \ 2020 do_##NAME); \ 2021 } 2022 2023 RVVCALL(OPIVX2_RM, vsaddu_vx_b, OP_UUU_B, H1, H1, saddu8) 2024 RVVCALL(OPIVX2_RM, vsaddu_vx_h, OP_UUU_H, H2, H2, saddu16) 2025 RVVCALL(OPIVX2_RM, vsaddu_vx_w, OP_UUU_W, H4, H4, saddu32) 2026 RVVCALL(OPIVX2_RM, vsaddu_vx_d, OP_UUU_D, H8, H8, saddu64) 2027 GEN_VEXT_VX_RM(vsaddu_vx_b, 1, 1) 2028 GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2) 2029 GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4) 2030 GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8) 2031 2032 static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) 2033 { 2034 int8_t res = a + b; 2035 if ((res ^ a) & (res ^ b) & INT8_MIN) { 2036 res = a > 0 ? INT8_MAX : INT8_MIN; 2037 env->vxsat = 0x1; 2038 } 2039 return res; 2040 } 2041 2042 static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) 2043 { 2044 int16_t res = a + b; 2045 if ((res ^ a) & (res ^ b) & INT16_MIN) { 2046 res = a > 0 ? INT16_MAX : INT16_MIN; 2047 env->vxsat = 0x1; 2048 } 2049 return res; 2050 } 2051 2052 static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2053 { 2054 int32_t res = a + b; 2055 if ((res ^ a) & (res ^ b) & INT32_MIN) { 2056 res = a > 0 ? INT32_MAX : INT32_MIN; 2057 env->vxsat = 0x1; 2058 } 2059 return res; 2060 } 2061 2062 static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2063 { 2064 int64_t res = a + b; 2065 if ((res ^ a) & (res ^ b) & INT64_MIN) { 2066 res = a > 0 ? INT64_MAX : INT64_MIN; 2067 env->vxsat = 0x1; 2068 } 2069 return res; 2070 } 2071 2072 RVVCALL(OPIVV2_RM, vsadd_vv_b, OP_SSS_B, H1, H1, H1, sadd8) 2073 RVVCALL(OPIVV2_RM, vsadd_vv_h, OP_SSS_H, H2, H2, H2, sadd16) 2074 RVVCALL(OPIVV2_RM, vsadd_vv_w, OP_SSS_W, H4, H4, H4, sadd32) 2075 RVVCALL(OPIVV2_RM, vsadd_vv_d, OP_SSS_D, H8, H8, H8, sadd64) 2076 GEN_VEXT_VV_RM(vsadd_vv_b, 1, 1) 2077 GEN_VEXT_VV_RM(vsadd_vv_h, 2, 2) 2078 GEN_VEXT_VV_RM(vsadd_vv_w, 4, 4) 2079 GEN_VEXT_VV_RM(vsadd_vv_d, 8, 8) 2080 2081 RVVCALL(OPIVX2_RM, vsadd_vx_b, OP_SSS_B, H1, H1, sadd8) 2082 RVVCALL(OPIVX2_RM, vsadd_vx_h, OP_SSS_H, H2, H2, sadd16) 2083 RVVCALL(OPIVX2_RM, vsadd_vx_w, OP_SSS_W, H4, H4, sadd32) 2084 RVVCALL(OPIVX2_RM, vsadd_vx_d, OP_SSS_D, H8, H8, sadd64) 2085 GEN_VEXT_VX_RM(vsadd_vx_b, 1, 1) 2086 GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2) 2087 GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4) 2088 GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8) 2089 2090 static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) 2091 { 2092 uint8_t res = a - b; 2093 if (res > a) { 2094 res = 0; 2095 env->vxsat = 0x1; 2096 } 2097 return res; 2098 } 2099 2100 static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, 2101 uint16_t b) 2102 { 2103 uint16_t res = a - b; 2104 if (res > a) { 2105 res = 0; 2106 env->vxsat = 0x1; 2107 } 2108 return res; 2109 } 2110 2111 static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, 2112 uint32_t b) 2113 { 2114 uint32_t res = a - b; 2115 if (res > a) { 2116 res = 0; 2117 env->vxsat = 0x1; 2118 } 2119 return res; 2120 } 2121 2122 static inline uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a, 2123 uint64_t b) 2124 { 2125 uint64_t res = a - b; 2126 if (res > a) { 2127 res = 0; 2128 env->vxsat = 0x1; 2129 } 2130 return res; 2131 } 2132 2133 RVVCALL(OPIVV2_RM, vssubu_vv_b, OP_UUU_B, H1, H1, H1, ssubu8) 2134 RVVCALL(OPIVV2_RM, vssubu_vv_h, OP_UUU_H, H2, H2, H2, ssubu16) 2135 RVVCALL(OPIVV2_RM, vssubu_vv_w, OP_UUU_W, H4, H4, H4, ssubu32) 2136 RVVCALL(OPIVV2_RM, vssubu_vv_d, OP_UUU_D, H8, H8, H8, ssubu64) 2137 GEN_VEXT_VV_RM(vssubu_vv_b, 1, 1) 2138 GEN_VEXT_VV_RM(vssubu_vv_h, 2, 2) 2139 GEN_VEXT_VV_RM(vssubu_vv_w, 4, 4) 2140 GEN_VEXT_VV_RM(vssubu_vv_d, 8, 8) 2141 2142 RVVCALL(OPIVX2_RM, vssubu_vx_b, OP_UUU_B, H1, H1, ssubu8) 2143 RVVCALL(OPIVX2_RM, vssubu_vx_h, OP_UUU_H, H2, H2, ssubu16) 2144 RVVCALL(OPIVX2_RM, vssubu_vx_w, OP_UUU_W, H4, H4, ssubu32) 2145 RVVCALL(OPIVX2_RM, vssubu_vx_d, OP_UUU_D, H8, H8, ssubu64) 2146 GEN_VEXT_VX_RM(vssubu_vx_b, 1, 1) 2147 GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2) 2148 GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4) 2149 GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8) 2150 2151 static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) 2152 { 2153 int8_t res = a - b; 2154 if ((res ^ a) & (a ^ b) & INT8_MIN) { 2155 res = a >= 0 ? INT8_MAX : INT8_MIN; 2156 env->vxsat = 0x1; 2157 } 2158 return res; 2159 } 2160 2161 static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) 2162 { 2163 int16_t res = a - b; 2164 if ((res ^ a) & (a ^ b) & INT16_MIN) { 2165 res = a >= 0 ? INT16_MAX : INT16_MIN; 2166 env->vxsat = 0x1; 2167 } 2168 return res; 2169 } 2170 2171 static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2172 { 2173 int32_t res = a - b; 2174 if ((res ^ a) & (a ^ b) & INT32_MIN) { 2175 res = a >= 0 ? INT32_MAX : INT32_MIN; 2176 env->vxsat = 0x1; 2177 } 2178 return res; 2179 } 2180 2181 static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2182 { 2183 int64_t res = a - b; 2184 if ((res ^ a) & (a ^ b) & INT64_MIN) { 2185 res = a >= 0 ? INT64_MAX : INT64_MIN; 2186 env->vxsat = 0x1; 2187 } 2188 return res; 2189 } 2190 2191 RVVCALL(OPIVV2_RM, vssub_vv_b, OP_SSS_B, H1, H1, H1, ssub8) 2192 RVVCALL(OPIVV2_RM, vssub_vv_h, OP_SSS_H, H2, H2, H2, ssub16) 2193 RVVCALL(OPIVV2_RM, vssub_vv_w, OP_SSS_W, H4, H4, H4, ssub32) 2194 RVVCALL(OPIVV2_RM, vssub_vv_d, OP_SSS_D, H8, H8, H8, ssub64) 2195 GEN_VEXT_VV_RM(vssub_vv_b, 1, 1) 2196 GEN_VEXT_VV_RM(vssub_vv_h, 2, 2) 2197 GEN_VEXT_VV_RM(vssub_vv_w, 4, 4) 2198 GEN_VEXT_VV_RM(vssub_vv_d, 8, 8) 2199 2200 RVVCALL(OPIVX2_RM, vssub_vx_b, OP_SSS_B, H1, H1, ssub8) 2201 RVVCALL(OPIVX2_RM, vssub_vx_h, OP_SSS_H, H2, H2, ssub16) 2202 RVVCALL(OPIVX2_RM, vssub_vx_w, OP_SSS_W, H4, H4, ssub32) 2203 RVVCALL(OPIVX2_RM, vssub_vx_d, OP_SSS_D, H8, H8, ssub64) 2204 GEN_VEXT_VX_RM(vssub_vx_b, 1, 1) 2205 GEN_VEXT_VX_RM(vssub_vx_h, 2, 2) 2206 GEN_VEXT_VX_RM(vssub_vx_w, 4, 4) 2207 GEN_VEXT_VX_RM(vssub_vx_d, 8, 8) 2208 2209 /* Vector Single-Width Averaging Add and Subtract */ 2210 static inline uint8_t get_round(int vxrm, uint64_t v, uint8_t shift) 2211 { 2212 uint8_t d = extract64(v, shift, 1); 2213 uint8_t d1; 2214 uint64_t D1, D2; 2215 2216 if (shift == 0 || shift > 64) { 2217 return 0; 2218 } 2219 2220 d1 = extract64(v, shift - 1, 1); 2221 D1 = extract64(v, 0, shift); 2222 if (vxrm == 0) { /* round-to-nearest-up (add +0.5 LSB) */ 2223 return d1; 2224 } else if (vxrm == 1) { /* round-to-nearest-even */ 2225 if (shift > 1) { 2226 D2 = extract64(v, 0, shift - 1); 2227 return d1 & ((D2 != 0) | d); 2228 } else { 2229 return d1 & d; 2230 } 2231 } else if (vxrm == 3) { /* round-to-odd (OR bits into LSB, aka "jam") */ 2232 return !d & (D1 != 0); 2233 } 2234 return 0; /* round-down (truncate) */ 2235 } 2236 2237 static inline int32_t aadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2238 { 2239 int64_t res = (int64_t)a + b; 2240 uint8_t round = get_round(vxrm, res, 1); 2241 2242 return (res >> 1) + round; 2243 } 2244 2245 static inline int64_t aadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2246 { 2247 int64_t res = a + b; 2248 uint8_t round = get_round(vxrm, res, 1); 2249 int64_t over = (res ^ a) & (res ^ b) & INT64_MIN; 2250 2251 /* With signed overflow, bit 64 is inverse of bit 63. */ 2252 return ((res >> 1) ^ over) + round; 2253 } 2254 2255 RVVCALL(OPIVV2_RM, vaadd_vv_b, OP_SSS_B, H1, H1, H1, aadd32) 2256 RVVCALL(OPIVV2_RM, vaadd_vv_h, OP_SSS_H, H2, H2, H2, aadd32) 2257 RVVCALL(OPIVV2_RM, vaadd_vv_w, OP_SSS_W, H4, H4, H4, aadd32) 2258 RVVCALL(OPIVV2_RM, vaadd_vv_d, OP_SSS_D, H8, H8, H8, aadd64) 2259 GEN_VEXT_VV_RM(vaadd_vv_b, 1, 1) 2260 GEN_VEXT_VV_RM(vaadd_vv_h, 2, 2) 2261 GEN_VEXT_VV_RM(vaadd_vv_w, 4, 4) 2262 GEN_VEXT_VV_RM(vaadd_vv_d, 8, 8) 2263 2264 RVVCALL(OPIVX2_RM, vaadd_vx_b, OP_SSS_B, H1, H1, aadd32) 2265 RVVCALL(OPIVX2_RM, vaadd_vx_h, OP_SSS_H, H2, H2, aadd32) 2266 RVVCALL(OPIVX2_RM, vaadd_vx_w, OP_SSS_W, H4, H4, aadd32) 2267 RVVCALL(OPIVX2_RM, vaadd_vx_d, OP_SSS_D, H8, H8, aadd64) 2268 GEN_VEXT_VX_RM(vaadd_vx_b, 1, 1) 2269 GEN_VEXT_VX_RM(vaadd_vx_h, 2, 2) 2270 GEN_VEXT_VX_RM(vaadd_vx_w, 4, 4) 2271 GEN_VEXT_VX_RM(vaadd_vx_d, 8, 8) 2272 2273 static inline int32_t asub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2274 { 2275 int64_t res = (int64_t)a - b; 2276 uint8_t round = get_round(vxrm, res, 1); 2277 2278 return (res >> 1) + round; 2279 } 2280 2281 static inline int64_t asub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2282 { 2283 int64_t res = (int64_t)a - b; 2284 uint8_t round = get_round(vxrm, res, 1); 2285 int64_t over = (res ^ a) & (a ^ b) & INT64_MIN; 2286 2287 /* With signed overflow, bit 64 is inverse of bit 63. */ 2288 return ((res >> 1) ^ over) + round; 2289 } 2290 2291 RVVCALL(OPIVV2_RM, vasub_vv_b, OP_SSS_B, H1, H1, H1, asub32) 2292 RVVCALL(OPIVV2_RM, vasub_vv_h, OP_SSS_H, H2, H2, H2, asub32) 2293 RVVCALL(OPIVV2_RM, vasub_vv_w, OP_SSS_W, H4, H4, H4, asub32) 2294 RVVCALL(OPIVV2_RM, vasub_vv_d, OP_SSS_D, H8, H8, H8, asub64) 2295 GEN_VEXT_VV_RM(vasub_vv_b, 1, 1) 2296 GEN_VEXT_VV_RM(vasub_vv_h, 2, 2) 2297 GEN_VEXT_VV_RM(vasub_vv_w, 4, 4) 2298 GEN_VEXT_VV_RM(vasub_vv_d, 8, 8) 2299 2300 RVVCALL(OPIVX2_RM, vasub_vx_b, OP_SSS_B, H1, H1, asub32) 2301 RVVCALL(OPIVX2_RM, vasub_vx_h, OP_SSS_H, H2, H2, asub32) 2302 RVVCALL(OPIVX2_RM, vasub_vx_w, OP_SSS_W, H4, H4, asub32) 2303 RVVCALL(OPIVX2_RM, vasub_vx_d, OP_SSS_D, H8, H8, asub64) 2304 GEN_VEXT_VX_RM(vasub_vx_b, 1, 1) 2305 GEN_VEXT_VX_RM(vasub_vx_h, 2, 2) 2306 GEN_VEXT_VX_RM(vasub_vx_w, 4, 4) 2307 GEN_VEXT_VX_RM(vasub_vx_d, 8, 8) 2308 2309 /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ 2310 static inline int8_t vsmul8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) 2311 { 2312 uint8_t round; 2313 int16_t res; 2314 2315 res = (int16_t)a * (int16_t)b; 2316 round = get_round(vxrm, res, 7); 2317 res = (res >> 7) + round; 2318 2319 if (res > INT8_MAX) { 2320 env->vxsat = 0x1; 2321 return INT8_MAX; 2322 } else if (res < INT8_MIN) { 2323 env->vxsat = 0x1; 2324 return INT8_MIN; 2325 } else { 2326 return res; 2327 } 2328 } 2329 2330 static int16_t vsmul16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) 2331 { 2332 uint8_t round; 2333 int32_t res; 2334 2335 res = (int32_t)a * (int32_t)b; 2336 round = get_round(vxrm, res, 15); 2337 res = (res >> 15) + round; 2338 2339 if (res > INT16_MAX) { 2340 env->vxsat = 0x1; 2341 return INT16_MAX; 2342 } else if (res < INT16_MIN) { 2343 env->vxsat = 0x1; 2344 return INT16_MIN; 2345 } else { 2346 return res; 2347 } 2348 } 2349 2350 static int32_t vsmul32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2351 { 2352 uint8_t round; 2353 int64_t res; 2354 2355 res = (int64_t)a * (int64_t)b; 2356 round = get_round(vxrm, res, 31); 2357 res = (res >> 31) + round; 2358 2359 if (res > INT32_MAX) { 2360 env->vxsat = 0x1; 2361 return INT32_MAX; 2362 } else if (res < INT32_MIN) { 2363 env->vxsat = 0x1; 2364 return INT32_MIN; 2365 } else { 2366 return res; 2367 } 2368 } 2369 2370 static int64_t vsmul64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2371 { 2372 uint8_t round; 2373 uint64_t hi_64, lo_64; 2374 int64_t res; 2375 2376 if (a == INT64_MIN && b == INT64_MIN) { 2377 env->vxsat = 1; 2378 return INT64_MAX; 2379 } 2380 2381 muls64(&lo_64, &hi_64, a, b); 2382 round = get_round(vxrm, lo_64, 63); 2383 /* 2384 * Cannot overflow, as there are always 2385 * 2 sign bits after multiply. 2386 */ 2387 res = (hi_64 << 1) | (lo_64 >> 63); 2388 if (round) { 2389 if (res == INT64_MAX) { 2390 env->vxsat = 1; 2391 } else { 2392 res += 1; 2393 } 2394 } 2395 return res; 2396 } 2397 2398 RVVCALL(OPIVV2_RM, vsmul_vv_b, OP_SSS_B, H1, H1, H1, vsmul8) 2399 RVVCALL(OPIVV2_RM, vsmul_vv_h, OP_SSS_H, H2, H2, H2, vsmul16) 2400 RVVCALL(OPIVV2_RM, vsmul_vv_w, OP_SSS_W, H4, H4, H4, vsmul32) 2401 RVVCALL(OPIVV2_RM, vsmul_vv_d, OP_SSS_D, H8, H8, H8, vsmul64) 2402 GEN_VEXT_VV_RM(vsmul_vv_b, 1, 1) 2403 GEN_VEXT_VV_RM(vsmul_vv_h, 2, 2) 2404 GEN_VEXT_VV_RM(vsmul_vv_w, 4, 4) 2405 GEN_VEXT_VV_RM(vsmul_vv_d, 8, 8) 2406 2407 RVVCALL(OPIVX2_RM, vsmul_vx_b, OP_SSS_B, H1, H1, vsmul8) 2408 RVVCALL(OPIVX2_RM, vsmul_vx_h, OP_SSS_H, H2, H2, vsmul16) 2409 RVVCALL(OPIVX2_RM, vsmul_vx_w, OP_SSS_W, H4, H4, vsmul32) 2410 RVVCALL(OPIVX2_RM, vsmul_vx_d, OP_SSS_D, H8, H8, vsmul64) 2411 GEN_VEXT_VX_RM(vsmul_vx_b, 1, 1) 2412 GEN_VEXT_VX_RM(vsmul_vx_h, 2, 2) 2413 GEN_VEXT_VX_RM(vsmul_vx_w, 4, 4) 2414 GEN_VEXT_VX_RM(vsmul_vx_d, 8, 8) 2415 2416 /* Vector Widening Saturating Scaled Multiply-Add */ 2417 static inline uint16_t 2418 vwsmaccu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b, 2419 uint16_t c) 2420 { 2421 uint8_t round; 2422 uint16_t res = (uint16_t)a * b; 2423 2424 round = get_round(vxrm, res, 4); 2425 res = (res >> 4) + round; 2426 return saddu16(env, vxrm, c, res); 2427 } 2428 2429 static inline uint32_t 2430 vwsmaccu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b, 2431 uint32_t c) 2432 { 2433 uint8_t round; 2434 uint32_t res = (uint32_t)a * b; 2435 2436 round = get_round(vxrm, res, 8); 2437 res = (res >> 8) + round; 2438 return saddu32(env, vxrm, c, res); 2439 } 2440 2441 static inline uint64_t 2442 vwsmaccu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b, 2443 uint64_t c) 2444 { 2445 uint8_t round; 2446 uint64_t res = (uint64_t)a * b; 2447 2448 round = get_round(vxrm, res, 16); 2449 res = (res >> 16) + round; 2450 return saddu64(env, vxrm, c, res); 2451 } 2452 2453 #define OPIVV3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 2454 static inline void \ 2455 do_##NAME(void *vd, void *vs1, void *vs2, int i, \ 2456 CPURISCVState *env, int vxrm) \ 2457 { \ 2458 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 2459 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 2460 TD d = *((TD *)vd + HD(i)); \ 2461 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, s1, d); \ 2462 } 2463 2464 RVVCALL(OPIVV3_RM, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) 2465 RVVCALL(OPIVV3_RM, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) 2466 RVVCALL(OPIVV3_RM, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) 2467 GEN_VEXT_VV_RM(vwsmaccu_vv_b, 1, 2) 2468 GEN_VEXT_VV_RM(vwsmaccu_vv_h, 2, 4) 2469 GEN_VEXT_VV_RM(vwsmaccu_vv_w, 4, 8) 2470 2471 #define OPIVX3_RM(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 2472 static inline void \ 2473 do_##NAME(void *vd, target_long s1, void *vs2, int i, \ 2474 CPURISCVState *env, int vxrm) \ 2475 { \ 2476 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 2477 TD d = *((TD *)vd + HD(i)); \ 2478 *((TD *)vd + HD(i)) = OP(env, vxrm, s2, (TX1)(T1)s1, d); \ 2479 } 2480 2481 RVVCALL(OPIVX3_RM, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) 2482 RVVCALL(OPIVX3_RM, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) 2483 RVVCALL(OPIVX3_RM, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) 2484 GEN_VEXT_VX_RM(vwsmaccu_vx_b, 1, 2) 2485 GEN_VEXT_VX_RM(vwsmaccu_vx_h, 2, 4) 2486 GEN_VEXT_VX_RM(vwsmaccu_vx_w, 4, 8) 2487 2488 static inline int16_t 2489 vwsmacc8(CPURISCVState *env, int vxrm, int8_t a, int8_t b, int16_t c) 2490 { 2491 uint8_t round; 2492 int16_t res = (int16_t)a * b; 2493 2494 round = get_round(vxrm, res, 4); 2495 res = (res >> 4) + round; 2496 return sadd16(env, vxrm, c, res); 2497 } 2498 2499 static inline int32_t 2500 vwsmacc16(CPURISCVState *env, int vxrm, int16_t a, int16_t b, int32_t c) 2501 { 2502 uint8_t round; 2503 int32_t res = (int32_t)a * b; 2504 2505 round = get_round(vxrm, res, 8); 2506 res = (res >> 8) + round; 2507 return sadd32(env, vxrm, c, res); 2508 2509 } 2510 2511 static inline int64_t 2512 vwsmacc32(CPURISCVState *env, int vxrm, int32_t a, int32_t b, int64_t c) 2513 { 2514 uint8_t round; 2515 int64_t res = (int64_t)a * b; 2516 2517 round = get_round(vxrm, res, 16); 2518 res = (res >> 16) + round; 2519 return sadd64(env, vxrm, c, res); 2520 } 2521 2522 RVVCALL(OPIVV3_RM, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) 2523 RVVCALL(OPIVV3_RM, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) 2524 RVVCALL(OPIVV3_RM, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) 2525 GEN_VEXT_VV_RM(vwsmacc_vv_b, 1, 2) 2526 GEN_VEXT_VV_RM(vwsmacc_vv_h, 2, 4) 2527 GEN_VEXT_VV_RM(vwsmacc_vv_w, 4, 8) 2528 RVVCALL(OPIVX3_RM, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) 2529 RVVCALL(OPIVX3_RM, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) 2530 RVVCALL(OPIVX3_RM, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) 2531 GEN_VEXT_VX_RM(vwsmacc_vx_b, 1, 2) 2532 GEN_VEXT_VX_RM(vwsmacc_vx_h, 2, 4) 2533 GEN_VEXT_VX_RM(vwsmacc_vx_w, 4, 8) 2534 2535 static inline int16_t 2536 vwsmaccsu8(CPURISCVState *env, int vxrm, uint8_t a, int8_t b, int16_t c) 2537 { 2538 uint8_t round; 2539 int16_t res = a * (int16_t)b; 2540 2541 round = get_round(vxrm, res, 4); 2542 res = (res >> 4) + round; 2543 return ssub16(env, vxrm, c, res); 2544 } 2545 2546 static inline int32_t 2547 vwsmaccsu16(CPURISCVState *env, int vxrm, uint16_t a, int16_t b, uint32_t c) 2548 { 2549 uint8_t round; 2550 int32_t res = a * (int32_t)b; 2551 2552 round = get_round(vxrm, res, 8); 2553 res = (res >> 8) + round; 2554 return ssub32(env, vxrm, c, res); 2555 } 2556 2557 static inline int64_t 2558 vwsmaccsu32(CPURISCVState *env, int vxrm, uint32_t a, int32_t b, int64_t c) 2559 { 2560 uint8_t round; 2561 int64_t res = a * (int64_t)b; 2562 2563 round = get_round(vxrm, res, 16); 2564 res = (res >> 16) + round; 2565 return ssub64(env, vxrm, c, res); 2566 } 2567 2568 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) 2569 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) 2570 RVVCALL(OPIVV3_RM, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) 2571 GEN_VEXT_VV_RM(vwsmaccsu_vv_b, 1, 2) 2572 GEN_VEXT_VV_RM(vwsmaccsu_vv_h, 2, 4) 2573 GEN_VEXT_VV_RM(vwsmaccsu_vv_w, 4, 8) 2574 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) 2575 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) 2576 RVVCALL(OPIVX3_RM, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) 2577 GEN_VEXT_VX_RM(vwsmaccsu_vx_b, 1, 2) 2578 GEN_VEXT_VX_RM(vwsmaccsu_vx_h, 2, 4) 2579 GEN_VEXT_VX_RM(vwsmaccsu_vx_w, 4, 8) 2580 2581 static inline int16_t 2582 vwsmaccus8(CPURISCVState *env, int vxrm, int8_t a, uint8_t b, int16_t c) 2583 { 2584 uint8_t round; 2585 int16_t res = (int16_t)a * b; 2586 2587 round = get_round(vxrm, res, 4); 2588 res = (res >> 4) + round; 2589 return ssub16(env, vxrm, c, res); 2590 } 2591 2592 static inline int32_t 2593 vwsmaccus16(CPURISCVState *env, int vxrm, int16_t a, uint16_t b, int32_t c) 2594 { 2595 uint8_t round; 2596 int32_t res = (int32_t)a * b; 2597 2598 round = get_round(vxrm, res, 8); 2599 res = (res >> 8) + round; 2600 return ssub32(env, vxrm, c, res); 2601 } 2602 2603 static inline int64_t 2604 vwsmaccus32(CPURISCVState *env, int vxrm, int32_t a, uint32_t b, int64_t c) 2605 { 2606 uint8_t round; 2607 int64_t res = (int64_t)a * b; 2608 2609 round = get_round(vxrm, res, 16); 2610 res = (res >> 16) + round; 2611 return ssub64(env, vxrm, c, res); 2612 } 2613 2614 RVVCALL(OPIVX3_RM, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) 2615 RVVCALL(OPIVX3_RM, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) 2616 RVVCALL(OPIVX3_RM, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) 2617 GEN_VEXT_VX_RM(vwsmaccus_vx_b, 1, 2) 2618 GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4) 2619 GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8) 2620 2621 /* Vector Single-Width Scaling Shift Instructions */ 2622 static inline uint8_t 2623 vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) 2624 { 2625 uint8_t round, shift = b & 0x7; 2626 uint8_t res; 2627 2628 round = get_round(vxrm, a, shift); 2629 res = (a >> shift) + round; 2630 return res; 2631 } 2632 static inline uint16_t 2633 vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) 2634 { 2635 uint8_t round, shift = b & 0xf; 2636 uint16_t res; 2637 2638 round = get_round(vxrm, a, shift); 2639 res = (a >> shift) + round; 2640 return res; 2641 } 2642 static inline uint32_t 2643 vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) 2644 { 2645 uint8_t round, shift = b & 0x1f; 2646 uint32_t res; 2647 2648 round = get_round(vxrm, a, shift); 2649 res = (a >> shift) + round; 2650 return res; 2651 } 2652 static inline uint64_t 2653 vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) 2654 { 2655 uint8_t round, shift = b & 0x3f; 2656 uint64_t res; 2657 2658 round = get_round(vxrm, a, shift); 2659 res = (a >> shift) + round; 2660 return res; 2661 } 2662 RVVCALL(OPIVV2_RM, vssrl_vv_b, OP_UUU_B, H1, H1, H1, vssrl8) 2663 RVVCALL(OPIVV2_RM, vssrl_vv_h, OP_UUU_H, H2, H2, H2, vssrl16) 2664 RVVCALL(OPIVV2_RM, vssrl_vv_w, OP_UUU_W, H4, H4, H4, vssrl32) 2665 RVVCALL(OPIVV2_RM, vssrl_vv_d, OP_UUU_D, H8, H8, H8, vssrl64) 2666 GEN_VEXT_VV_RM(vssrl_vv_b, 1, 1) 2667 GEN_VEXT_VV_RM(vssrl_vv_h, 2, 2) 2668 GEN_VEXT_VV_RM(vssrl_vv_w, 4, 4) 2669 GEN_VEXT_VV_RM(vssrl_vv_d, 8, 8) 2670 2671 RVVCALL(OPIVX2_RM, vssrl_vx_b, OP_UUU_B, H1, H1, vssrl8) 2672 RVVCALL(OPIVX2_RM, vssrl_vx_h, OP_UUU_H, H2, H2, vssrl16) 2673 RVVCALL(OPIVX2_RM, vssrl_vx_w, OP_UUU_W, H4, H4, vssrl32) 2674 RVVCALL(OPIVX2_RM, vssrl_vx_d, OP_UUU_D, H8, H8, vssrl64) 2675 GEN_VEXT_VX_RM(vssrl_vx_b, 1, 1) 2676 GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2) 2677 GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4) 2678 GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8) 2679 2680 static inline int8_t 2681 vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) 2682 { 2683 uint8_t round, shift = b & 0x7; 2684 int8_t res; 2685 2686 round = get_round(vxrm, a, shift); 2687 res = (a >> shift) + round; 2688 return res; 2689 } 2690 static inline int16_t 2691 vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) 2692 { 2693 uint8_t round, shift = b & 0xf; 2694 int16_t res; 2695 2696 round = get_round(vxrm, a, shift); 2697 res = (a >> shift) + round; 2698 return res; 2699 } 2700 static inline int32_t 2701 vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) 2702 { 2703 uint8_t round, shift = b & 0x1f; 2704 int32_t res; 2705 2706 round = get_round(vxrm, a, shift); 2707 res = (a >> shift) + round; 2708 return res; 2709 } 2710 static inline int64_t 2711 vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) 2712 { 2713 uint8_t round, shift = b & 0x3f; 2714 int64_t res; 2715 2716 round = get_round(vxrm, a, shift); 2717 res = (a >> shift) + round; 2718 return res; 2719 } 2720 2721 RVVCALL(OPIVV2_RM, vssra_vv_b, OP_SSS_B, H1, H1, H1, vssra8) 2722 RVVCALL(OPIVV2_RM, vssra_vv_h, OP_SSS_H, H2, H2, H2, vssra16) 2723 RVVCALL(OPIVV2_RM, vssra_vv_w, OP_SSS_W, H4, H4, H4, vssra32) 2724 RVVCALL(OPIVV2_RM, vssra_vv_d, OP_SSS_D, H8, H8, H8, vssra64) 2725 GEN_VEXT_VV_RM(vssra_vv_b, 1, 1) 2726 GEN_VEXT_VV_RM(vssra_vv_h, 2, 2) 2727 GEN_VEXT_VV_RM(vssra_vv_w, 4, 4) 2728 GEN_VEXT_VV_RM(vssra_vv_d, 8, 8) 2729 2730 RVVCALL(OPIVX2_RM, vssra_vx_b, OP_SSS_B, H1, H1, vssra8) 2731 RVVCALL(OPIVX2_RM, vssra_vx_h, OP_SSS_H, H2, H2, vssra16) 2732 RVVCALL(OPIVX2_RM, vssra_vx_w, OP_SSS_W, H4, H4, vssra32) 2733 RVVCALL(OPIVX2_RM, vssra_vx_d, OP_SSS_D, H8, H8, vssra64) 2734 GEN_VEXT_VX_RM(vssra_vx_b, 1, 1) 2735 GEN_VEXT_VX_RM(vssra_vx_h, 2, 2) 2736 GEN_VEXT_VX_RM(vssra_vx_w, 4, 4) 2737 GEN_VEXT_VX_RM(vssra_vx_d, 8, 8) 2738 2739 /* Vector Narrowing Fixed-Point Clip Instructions */ 2740 static inline int8_t 2741 vnclip8(CPURISCVState *env, int vxrm, int16_t a, int8_t b) 2742 { 2743 uint8_t round, shift = b & 0xf; 2744 int16_t res; 2745 2746 round = get_round(vxrm, a, shift); 2747 res = (a >> shift) + round; 2748 if (res > INT8_MAX) { 2749 env->vxsat = 0x1; 2750 return INT8_MAX; 2751 } else if (res < INT8_MIN) { 2752 env->vxsat = 0x1; 2753 return INT8_MIN; 2754 } else { 2755 return res; 2756 } 2757 } 2758 2759 static inline int16_t 2760 vnclip16(CPURISCVState *env, int vxrm, int32_t a, int16_t b) 2761 { 2762 uint8_t round, shift = b & 0x1f; 2763 int32_t res; 2764 2765 round = get_round(vxrm, a, shift); 2766 res = (a >> shift) + round; 2767 if (res > INT16_MAX) { 2768 env->vxsat = 0x1; 2769 return INT16_MAX; 2770 } else if (res < INT16_MIN) { 2771 env->vxsat = 0x1; 2772 return INT16_MIN; 2773 } else { 2774 return res; 2775 } 2776 } 2777 2778 static inline int32_t 2779 vnclip32(CPURISCVState *env, int vxrm, int64_t a, int32_t b) 2780 { 2781 uint8_t round, shift = b & 0x3f; 2782 int64_t res; 2783 2784 round = get_round(vxrm, a, shift); 2785 res = (a >> shift) + round; 2786 if (res > INT32_MAX) { 2787 env->vxsat = 0x1; 2788 return INT32_MAX; 2789 } else if (res < INT32_MIN) { 2790 env->vxsat = 0x1; 2791 return INT32_MIN; 2792 } else { 2793 return res; 2794 } 2795 } 2796 2797 RVVCALL(OPIVV2_RM, vnclip_vv_b, NOP_SSS_B, H1, H2, H1, vnclip8) 2798 RVVCALL(OPIVV2_RM, vnclip_vv_h, NOP_SSS_H, H2, H4, H2, vnclip16) 2799 RVVCALL(OPIVV2_RM, vnclip_vv_w, NOP_SSS_W, H4, H8, H4, vnclip32) 2800 GEN_VEXT_VV_RM(vnclip_vv_b, 1, 1) 2801 GEN_VEXT_VV_RM(vnclip_vv_h, 2, 2) 2802 GEN_VEXT_VV_RM(vnclip_vv_w, 4, 4) 2803 2804 RVVCALL(OPIVX2_RM, vnclip_vx_b, NOP_SSS_B, H1, H2, vnclip8) 2805 RVVCALL(OPIVX2_RM, vnclip_vx_h, NOP_SSS_H, H2, H4, vnclip16) 2806 RVVCALL(OPIVX2_RM, vnclip_vx_w, NOP_SSS_W, H4, H8, vnclip32) 2807 GEN_VEXT_VX_RM(vnclip_vx_b, 1, 1) 2808 GEN_VEXT_VX_RM(vnclip_vx_h, 2, 2) 2809 GEN_VEXT_VX_RM(vnclip_vx_w, 4, 4) 2810 2811 static inline uint8_t 2812 vnclipu8(CPURISCVState *env, int vxrm, uint16_t a, uint8_t b) 2813 { 2814 uint8_t round, shift = b & 0xf; 2815 uint16_t res; 2816 2817 round = get_round(vxrm, a, shift); 2818 res = (a >> shift) + round; 2819 if (res > UINT8_MAX) { 2820 env->vxsat = 0x1; 2821 return UINT8_MAX; 2822 } else { 2823 return res; 2824 } 2825 } 2826 2827 static inline uint16_t 2828 vnclipu16(CPURISCVState *env, int vxrm, uint32_t a, uint16_t b) 2829 { 2830 uint8_t round, shift = b & 0x1f; 2831 uint32_t res; 2832 2833 round = get_round(vxrm, a, shift); 2834 res = (a >> shift) + round; 2835 if (res > UINT16_MAX) { 2836 env->vxsat = 0x1; 2837 return UINT16_MAX; 2838 } else { 2839 return res; 2840 } 2841 } 2842 2843 static inline uint32_t 2844 vnclipu32(CPURISCVState *env, int vxrm, uint64_t a, uint32_t b) 2845 { 2846 uint8_t round, shift = b & 0x3f; 2847 int64_t res; 2848 2849 round = get_round(vxrm, a, shift); 2850 res = (a >> shift) + round; 2851 if (res > UINT32_MAX) { 2852 env->vxsat = 0x1; 2853 return UINT32_MAX; 2854 } else { 2855 return res; 2856 } 2857 } 2858 2859 RVVCALL(OPIVV2_RM, vnclipu_vv_b, NOP_UUU_B, H1, H2, H1, vnclipu8) 2860 RVVCALL(OPIVV2_RM, vnclipu_vv_h, NOP_UUU_H, H2, H4, H2, vnclipu16) 2861 RVVCALL(OPIVV2_RM, vnclipu_vv_w, NOP_UUU_W, H4, H8, H4, vnclipu32) 2862 GEN_VEXT_VV_RM(vnclipu_vv_b, 1, 1) 2863 GEN_VEXT_VV_RM(vnclipu_vv_h, 2, 2) 2864 GEN_VEXT_VV_RM(vnclipu_vv_w, 4, 4) 2865 2866 RVVCALL(OPIVX2_RM, vnclipu_vx_b, NOP_UUU_B, H1, H2, vnclipu8) 2867 RVVCALL(OPIVX2_RM, vnclipu_vx_h, NOP_UUU_H, H2, H4, vnclipu16) 2868 RVVCALL(OPIVX2_RM, vnclipu_vx_w, NOP_UUU_W, H4, H8, vnclipu32) 2869 GEN_VEXT_VX_RM(vnclipu_vx_b, 1, 1) 2870 GEN_VEXT_VX_RM(vnclipu_vx_h, 2, 2) 2871 GEN_VEXT_VX_RM(vnclipu_vx_w, 4, 4) 2872 2873 /* 2874 *** Vector Float Point Arithmetic Instructions 2875 */ 2876 /* Vector Single-Width Floating-Point Add/Subtract Instructions */ 2877 #define OPFVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 2878 static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ 2879 CPURISCVState *env) \ 2880 { \ 2881 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 2882 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 2883 *((TD *)vd + HD(i)) = OP(s2, s1, &env->fp_status); \ 2884 } 2885 2886 #define GEN_VEXT_VV_ENV(NAME, ESZ, DSZ) \ 2887 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 2888 void *vs2, CPURISCVState *env, \ 2889 uint32_t desc) \ 2890 { \ 2891 uint32_t vm = vext_vm(desc); \ 2892 uint32_t vl = env->vl; \ 2893 uint32_t i; \ 2894 \ 2895 for (i = 0; i < vl; i++) { \ 2896 if (!vm && !vext_elem_mask(v0, i)) { \ 2897 continue; \ 2898 } \ 2899 do_##NAME(vd, vs1, vs2, i, env); \ 2900 } \ 2901 } 2902 2903 RVVCALL(OPFVV2, vfadd_vv_h, OP_UUU_H, H2, H2, H2, float16_add) 2904 RVVCALL(OPFVV2, vfadd_vv_w, OP_UUU_W, H4, H4, H4, float32_add) 2905 RVVCALL(OPFVV2, vfadd_vv_d, OP_UUU_D, H8, H8, H8, float64_add) 2906 GEN_VEXT_VV_ENV(vfadd_vv_h, 2, 2) 2907 GEN_VEXT_VV_ENV(vfadd_vv_w, 4, 4) 2908 GEN_VEXT_VV_ENV(vfadd_vv_d, 8, 8) 2909 2910 #define OPFVF2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 2911 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ 2912 CPURISCVState *env) \ 2913 { \ 2914 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 2915 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, &env->fp_status);\ 2916 } 2917 2918 #define GEN_VEXT_VF(NAME, ESZ, DSZ) \ 2919 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, \ 2920 void *vs2, CPURISCVState *env, \ 2921 uint32_t desc) \ 2922 { \ 2923 uint32_t vm = vext_vm(desc); \ 2924 uint32_t vl = env->vl; \ 2925 uint32_t i; \ 2926 \ 2927 for (i = 0; i < vl; i++) { \ 2928 if (!vm && !vext_elem_mask(v0, i)) { \ 2929 continue; \ 2930 } \ 2931 do_##NAME(vd, s1, vs2, i, env); \ 2932 } \ 2933 } 2934 2935 RVVCALL(OPFVF2, vfadd_vf_h, OP_UUU_H, H2, H2, float16_add) 2936 RVVCALL(OPFVF2, vfadd_vf_w, OP_UUU_W, H4, H4, float32_add) 2937 RVVCALL(OPFVF2, vfadd_vf_d, OP_UUU_D, H8, H8, float64_add) 2938 GEN_VEXT_VF(vfadd_vf_h, 2, 2) 2939 GEN_VEXT_VF(vfadd_vf_w, 4, 4) 2940 GEN_VEXT_VF(vfadd_vf_d, 8, 8) 2941 2942 RVVCALL(OPFVV2, vfsub_vv_h, OP_UUU_H, H2, H2, H2, float16_sub) 2943 RVVCALL(OPFVV2, vfsub_vv_w, OP_UUU_W, H4, H4, H4, float32_sub) 2944 RVVCALL(OPFVV2, vfsub_vv_d, OP_UUU_D, H8, H8, H8, float64_sub) 2945 GEN_VEXT_VV_ENV(vfsub_vv_h, 2, 2) 2946 GEN_VEXT_VV_ENV(vfsub_vv_w, 4, 4) 2947 GEN_VEXT_VV_ENV(vfsub_vv_d, 8, 8) 2948 RVVCALL(OPFVF2, vfsub_vf_h, OP_UUU_H, H2, H2, float16_sub) 2949 RVVCALL(OPFVF2, vfsub_vf_w, OP_UUU_W, H4, H4, float32_sub) 2950 RVVCALL(OPFVF2, vfsub_vf_d, OP_UUU_D, H8, H8, float64_sub) 2951 GEN_VEXT_VF(vfsub_vf_h, 2, 2) 2952 GEN_VEXT_VF(vfsub_vf_w, 4, 4) 2953 GEN_VEXT_VF(vfsub_vf_d, 8, 8) 2954 2955 static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s) 2956 { 2957 return float16_sub(b, a, s); 2958 } 2959 2960 static uint32_t float32_rsub(uint32_t a, uint32_t b, float_status *s) 2961 { 2962 return float32_sub(b, a, s); 2963 } 2964 2965 static uint64_t float64_rsub(uint64_t a, uint64_t b, float_status *s) 2966 { 2967 return float64_sub(b, a, s); 2968 } 2969 2970 RVVCALL(OPFVF2, vfrsub_vf_h, OP_UUU_H, H2, H2, float16_rsub) 2971 RVVCALL(OPFVF2, vfrsub_vf_w, OP_UUU_W, H4, H4, float32_rsub) 2972 RVVCALL(OPFVF2, vfrsub_vf_d, OP_UUU_D, H8, H8, float64_rsub) 2973 GEN_VEXT_VF(vfrsub_vf_h, 2, 2) 2974 GEN_VEXT_VF(vfrsub_vf_w, 4, 4) 2975 GEN_VEXT_VF(vfrsub_vf_d, 8, 8) 2976 2977 /* Vector Widening Floating-Point Add/Subtract Instructions */ 2978 static uint32_t vfwadd16(uint16_t a, uint16_t b, float_status *s) 2979 { 2980 return float32_add(float16_to_float32(a, true, s), 2981 float16_to_float32(b, true, s), s); 2982 } 2983 2984 static uint64_t vfwadd32(uint32_t a, uint32_t b, float_status *s) 2985 { 2986 return float64_add(float32_to_float64(a, s), 2987 float32_to_float64(b, s), s); 2988 2989 } 2990 2991 RVVCALL(OPFVV2, vfwadd_vv_h, WOP_UUU_H, H4, H2, H2, vfwadd16) 2992 RVVCALL(OPFVV2, vfwadd_vv_w, WOP_UUU_W, H8, H4, H4, vfwadd32) 2993 GEN_VEXT_VV_ENV(vfwadd_vv_h, 2, 4) 2994 GEN_VEXT_VV_ENV(vfwadd_vv_w, 4, 8) 2995 RVVCALL(OPFVF2, vfwadd_vf_h, WOP_UUU_H, H4, H2, vfwadd16) 2996 RVVCALL(OPFVF2, vfwadd_vf_w, WOP_UUU_W, H8, H4, vfwadd32) 2997 GEN_VEXT_VF(vfwadd_vf_h, 2, 4) 2998 GEN_VEXT_VF(vfwadd_vf_w, 4, 8) 2999 3000 static uint32_t vfwsub16(uint16_t a, uint16_t b, float_status *s) 3001 { 3002 return float32_sub(float16_to_float32(a, true, s), 3003 float16_to_float32(b, true, s), s); 3004 } 3005 3006 static uint64_t vfwsub32(uint32_t a, uint32_t b, float_status *s) 3007 { 3008 return float64_sub(float32_to_float64(a, s), 3009 float32_to_float64(b, s), s); 3010 3011 } 3012 3013 RVVCALL(OPFVV2, vfwsub_vv_h, WOP_UUU_H, H4, H2, H2, vfwsub16) 3014 RVVCALL(OPFVV2, vfwsub_vv_w, WOP_UUU_W, H8, H4, H4, vfwsub32) 3015 GEN_VEXT_VV_ENV(vfwsub_vv_h, 2, 4) 3016 GEN_VEXT_VV_ENV(vfwsub_vv_w, 4, 8) 3017 RVVCALL(OPFVF2, vfwsub_vf_h, WOP_UUU_H, H4, H2, vfwsub16) 3018 RVVCALL(OPFVF2, vfwsub_vf_w, WOP_UUU_W, H8, H4, vfwsub32) 3019 GEN_VEXT_VF(vfwsub_vf_h, 2, 4) 3020 GEN_VEXT_VF(vfwsub_vf_w, 4, 8) 3021 3022 static uint32_t vfwaddw16(uint32_t a, uint16_t b, float_status *s) 3023 { 3024 return float32_add(a, float16_to_float32(b, true, s), s); 3025 } 3026 3027 static uint64_t vfwaddw32(uint64_t a, uint32_t b, float_status *s) 3028 { 3029 return float64_add(a, float32_to_float64(b, s), s); 3030 } 3031 3032 RVVCALL(OPFVV2, vfwadd_wv_h, WOP_WUUU_H, H4, H2, H2, vfwaddw16) 3033 RVVCALL(OPFVV2, vfwadd_wv_w, WOP_WUUU_W, H8, H4, H4, vfwaddw32) 3034 GEN_VEXT_VV_ENV(vfwadd_wv_h, 2, 4) 3035 GEN_VEXT_VV_ENV(vfwadd_wv_w, 4, 8) 3036 RVVCALL(OPFVF2, vfwadd_wf_h, WOP_WUUU_H, H4, H2, vfwaddw16) 3037 RVVCALL(OPFVF2, vfwadd_wf_w, WOP_WUUU_W, H8, H4, vfwaddw32) 3038 GEN_VEXT_VF(vfwadd_wf_h, 2, 4) 3039 GEN_VEXT_VF(vfwadd_wf_w, 4, 8) 3040 3041 static uint32_t vfwsubw16(uint32_t a, uint16_t b, float_status *s) 3042 { 3043 return float32_sub(a, float16_to_float32(b, true, s), s); 3044 } 3045 3046 static uint64_t vfwsubw32(uint64_t a, uint32_t b, float_status *s) 3047 { 3048 return float64_sub(a, float32_to_float64(b, s), s); 3049 } 3050 3051 RVVCALL(OPFVV2, vfwsub_wv_h, WOP_WUUU_H, H4, H2, H2, vfwsubw16) 3052 RVVCALL(OPFVV2, vfwsub_wv_w, WOP_WUUU_W, H8, H4, H4, vfwsubw32) 3053 GEN_VEXT_VV_ENV(vfwsub_wv_h, 2, 4) 3054 GEN_VEXT_VV_ENV(vfwsub_wv_w, 4, 8) 3055 RVVCALL(OPFVF2, vfwsub_wf_h, WOP_WUUU_H, H4, H2, vfwsubw16) 3056 RVVCALL(OPFVF2, vfwsub_wf_w, WOP_WUUU_W, H8, H4, vfwsubw32) 3057 GEN_VEXT_VF(vfwsub_wf_h, 2, 4) 3058 GEN_VEXT_VF(vfwsub_wf_w, 4, 8) 3059 3060 /* Vector Single-Width Floating-Point Multiply/Divide Instructions */ 3061 RVVCALL(OPFVV2, vfmul_vv_h, OP_UUU_H, H2, H2, H2, float16_mul) 3062 RVVCALL(OPFVV2, vfmul_vv_w, OP_UUU_W, H4, H4, H4, float32_mul) 3063 RVVCALL(OPFVV2, vfmul_vv_d, OP_UUU_D, H8, H8, H8, float64_mul) 3064 GEN_VEXT_VV_ENV(vfmul_vv_h, 2, 2) 3065 GEN_VEXT_VV_ENV(vfmul_vv_w, 4, 4) 3066 GEN_VEXT_VV_ENV(vfmul_vv_d, 8, 8) 3067 RVVCALL(OPFVF2, vfmul_vf_h, OP_UUU_H, H2, H2, float16_mul) 3068 RVVCALL(OPFVF2, vfmul_vf_w, OP_UUU_W, H4, H4, float32_mul) 3069 RVVCALL(OPFVF2, vfmul_vf_d, OP_UUU_D, H8, H8, float64_mul) 3070 GEN_VEXT_VF(vfmul_vf_h, 2, 2) 3071 GEN_VEXT_VF(vfmul_vf_w, 4, 4) 3072 GEN_VEXT_VF(vfmul_vf_d, 8, 8) 3073 3074 RVVCALL(OPFVV2, vfdiv_vv_h, OP_UUU_H, H2, H2, H2, float16_div) 3075 RVVCALL(OPFVV2, vfdiv_vv_w, OP_UUU_W, H4, H4, H4, float32_div) 3076 RVVCALL(OPFVV2, vfdiv_vv_d, OP_UUU_D, H8, H8, H8, float64_div) 3077 GEN_VEXT_VV_ENV(vfdiv_vv_h, 2, 2) 3078 GEN_VEXT_VV_ENV(vfdiv_vv_w, 4, 4) 3079 GEN_VEXT_VV_ENV(vfdiv_vv_d, 8, 8) 3080 RVVCALL(OPFVF2, vfdiv_vf_h, OP_UUU_H, H2, H2, float16_div) 3081 RVVCALL(OPFVF2, vfdiv_vf_w, OP_UUU_W, H4, H4, float32_div) 3082 RVVCALL(OPFVF2, vfdiv_vf_d, OP_UUU_D, H8, H8, float64_div) 3083 GEN_VEXT_VF(vfdiv_vf_h, 2, 2) 3084 GEN_VEXT_VF(vfdiv_vf_w, 4, 4) 3085 GEN_VEXT_VF(vfdiv_vf_d, 8, 8) 3086 3087 static uint16_t float16_rdiv(uint16_t a, uint16_t b, float_status *s) 3088 { 3089 return float16_div(b, a, s); 3090 } 3091 3092 static uint32_t float32_rdiv(uint32_t a, uint32_t b, float_status *s) 3093 { 3094 return float32_div(b, a, s); 3095 } 3096 3097 static uint64_t float64_rdiv(uint64_t a, uint64_t b, float_status *s) 3098 { 3099 return float64_div(b, a, s); 3100 } 3101 3102 RVVCALL(OPFVF2, vfrdiv_vf_h, OP_UUU_H, H2, H2, float16_rdiv) 3103 RVVCALL(OPFVF2, vfrdiv_vf_w, OP_UUU_W, H4, H4, float32_rdiv) 3104 RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv) 3105 GEN_VEXT_VF(vfrdiv_vf_h, 2, 2) 3106 GEN_VEXT_VF(vfrdiv_vf_w, 4, 4) 3107 GEN_VEXT_VF(vfrdiv_vf_d, 8, 8) 3108 3109 /* Vector Widening Floating-Point Multiply */ 3110 static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s) 3111 { 3112 return float32_mul(float16_to_float32(a, true, s), 3113 float16_to_float32(b, true, s), s); 3114 } 3115 3116 static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s) 3117 { 3118 return float64_mul(float32_to_float64(a, s), 3119 float32_to_float64(b, s), s); 3120 3121 } 3122 RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16) 3123 RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32) 3124 GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4) 3125 GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8) 3126 RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16) 3127 RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32) 3128 GEN_VEXT_VF(vfwmul_vf_h, 2, 4) 3129 GEN_VEXT_VF(vfwmul_vf_w, 4, 8) 3130 3131 /* Vector Single-Width Floating-Point Fused Multiply-Add Instructions */ 3132 #define OPFVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ 3133 static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ 3134 CPURISCVState *env) \ 3135 { \ 3136 TX1 s1 = *((T1 *)vs1 + HS1(i)); \ 3137 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 3138 TD d = *((TD *)vd + HD(i)); \ 3139 *((TD *)vd + HD(i)) = OP(s2, s1, d, &env->fp_status); \ 3140 } 3141 3142 static uint16_t fmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3143 { 3144 return float16_muladd(a, b, d, 0, s); 3145 } 3146 3147 static uint32_t fmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3148 { 3149 return float32_muladd(a, b, d, 0, s); 3150 } 3151 3152 static uint64_t fmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3153 { 3154 return float64_muladd(a, b, d, 0, s); 3155 } 3156 3157 RVVCALL(OPFVV3, vfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16) 3158 RVVCALL(OPFVV3, vfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32) 3159 RVVCALL(OPFVV3, vfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64) 3160 GEN_VEXT_VV_ENV(vfmacc_vv_h, 2, 2) 3161 GEN_VEXT_VV_ENV(vfmacc_vv_w, 4, 4) 3162 GEN_VEXT_VV_ENV(vfmacc_vv_d, 8, 8) 3163 3164 #define OPFVF3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ 3165 static void do_##NAME(void *vd, uint64_t s1, void *vs2, int i, \ 3166 CPURISCVState *env) \ 3167 { \ 3168 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 3169 TD d = *((TD *)vd + HD(i)); \ 3170 *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d, &env->fp_status);\ 3171 } 3172 3173 RVVCALL(OPFVF3, vfmacc_vf_h, OP_UUU_H, H2, H2, fmacc16) 3174 RVVCALL(OPFVF3, vfmacc_vf_w, OP_UUU_W, H4, H4, fmacc32) 3175 RVVCALL(OPFVF3, vfmacc_vf_d, OP_UUU_D, H8, H8, fmacc64) 3176 GEN_VEXT_VF(vfmacc_vf_h, 2, 2) 3177 GEN_VEXT_VF(vfmacc_vf_w, 4, 4) 3178 GEN_VEXT_VF(vfmacc_vf_d, 8, 8) 3179 3180 static uint16_t fnmacc16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3181 { 3182 return float16_muladd(a, b, d, 3183 float_muladd_negate_c | float_muladd_negate_product, s); 3184 } 3185 3186 static uint32_t fnmacc32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3187 { 3188 return float32_muladd(a, b, d, 3189 float_muladd_negate_c | float_muladd_negate_product, s); 3190 } 3191 3192 static uint64_t fnmacc64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3193 { 3194 return float64_muladd(a, b, d, 3195 float_muladd_negate_c | float_muladd_negate_product, s); 3196 } 3197 3198 RVVCALL(OPFVV3, vfnmacc_vv_h, OP_UUU_H, H2, H2, H2, fnmacc16) 3199 RVVCALL(OPFVV3, vfnmacc_vv_w, OP_UUU_W, H4, H4, H4, fnmacc32) 3200 RVVCALL(OPFVV3, vfnmacc_vv_d, OP_UUU_D, H8, H8, H8, fnmacc64) 3201 GEN_VEXT_VV_ENV(vfnmacc_vv_h, 2, 2) 3202 GEN_VEXT_VV_ENV(vfnmacc_vv_w, 4, 4) 3203 GEN_VEXT_VV_ENV(vfnmacc_vv_d, 8, 8) 3204 RVVCALL(OPFVF3, vfnmacc_vf_h, OP_UUU_H, H2, H2, fnmacc16) 3205 RVVCALL(OPFVF3, vfnmacc_vf_w, OP_UUU_W, H4, H4, fnmacc32) 3206 RVVCALL(OPFVF3, vfnmacc_vf_d, OP_UUU_D, H8, H8, fnmacc64) 3207 GEN_VEXT_VF(vfnmacc_vf_h, 2, 2) 3208 GEN_VEXT_VF(vfnmacc_vf_w, 4, 4) 3209 GEN_VEXT_VF(vfnmacc_vf_d, 8, 8) 3210 3211 static uint16_t fmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3212 { 3213 return float16_muladd(a, b, d, float_muladd_negate_c, s); 3214 } 3215 3216 static uint32_t fmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3217 { 3218 return float32_muladd(a, b, d, float_muladd_negate_c, s); 3219 } 3220 3221 static uint64_t fmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3222 { 3223 return float64_muladd(a, b, d, float_muladd_negate_c, s); 3224 } 3225 3226 RVVCALL(OPFVV3, vfmsac_vv_h, OP_UUU_H, H2, H2, H2, fmsac16) 3227 RVVCALL(OPFVV3, vfmsac_vv_w, OP_UUU_W, H4, H4, H4, fmsac32) 3228 RVVCALL(OPFVV3, vfmsac_vv_d, OP_UUU_D, H8, H8, H8, fmsac64) 3229 GEN_VEXT_VV_ENV(vfmsac_vv_h, 2, 2) 3230 GEN_VEXT_VV_ENV(vfmsac_vv_w, 4, 4) 3231 GEN_VEXT_VV_ENV(vfmsac_vv_d, 8, 8) 3232 RVVCALL(OPFVF3, vfmsac_vf_h, OP_UUU_H, H2, H2, fmsac16) 3233 RVVCALL(OPFVF3, vfmsac_vf_w, OP_UUU_W, H4, H4, fmsac32) 3234 RVVCALL(OPFVF3, vfmsac_vf_d, OP_UUU_D, H8, H8, fmsac64) 3235 GEN_VEXT_VF(vfmsac_vf_h, 2, 2) 3236 GEN_VEXT_VF(vfmsac_vf_w, 4, 4) 3237 GEN_VEXT_VF(vfmsac_vf_d, 8, 8) 3238 3239 static uint16_t fnmsac16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3240 { 3241 return float16_muladd(a, b, d, float_muladd_negate_product, s); 3242 } 3243 3244 static uint32_t fnmsac32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3245 { 3246 return float32_muladd(a, b, d, float_muladd_negate_product, s); 3247 } 3248 3249 static uint64_t fnmsac64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3250 { 3251 return float64_muladd(a, b, d, float_muladd_negate_product, s); 3252 } 3253 3254 RVVCALL(OPFVV3, vfnmsac_vv_h, OP_UUU_H, H2, H2, H2, fnmsac16) 3255 RVVCALL(OPFVV3, vfnmsac_vv_w, OP_UUU_W, H4, H4, H4, fnmsac32) 3256 RVVCALL(OPFVV3, vfnmsac_vv_d, OP_UUU_D, H8, H8, H8, fnmsac64) 3257 GEN_VEXT_VV_ENV(vfnmsac_vv_h, 2, 2) 3258 GEN_VEXT_VV_ENV(vfnmsac_vv_w, 4, 4) 3259 GEN_VEXT_VV_ENV(vfnmsac_vv_d, 8, 8) 3260 RVVCALL(OPFVF3, vfnmsac_vf_h, OP_UUU_H, H2, H2, fnmsac16) 3261 RVVCALL(OPFVF3, vfnmsac_vf_w, OP_UUU_W, H4, H4, fnmsac32) 3262 RVVCALL(OPFVF3, vfnmsac_vf_d, OP_UUU_D, H8, H8, fnmsac64) 3263 GEN_VEXT_VF(vfnmsac_vf_h, 2, 2) 3264 GEN_VEXT_VF(vfnmsac_vf_w, 4, 4) 3265 GEN_VEXT_VF(vfnmsac_vf_d, 8, 8) 3266 3267 static uint16_t fmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3268 { 3269 return float16_muladd(d, b, a, 0, s); 3270 } 3271 3272 static uint32_t fmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3273 { 3274 return float32_muladd(d, b, a, 0, s); 3275 } 3276 3277 static uint64_t fmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3278 { 3279 return float64_muladd(d, b, a, 0, s); 3280 } 3281 3282 RVVCALL(OPFVV3, vfmadd_vv_h, OP_UUU_H, H2, H2, H2, fmadd16) 3283 RVVCALL(OPFVV3, vfmadd_vv_w, OP_UUU_W, H4, H4, H4, fmadd32) 3284 RVVCALL(OPFVV3, vfmadd_vv_d, OP_UUU_D, H8, H8, H8, fmadd64) 3285 GEN_VEXT_VV_ENV(vfmadd_vv_h, 2, 2) 3286 GEN_VEXT_VV_ENV(vfmadd_vv_w, 4, 4) 3287 GEN_VEXT_VV_ENV(vfmadd_vv_d, 8, 8) 3288 RVVCALL(OPFVF3, vfmadd_vf_h, OP_UUU_H, H2, H2, fmadd16) 3289 RVVCALL(OPFVF3, vfmadd_vf_w, OP_UUU_W, H4, H4, fmadd32) 3290 RVVCALL(OPFVF3, vfmadd_vf_d, OP_UUU_D, H8, H8, fmadd64) 3291 GEN_VEXT_VF(vfmadd_vf_h, 2, 2) 3292 GEN_VEXT_VF(vfmadd_vf_w, 4, 4) 3293 GEN_VEXT_VF(vfmadd_vf_d, 8, 8) 3294 3295 static uint16_t fnmadd16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3296 { 3297 return float16_muladd(d, b, a, 3298 float_muladd_negate_c | float_muladd_negate_product, s); 3299 } 3300 3301 static uint32_t fnmadd32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3302 { 3303 return float32_muladd(d, b, a, 3304 float_muladd_negate_c | float_muladd_negate_product, s); 3305 } 3306 3307 static uint64_t fnmadd64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3308 { 3309 return float64_muladd(d, b, a, 3310 float_muladd_negate_c | float_muladd_negate_product, s); 3311 } 3312 3313 RVVCALL(OPFVV3, vfnmadd_vv_h, OP_UUU_H, H2, H2, H2, fnmadd16) 3314 RVVCALL(OPFVV3, vfnmadd_vv_w, OP_UUU_W, H4, H4, H4, fnmadd32) 3315 RVVCALL(OPFVV3, vfnmadd_vv_d, OP_UUU_D, H8, H8, H8, fnmadd64) 3316 GEN_VEXT_VV_ENV(vfnmadd_vv_h, 2, 2) 3317 GEN_VEXT_VV_ENV(vfnmadd_vv_w, 4, 4) 3318 GEN_VEXT_VV_ENV(vfnmadd_vv_d, 8, 8) 3319 RVVCALL(OPFVF3, vfnmadd_vf_h, OP_UUU_H, H2, H2, fnmadd16) 3320 RVVCALL(OPFVF3, vfnmadd_vf_w, OP_UUU_W, H4, H4, fnmadd32) 3321 RVVCALL(OPFVF3, vfnmadd_vf_d, OP_UUU_D, H8, H8, fnmadd64) 3322 GEN_VEXT_VF(vfnmadd_vf_h, 2, 2) 3323 GEN_VEXT_VF(vfnmadd_vf_w, 4, 4) 3324 GEN_VEXT_VF(vfnmadd_vf_d, 8, 8) 3325 3326 static uint16_t fmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3327 { 3328 return float16_muladd(d, b, a, float_muladd_negate_c, s); 3329 } 3330 3331 static uint32_t fmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3332 { 3333 return float32_muladd(d, b, a, float_muladd_negate_c, s); 3334 } 3335 3336 static uint64_t fmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3337 { 3338 return float64_muladd(d, b, a, float_muladd_negate_c, s); 3339 } 3340 3341 RVVCALL(OPFVV3, vfmsub_vv_h, OP_UUU_H, H2, H2, H2, fmsub16) 3342 RVVCALL(OPFVV3, vfmsub_vv_w, OP_UUU_W, H4, H4, H4, fmsub32) 3343 RVVCALL(OPFVV3, vfmsub_vv_d, OP_UUU_D, H8, H8, H8, fmsub64) 3344 GEN_VEXT_VV_ENV(vfmsub_vv_h, 2, 2) 3345 GEN_VEXT_VV_ENV(vfmsub_vv_w, 4, 4) 3346 GEN_VEXT_VV_ENV(vfmsub_vv_d, 8, 8) 3347 RVVCALL(OPFVF3, vfmsub_vf_h, OP_UUU_H, H2, H2, fmsub16) 3348 RVVCALL(OPFVF3, vfmsub_vf_w, OP_UUU_W, H4, H4, fmsub32) 3349 RVVCALL(OPFVF3, vfmsub_vf_d, OP_UUU_D, H8, H8, fmsub64) 3350 GEN_VEXT_VF(vfmsub_vf_h, 2, 2) 3351 GEN_VEXT_VF(vfmsub_vf_w, 4, 4) 3352 GEN_VEXT_VF(vfmsub_vf_d, 8, 8) 3353 3354 static uint16_t fnmsub16(uint16_t a, uint16_t b, uint16_t d, float_status *s) 3355 { 3356 return float16_muladd(d, b, a, float_muladd_negate_product, s); 3357 } 3358 3359 static uint32_t fnmsub32(uint32_t a, uint32_t b, uint32_t d, float_status *s) 3360 { 3361 return float32_muladd(d, b, a, float_muladd_negate_product, s); 3362 } 3363 3364 static uint64_t fnmsub64(uint64_t a, uint64_t b, uint64_t d, float_status *s) 3365 { 3366 return float64_muladd(d, b, a, float_muladd_negate_product, s); 3367 } 3368 3369 RVVCALL(OPFVV3, vfnmsub_vv_h, OP_UUU_H, H2, H2, H2, fnmsub16) 3370 RVVCALL(OPFVV3, vfnmsub_vv_w, OP_UUU_W, H4, H4, H4, fnmsub32) 3371 RVVCALL(OPFVV3, vfnmsub_vv_d, OP_UUU_D, H8, H8, H8, fnmsub64) 3372 GEN_VEXT_VV_ENV(vfnmsub_vv_h, 2, 2) 3373 GEN_VEXT_VV_ENV(vfnmsub_vv_w, 4, 4) 3374 GEN_VEXT_VV_ENV(vfnmsub_vv_d, 8, 8) 3375 RVVCALL(OPFVF3, vfnmsub_vf_h, OP_UUU_H, H2, H2, fnmsub16) 3376 RVVCALL(OPFVF3, vfnmsub_vf_w, OP_UUU_W, H4, H4, fnmsub32) 3377 RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64) 3378 GEN_VEXT_VF(vfnmsub_vf_h, 2, 2) 3379 GEN_VEXT_VF(vfnmsub_vf_w, 4, 4) 3380 GEN_VEXT_VF(vfnmsub_vf_d, 8, 8) 3381 3382 /* Vector Widening Floating-Point Fused Multiply-Add Instructions */ 3383 static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) 3384 { 3385 return float32_muladd(float16_to_float32(a, true, s), 3386 float16_to_float32(b, true, s), d, 0, s); 3387 } 3388 3389 static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) 3390 { 3391 return float64_muladd(float32_to_float64(a, s), 3392 float32_to_float64(b, s), d, 0, s); 3393 } 3394 3395 RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) 3396 RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32) 3397 GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4) 3398 GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8) 3399 RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16) 3400 RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32) 3401 GEN_VEXT_VF(vfwmacc_vf_h, 2, 4) 3402 GEN_VEXT_VF(vfwmacc_vf_w, 4, 8) 3403 3404 static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) 3405 { 3406 return float32_muladd(float16_to_float32(a, true, s), 3407 float16_to_float32(b, true, s), d, 3408 float_muladd_negate_c | float_muladd_negate_product, s); 3409 } 3410 3411 static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) 3412 { 3413 return float64_muladd(float32_to_float64(a, s), 3414 float32_to_float64(b, s), d, 3415 float_muladd_negate_c | float_muladd_negate_product, s); 3416 } 3417 3418 RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) 3419 RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32) 3420 GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4) 3421 GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8) 3422 RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16) 3423 RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32) 3424 GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4) 3425 GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8) 3426 3427 static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) 3428 { 3429 return float32_muladd(float16_to_float32(a, true, s), 3430 float16_to_float32(b, true, s), d, 3431 float_muladd_negate_c, s); 3432 } 3433 3434 static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) 3435 { 3436 return float64_muladd(float32_to_float64(a, s), 3437 float32_to_float64(b, s), d, 3438 float_muladd_negate_c, s); 3439 } 3440 3441 RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) 3442 RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32) 3443 GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4) 3444 GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8) 3445 RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16) 3446 RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32) 3447 GEN_VEXT_VF(vfwmsac_vf_h, 2, 4) 3448 GEN_VEXT_VF(vfwmsac_vf_w, 4, 8) 3449 3450 static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) 3451 { 3452 return float32_muladd(float16_to_float32(a, true, s), 3453 float16_to_float32(b, true, s), d, 3454 float_muladd_negate_product, s); 3455 } 3456 3457 static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) 3458 { 3459 return float64_muladd(float32_to_float64(a, s), 3460 float32_to_float64(b, s), d, 3461 float_muladd_negate_product, s); 3462 } 3463 3464 RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) 3465 RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32) 3466 GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4) 3467 GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8) 3468 RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) 3469 RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) 3470 GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4) 3471 GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8) 3472 3473 /* Vector Floating-Point Square-Root Instruction */ 3474 /* (TD, T2, TX2) */ 3475 #define OP_UU_H uint16_t, uint16_t, uint16_t 3476 #define OP_UU_W uint32_t, uint32_t, uint32_t 3477 #define OP_UU_D uint64_t, uint64_t, uint64_t 3478 3479 #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ 3480 static void do_##NAME(void *vd, void *vs2, int i, \ 3481 CPURISCVState *env) \ 3482 { \ 3483 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 3484 *((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \ 3485 } 3486 3487 #define GEN_VEXT_V_ENV(NAME, ESZ, DSZ) \ 3488 void HELPER(NAME)(void *vd, void *v0, void *vs2, \ 3489 CPURISCVState *env, uint32_t desc) \ 3490 { \ 3491 uint32_t vm = vext_vm(desc); \ 3492 uint32_t vl = env->vl; \ 3493 uint32_t i; \ 3494 \ 3495 if (vl == 0) { \ 3496 return; \ 3497 } \ 3498 for (i = 0; i < vl; i++) { \ 3499 if (!vm && !vext_elem_mask(v0, i)) { \ 3500 continue; \ 3501 } \ 3502 do_##NAME(vd, vs2, i, env); \ 3503 } \ 3504 } 3505 3506 RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) 3507 RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt) 3508 RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) 3509 GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2) 3510 GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4) 3511 GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8) 3512 3513 /* Vector Floating-Point MIN/MAX Instructions */ 3514 RVVCALL(OPFVV2, vfmin_vv_h, OP_UUU_H, H2, H2, H2, float16_minnum) 3515 RVVCALL(OPFVV2, vfmin_vv_w, OP_UUU_W, H4, H4, H4, float32_minnum) 3516 RVVCALL(OPFVV2, vfmin_vv_d, OP_UUU_D, H8, H8, H8, float64_minnum) 3517 GEN_VEXT_VV_ENV(vfmin_vv_h, 2, 2) 3518 GEN_VEXT_VV_ENV(vfmin_vv_w, 4, 4) 3519 GEN_VEXT_VV_ENV(vfmin_vv_d, 8, 8) 3520 RVVCALL(OPFVF2, vfmin_vf_h, OP_UUU_H, H2, H2, float16_minnum) 3521 RVVCALL(OPFVF2, vfmin_vf_w, OP_UUU_W, H4, H4, float32_minnum) 3522 RVVCALL(OPFVF2, vfmin_vf_d, OP_UUU_D, H8, H8, float64_minnum) 3523 GEN_VEXT_VF(vfmin_vf_h, 2, 2) 3524 GEN_VEXT_VF(vfmin_vf_w, 4, 4) 3525 GEN_VEXT_VF(vfmin_vf_d, 8, 8) 3526 3527 RVVCALL(OPFVV2, vfmax_vv_h, OP_UUU_H, H2, H2, H2, float16_maxnum) 3528 RVVCALL(OPFVV2, vfmax_vv_w, OP_UUU_W, H4, H4, H4, float32_maxnum) 3529 RVVCALL(OPFVV2, vfmax_vv_d, OP_UUU_D, H8, H8, H8, float64_maxnum) 3530 GEN_VEXT_VV_ENV(vfmax_vv_h, 2, 2) 3531 GEN_VEXT_VV_ENV(vfmax_vv_w, 4, 4) 3532 GEN_VEXT_VV_ENV(vfmax_vv_d, 8, 8) 3533 RVVCALL(OPFVF2, vfmax_vf_h, OP_UUU_H, H2, H2, float16_maxnum) 3534 RVVCALL(OPFVF2, vfmax_vf_w, OP_UUU_W, H4, H4, float32_maxnum) 3535 RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum) 3536 GEN_VEXT_VF(vfmax_vf_h, 2, 2) 3537 GEN_VEXT_VF(vfmax_vf_w, 4, 4) 3538 GEN_VEXT_VF(vfmax_vf_d, 8, 8) 3539 3540 /* Vector Floating-Point Sign-Injection Instructions */ 3541 static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s) 3542 { 3543 return deposit64(b, 0, 15, a); 3544 } 3545 3546 static uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s) 3547 { 3548 return deposit64(b, 0, 31, a); 3549 } 3550 3551 static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s) 3552 { 3553 return deposit64(b, 0, 63, a); 3554 } 3555 3556 RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16) 3557 RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32) 3558 RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64) 3559 GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2) 3560 GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4) 3561 GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8) 3562 RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16) 3563 RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32) 3564 RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64) 3565 GEN_VEXT_VF(vfsgnj_vf_h, 2, 2) 3566 GEN_VEXT_VF(vfsgnj_vf_w, 4, 4) 3567 GEN_VEXT_VF(vfsgnj_vf_d, 8, 8) 3568 3569 static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s) 3570 { 3571 return deposit64(~b, 0, 15, a); 3572 } 3573 3574 static uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s) 3575 { 3576 return deposit64(~b, 0, 31, a); 3577 } 3578 3579 static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s) 3580 { 3581 return deposit64(~b, 0, 63, a); 3582 } 3583 3584 RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16) 3585 RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32) 3586 RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64) 3587 GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2) 3588 GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4) 3589 GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8) 3590 RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16) 3591 RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32) 3592 RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64) 3593 GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2) 3594 GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4) 3595 GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8) 3596 3597 static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s) 3598 { 3599 return deposit64(b ^ a, 0, 15, a); 3600 } 3601 3602 static uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s) 3603 { 3604 return deposit64(b ^ a, 0, 31, a); 3605 } 3606 3607 static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s) 3608 { 3609 return deposit64(b ^ a, 0, 63, a); 3610 } 3611 3612 RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16) 3613 RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32) 3614 RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64) 3615 GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2) 3616 GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4) 3617 GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8) 3618 RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16) 3619 RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32) 3620 RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64) 3621 GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2) 3622 GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4) 3623 GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8) 3624 3625 /* Vector Floating-Point Compare Instructions */ 3626 #define GEN_VEXT_CMP_VV_ENV(NAME, ETYPE, H, DO_OP) \ 3627 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 3628 CPURISCVState *env, uint32_t desc) \ 3629 { \ 3630 uint32_t vm = vext_vm(desc); \ 3631 uint32_t vl = env->vl; \ 3632 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 3633 uint32_t i; \ 3634 \ 3635 for (i = 0; i < vl; i++) { \ 3636 ETYPE s1 = *((ETYPE *)vs1 + H(i)); \ 3637 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 3638 if (!vm && !vext_elem_mask(v0, i)) { \ 3639 continue; \ 3640 } \ 3641 vext_set_elem_mask(vd, i, \ 3642 DO_OP(s2, s1, &env->fp_status)); \ 3643 } \ 3644 for (; i < vlmax; i++) { \ 3645 vext_set_elem_mask(vd, i, 0); \ 3646 } \ 3647 } 3648 3649 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_h, uint16_t, H2, float16_eq_quiet) 3650 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_w, uint32_t, H4, float32_eq_quiet) 3651 GEN_VEXT_CMP_VV_ENV(vmfeq_vv_d, uint64_t, H8, float64_eq_quiet) 3652 3653 #define GEN_VEXT_CMP_VF(NAME, ETYPE, H, DO_OP) \ 3654 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ 3655 CPURISCVState *env, uint32_t desc) \ 3656 { \ 3657 uint32_t vm = vext_vm(desc); \ 3658 uint32_t vl = env->vl; \ 3659 uint32_t vlmax = vext_maxsz(desc) / sizeof(ETYPE); \ 3660 uint32_t i; \ 3661 \ 3662 for (i = 0; i < vl; i++) { \ 3663 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 3664 if (!vm && !vext_elem_mask(v0, i)) { \ 3665 continue; \ 3666 } \ 3667 vext_set_elem_mask(vd, i, \ 3668 DO_OP(s2, (ETYPE)s1, &env->fp_status)); \ 3669 } \ 3670 for (; i < vlmax; i++) { \ 3671 vext_set_elem_mask(vd, i, 0); \ 3672 } \ 3673 } 3674 3675 GEN_VEXT_CMP_VF(vmfeq_vf_h, uint16_t, H2, float16_eq_quiet) 3676 GEN_VEXT_CMP_VF(vmfeq_vf_w, uint32_t, H4, float32_eq_quiet) 3677 GEN_VEXT_CMP_VF(vmfeq_vf_d, uint64_t, H8, float64_eq_quiet) 3678 3679 static bool vmfne16(uint16_t a, uint16_t b, float_status *s) 3680 { 3681 FloatRelation compare = float16_compare_quiet(a, b, s); 3682 return compare != float_relation_equal; 3683 } 3684 3685 static bool vmfne32(uint32_t a, uint32_t b, float_status *s) 3686 { 3687 FloatRelation compare = float32_compare_quiet(a, b, s); 3688 return compare != float_relation_equal; 3689 } 3690 3691 static bool vmfne64(uint64_t a, uint64_t b, float_status *s) 3692 { 3693 FloatRelation compare = float64_compare_quiet(a, b, s); 3694 return compare != float_relation_equal; 3695 } 3696 3697 GEN_VEXT_CMP_VV_ENV(vmfne_vv_h, uint16_t, H2, vmfne16) 3698 GEN_VEXT_CMP_VV_ENV(vmfne_vv_w, uint32_t, H4, vmfne32) 3699 GEN_VEXT_CMP_VV_ENV(vmfne_vv_d, uint64_t, H8, vmfne64) 3700 GEN_VEXT_CMP_VF(vmfne_vf_h, uint16_t, H2, vmfne16) 3701 GEN_VEXT_CMP_VF(vmfne_vf_w, uint32_t, H4, vmfne32) 3702 GEN_VEXT_CMP_VF(vmfne_vf_d, uint64_t, H8, vmfne64) 3703 3704 GEN_VEXT_CMP_VV_ENV(vmflt_vv_h, uint16_t, H2, float16_lt) 3705 GEN_VEXT_CMP_VV_ENV(vmflt_vv_w, uint32_t, H4, float32_lt) 3706 GEN_VEXT_CMP_VV_ENV(vmflt_vv_d, uint64_t, H8, float64_lt) 3707 GEN_VEXT_CMP_VF(vmflt_vf_h, uint16_t, H2, float16_lt) 3708 GEN_VEXT_CMP_VF(vmflt_vf_w, uint32_t, H4, float32_lt) 3709 GEN_VEXT_CMP_VF(vmflt_vf_d, uint64_t, H8, float64_lt) 3710 3711 GEN_VEXT_CMP_VV_ENV(vmfle_vv_h, uint16_t, H2, float16_le) 3712 GEN_VEXT_CMP_VV_ENV(vmfle_vv_w, uint32_t, H4, float32_le) 3713 GEN_VEXT_CMP_VV_ENV(vmfle_vv_d, uint64_t, H8, float64_le) 3714 GEN_VEXT_CMP_VF(vmfle_vf_h, uint16_t, H2, float16_le) 3715 GEN_VEXT_CMP_VF(vmfle_vf_w, uint32_t, H4, float32_le) 3716 GEN_VEXT_CMP_VF(vmfle_vf_d, uint64_t, H8, float64_le) 3717 3718 static bool vmfgt16(uint16_t a, uint16_t b, float_status *s) 3719 { 3720 FloatRelation compare = float16_compare(a, b, s); 3721 return compare == float_relation_greater; 3722 } 3723 3724 static bool vmfgt32(uint32_t a, uint32_t b, float_status *s) 3725 { 3726 FloatRelation compare = float32_compare(a, b, s); 3727 return compare == float_relation_greater; 3728 } 3729 3730 static bool vmfgt64(uint64_t a, uint64_t b, float_status *s) 3731 { 3732 FloatRelation compare = float64_compare(a, b, s); 3733 return compare == float_relation_greater; 3734 } 3735 3736 GEN_VEXT_CMP_VF(vmfgt_vf_h, uint16_t, H2, vmfgt16) 3737 GEN_VEXT_CMP_VF(vmfgt_vf_w, uint32_t, H4, vmfgt32) 3738 GEN_VEXT_CMP_VF(vmfgt_vf_d, uint64_t, H8, vmfgt64) 3739 3740 static bool vmfge16(uint16_t a, uint16_t b, float_status *s) 3741 { 3742 FloatRelation compare = float16_compare(a, b, s); 3743 return compare == float_relation_greater || 3744 compare == float_relation_equal; 3745 } 3746 3747 static bool vmfge32(uint32_t a, uint32_t b, float_status *s) 3748 { 3749 FloatRelation compare = float32_compare(a, b, s); 3750 return compare == float_relation_greater || 3751 compare == float_relation_equal; 3752 } 3753 3754 static bool vmfge64(uint64_t a, uint64_t b, float_status *s) 3755 { 3756 FloatRelation compare = float64_compare(a, b, s); 3757 return compare == float_relation_greater || 3758 compare == float_relation_equal; 3759 } 3760 3761 GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) 3762 GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) 3763 GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) 3764 3765 GEN_VEXT_CMP_VV_ENV(vmford_vv_h, uint16_t, H2, !float16_unordered_quiet) 3766 GEN_VEXT_CMP_VV_ENV(vmford_vv_w, uint32_t, H4, !float32_unordered_quiet) 3767 GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet) 3768 GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet) 3769 GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet) 3770 GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet) 3771 3772 /* Vector Floating-Point Classify Instruction */ 3773 #define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ 3774 static void do_##NAME(void *vd, void *vs2, int i) \ 3775 { \ 3776 TX2 s2 = *((T2 *)vs2 + HS2(i)); \ 3777 *((TD *)vd + HD(i)) = OP(s2); \ 3778 } 3779 3780 #define GEN_VEXT_V(NAME, ESZ, DSZ) \ 3781 void HELPER(NAME)(void *vd, void *v0, void *vs2, \ 3782 CPURISCVState *env, uint32_t desc) \ 3783 { \ 3784 uint32_t vm = vext_vm(desc); \ 3785 uint32_t vl = env->vl; \ 3786 uint32_t i; \ 3787 \ 3788 for (i = 0; i < vl; i++) { \ 3789 if (!vm && !vext_elem_mask(v0, i)) { \ 3790 continue; \ 3791 } \ 3792 do_##NAME(vd, vs2, i); \ 3793 } \ 3794 } 3795 3796 target_ulong fclass_h(uint64_t frs1) 3797 { 3798 float16 f = frs1; 3799 bool sign = float16_is_neg(f); 3800 3801 if (float16_is_infinity(f)) { 3802 return sign ? 1 << 0 : 1 << 7; 3803 } else if (float16_is_zero(f)) { 3804 return sign ? 1 << 3 : 1 << 4; 3805 } else if (float16_is_zero_or_denormal(f)) { 3806 return sign ? 1 << 2 : 1 << 5; 3807 } else if (float16_is_any_nan(f)) { 3808 float_status s = { }; /* for snan_bit_is_one */ 3809 return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; 3810 } else { 3811 return sign ? 1 << 1 : 1 << 6; 3812 } 3813 } 3814 3815 target_ulong fclass_s(uint64_t frs1) 3816 { 3817 float32 f = frs1; 3818 bool sign = float32_is_neg(f); 3819 3820 if (float32_is_infinity(f)) { 3821 return sign ? 1 << 0 : 1 << 7; 3822 } else if (float32_is_zero(f)) { 3823 return sign ? 1 << 3 : 1 << 4; 3824 } else if (float32_is_zero_or_denormal(f)) { 3825 return sign ? 1 << 2 : 1 << 5; 3826 } else if (float32_is_any_nan(f)) { 3827 float_status s = { }; /* for snan_bit_is_one */ 3828 return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; 3829 } else { 3830 return sign ? 1 << 1 : 1 << 6; 3831 } 3832 } 3833 3834 target_ulong fclass_d(uint64_t frs1) 3835 { 3836 float64 f = frs1; 3837 bool sign = float64_is_neg(f); 3838 3839 if (float64_is_infinity(f)) { 3840 return sign ? 1 << 0 : 1 << 7; 3841 } else if (float64_is_zero(f)) { 3842 return sign ? 1 << 3 : 1 << 4; 3843 } else if (float64_is_zero_or_denormal(f)) { 3844 return sign ? 1 << 2 : 1 << 5; 3845 } else if (float64_is_any_nan(f)) { 3846 float_status s = { }; /* for snan_bit_is_one */ 3847 return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; 3848 } else { 3849 return sign ? 1 << 1 : 1 << 6; 3850 } 3851 } 3852 3853 RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h) 3854 RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s) 3855 RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d) 3856 GEN_VEXT_V(vfclass_v_h, 2, 2) 3857 GEN_VEXT_V(vfclass_v_w, 4, 4) 3858 GEN_VEXT_V(vfclass_v_d, 8, 8) 3859 3860 /* Vector Floating-Point Merge Instruction */ 3861 #define GEN_VFMERGE_VF(NAME, ETYPE, H) \ 3862 void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ 3863 CPURISCVState *env, uint32_t desc) \ 3864 { \ 3865 uint32_t vm = vext_vm(desc); \ 3866 uint32_t vl = env->vl; \ 3867 uint32_t i; \ 3868 \ 3869 for (i = 0; i < vl; i++) { \ 3870 ETYPE s2 = *((ETYPE *)vs2 + H(i)); \ 3871 *((ETYPE *)vd + H(i)) \ 3872 = (!vm && !vext_elem_mask(v0, i) ? s2 : s1); \ 3873 } \ 3874 } 3875 3876 GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2) 3877 GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4) 3878 GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8) 3879 3880 /* Single-Width Floating-Point/Integer Type-Convert Instructions */ 3881 /* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ 3882 RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16) 3883 RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32) 3884 RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64) 3885 GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2) 3886 GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4) 3887 GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8) 3888 3889 /* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */ 3890 RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16) 3891 RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32) 3892 RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64) 3893 GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2) 3894 GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4) 3895 GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8) 3896 3897 /* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */ 3898 RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16) 3899 RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32) 3900 RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64) 3901 GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2) 3902 GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4) 3903 GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8) 3904 3905 /* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */ 3906 RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16) 3907 RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32) 3908 RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64) 3909 GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2) 3910 GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4) 3911 GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8) 3912 3913 /* Widening Floating-Point/Integer Type-Convert Instructions */ 3914 /* (TD, T2, TX2) */ 3915 #define WOP_UU_H uint32_t, uint16_t, uint16_t 3916 #define WOP_UU_W uint64_t, uint32_t, uint32_t 3917 /* vfwcvt.xu.f.v vd, vs2, vm # Convert float to double-width unsigned integer.*/ 3918 RVVCALL(OPFVV1, vfwcvt_xu_f_v_h, WOP_UU_H, H4, H2, float16_to_uint32) 3919 RVVCALL(OPFVV1, vfwcvt_xu_f_v_w, WOP_UU_W, H8, H4, float32_to_uint64) 3920 GEN_VEXT_V_ENV(vfwcvt_xu_f_v_h, 2, 4) 3921 GEN_VEXT_V_ENV(vfwcvt_xu_f_v_w, 4, 8) 3922 3923 /* vfwcvt.x.f.v vd, vs2, vm # Convert float to double-width signed integer. */ 3924 RVVCALL(OPFVV1, vfwcvt_x_f_v_h, WOP_UU_H, H4, H2, float16_to_int32) 3925 RVVCALL(OPFVV1, vfwcvt_x_f_v_w, WOP_UU_W, H8, H4, float32_to_int64) 3926 GEN_VEXT_V_ENV(vfwcvt_x_f_v_h, 2, 4) 3927 GEN_VEXT_V_ENV(vfwcvt_x_f_v_w, 4, 8) 3928 3929 /* vfwcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to double-width float */ 3930 RVVCALL(OPFVV1, vfwcvt_f_xu_v_h, WOP_UU_H, H4, H2, uint16_to_float32) 3931 RVVCALL(OPFVV1, vfwcvt_f_xu_v_w, WOP_UU_W, H8, H4, uint32_to_float64) 3932 GEN_VEXT_V_ENV(vfwcvt_f_xu_v_h, 2, 4) 3933 GEN_VEXT_V_ENV(vfwcvt_f_xu_v_w, 4, 8) 3934 3935 /* vfwcvt.f.x.v vd, vs2, vm # Convert integer to double-width float. */ 3936 RVVCALL(OPFVV1, vfwcvt_f_x_v_h, WOP_UU_H, H4, H2, int16_to_float32) 3937 RVVCALL(OPFVV1, vfwcvt_f_x_v_w, WOP_UU_W, H8, H4, int32_to_float64) 3938 GEN_VEXT_V_ENV(vfwcvt_f_x_v_h, 2, 4) 3939 GEN_VEXT_V_ENV(vfwcvt_f_x_v_w, 4, 8) 3940 3941 /* 3942 * vfwcvt.f.f.v vd, vs2, vm # 3943 * Convert single-width float to double-width float. 3944 */ 3945 static uint32_t vfwcvtffv16(uint16_t a, float_status *s) 3946 { 3947 return float16_to_float32(a, true, s); 3948 } 3949 3950 RVVCALL(OPFVV1, vfwcvt_f_f_v_h, WOP_UU_H, H4, H2, vfwcvtffv16) 3951 RVVCALL(OPFVV1, vfwcvt_f_f_v_w, WOP_UU_W, H8, H4, float32_to_float64) 3952 GEN_VEXT_V_ENV(vfwcvt_f_f_v_h, 2, 4) 3953 GEN_VEXT_V_ENV(vfwcvt_f_f_v_w, 4, 8) 3954 3955 /* Narrowing Floating-Point/Integer Type-Convert Instructions */ 3956 /* (TD, T2, TX2) */ 3957 #define NOP_UU_H uint16_t, uint32_t, uint32_t 3958 #define NOP_UU_W uint32_t, uint64_t, uint64_t 3959 /* vfncvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ 3960 RVVCALL(OPFVV1, vfncvt_xu_f_v_h, NOP_UU_H, H2, H4, float32_to_uint16) 3961 RVVCALL(OPFVV1, vfncvt_xu_f_v_w, NOP_UU_W, H4, H8, float64_to_uint32) 3962 GEN_VEXT_V_ENV(vfncvt_xu_f_v_h, 2, 2) 3963 GEN_VEXT_V_ENV(vfncvt_xu_f_v_w, 4, 4) 3964 3965 /* vfncvt.x.f.v vd, vs2, vm # Convert double-width float to signed integer. */ 3966 RVVCALL(OPFVV1, vfncvt_x_f_v_h, NOP_UU_H, H2, H4, float32_to_int16) 3967 RVVCALL(OPFVV1, vfncvt_x_f_v_w, NOP_UU_W, H4, H8, float64_to_int32) 3968 GEN_VEXT_V_ENV(vfncvt_x_f_v_h, 2, 2) 3969 GEN_VEXT_V_ENV(vfncvt_x_f_v_w, 4, 4) 3970 3971 /* vfncvt.f.xu.v vd, vs2, vm # Convert double-width unsigned integer to float */ 3972 RVVCALL(OPFVV1, vfncvt_f_xu_v_h, NOP_UU_H, H2, H4, uint32_to_float16) 3973 RVVCALL(OPFVV1, vfncvt_f_xu_v_w, NOP_UU_W, H4, H8, uint64_to_float32) 3974 GEN_VEXT_V_ENV(vfncvt_f_xu_v_h, 2, 2) 3975 GEN_VEXT_V_ENV(vfncvt_f_xu_v_w, 4, 4) 3976 3977 /* vfncvt.f.x.v vd, vs2, vm # Convert double-width integer to float. */ 3978 RVVCALL(OPFVV1, vfncvt_f_x_v_h, NOP_UU_H, H2, H4, int32_to_float16) 3979 RVVCALL(OPFVV1, vfncvt_f_x_v_w, NOP_UU_W, H4, H8, int64_to_float32) 3980 GEN_VEXT_V_ENV(vfncvt_f_x_v_h, 2, 2) 3981 GEN_VEXT_V_ENV(vfncvt_f_x_v_w, 4, 4) 3982 3983 /* vfncvt.f.f.v vd, vs2, vm # Convert double float to single-width float. */ 3984 static uint16_t vfncvtffv16(uint32_t a, float_status *s) 3985 { 3986 return float32_to_float16(a, true, s); 3987 } 3988 3989 RVVCALL(OPFVV1, vfncvt_f_f_v_h, NOP_UU_H, H2, H4, vfncvtffv16) 3990 RVVCALL(OPFVV1, vfncvt_f_f_v_w, NOP_UU_W, H4, H8, float64_to_float32) 3991 GEN_VEXT_V_ENV(vfncvt_f_f_v_h, 2, 2) 3992 GEN_VEXT_V_ENV(vfncvt_f_f_v_w, 4, 4) 3993 3994 /* 3995 *** Vector Reduction Operations 3996 */ 3997 /* Vector Single-Width Integer Reduction Instructions */ 3998 #define GEN_VEXT_RED(NAME, TD, TS2, HD, HS2, OP) \ 3999 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 4000 void *vs2, CPURISCVState *env, uint32_t desc) \ 4001 { \ 4002 uint32_t vm = vext_vm(desc); \ 4003 uint32_t vl = env->vl; \ 4004 uint32_t i; \ 4005 TD s1 = *((TD *)vs1 + HD(0)); \ 4006 \ 4007 for (i = 0; i < vl; i++) { \ 4008 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 4009 if (!vm && !vext_elem_mask(v0, i)) { \ 4010 continue; \ 4011 } \ 4012 s1 = OP(s1, (TD)s2); \ 4013 } \ 4014 *((TD *)vd + HD(0)) = s1; \ 4015 } 4016 4017 /* vd[0] = sum(vs1[0], vs2[*]) */ 4018 GEN_VEXT_RED(vredsum_vs_b, int8_t, int8_t, H1, H1, DO_ADD) 4019 GEN_VEXT_RED(vredsum_vs_h, int16_t, int16_t, H2, H2, DO_ADD) 4020 GEN_VEXT_RED(vredsum_vs_w, int32_t, int32_t, H4, H4, DO_ADD) 4021 GEN_VEXT_RED(vredsum_vs_d, int64_t, int64_t, H8, H8, DO_ADD) 4022 4023 /* vd[0] = maxu(vs1[0], vs2[*]) */ 4024 GEN_VEXT_RED(vredmaxu_vs_b, uint8_t, uint8_t, H1, H1, DO_MAX) 4025 GEN_VEXT_RED(vredmaxu_vs_h, uint16_t, uint16_t, H2, H2, DO_MAX) 4026 GEN_VEXT_RED(vredmaxu_vs_w, uint32_t, uint32_t, H4, H4, DO_MAX) 4027 GEN_VEXT_RED(vredmaxu_vs_d, uint64_t, uint64_t, H8, H8, DO_MAX) 4028 4029 /* vd[0] = max(vs1[0], vs2[*]) */ 4030 GEN_VEXT_RED(vredmax_vs_b, int8_t, int8_t, H1, H1, DO_MAX) 4031 GEN_VEXT_RED(vredmax_vs_h, int16_t, int16_t, H2, H2, DO_MAX) 4032 GEN_VEXT_RED(vredmax_vs_w, int32_t, int32_t, H4, H4, DO_MAX) 4033 GEN_VEXT_RED(vredmax_vs_d, int64_t, int64_t, H8, H8, DO_MAX) 4034 4035 /* vd[0] = minu(vs1[0], vs2[*]) */ 4036 GEN_VEXT_RED(vredminu_vs_b, uint8_t, uint8_t, H1, H1, DO_MIN) 4037 GEN_VEXT_RED(vredminu_vs_h, uint16_t, uint16_t, H2, H2, DO_MIN) 4038 GEN_VEXT_RED(vredminu_vs_w, uint32_t, uint32_t, H4, H4, DO_MIN) 4039 GEN_VEXT_RED(vredminu_vs_d, uint64_t, uint64_t, H8, H8, DO_MIN) 4040 4041 /* vd[0] = min(vs1[0], vs2[*]) */ 4042 GEN_VEXT_RED(vredmin_vs_b, int8_t, int8_t, H1, H1, DO_MIN) 4043 GEN_VEXT_RED(vredmin_vs_h, int16_t, int16_t, H2, H2, DO_MIN) 4044 GEN_VEXT_RED(vredmin_vs_w, int32_t, int32_t, H4, H4, DO_MIN) 4045 GEN_VEXT_RED(vredmin_vs_d, int64_t, int64_t, H8, H8, DO_MIN) 4046 4047 /* vd[0] = and(vs1[0], vs2[*]) */ 4048 GEN_VEXT_RED(vredand_vs_b, int8_t, int8_t, H1, H1, DO_AND) 4049 GEN_VEXT_RED(vredand_vs_h, int16_t, int16_t, H2, H2, DO_AND) 4050 GEN_VEXT_RED(vredand_vs_w, int32_t, int32_t, H4, H4, DO_AND) 4051 GEN_VEXT_RED(vredand_vs_d, int64_t, int64_t, H8, H8, DO_AND) 4052 4053 /* vd[0] = or(vs1[0], vs2[*]) */ 4054 GEN_VEXT_RED(vredor_vs_b, int8_t, int8_t, H1, H1, DO_OR) 4055 GEN_VEXT_RED(vredor_vs_h, int16_t, int16_t, H2, H2, DO_OR) 4056 GEN_VEXT_RED(vredor_vs_w, int32_t, int32_t, H4, H4, DO_OR) 4057 GEN_VEXT_RED(vredor_vs_d, int64_t, int64_t, H8, H8, DO_OR) 4058 4059 /* vd[0] = xor(vs1[0], vs2[*]) */ 4060 GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR) 4061 GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR) 4062 GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR) 4063 GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR) 4064 4065 /* Vector Widening Integer Reduction Instructions */ 4066 /* signed sum reduction into double-width accumulator */ 4067 GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD) 4068 GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD) 4069 GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD) 4070 4071 /* Unsigned sum reduction into double-width accumulator */ 4072 GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD) 4073 GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD) 4074 GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD) 4075 4076 /* Vector Single-Width Floating-Point Reduction Instructions */ 4077 #define GEN_VEXT_FRED(NAME, TD, TS2, HD, HS2, OP) \ 4078 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 4079 void *vs2, CPURISCVState *env, \ 4080 uint32_t desc) \ 4081 { \ 4082 uint32_t vm = vext_vm(desc); \ 4083 uint32_t vl = env->vl; \ 4084 uint32_t i; \ 4085 TD s1 = *((TD *)vs1 + HD(0)); \ 4086 \ 4087 for (i = 0; i < vl; i++) { \ 4088 TS2 s2 = *((TS2 *)vs2 + HS2(i)); \ 4089 if (!vm && !vext_elem_mask(v0, i)) { \ 4090 continue; \ 4091 } \ 4092 s1 = OP(s1, (TD)s2, &env->fp_status); \ 4093 } \ 4094 *((TD *)vd + HD(0)) = s1; \ 4095 } 4096 4097 /* Unordered sum */ 4098 GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) 4099 GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) 4100 GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) 4101 4102 /* Maximum value */ 4103 GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maxnum) 4104 GEN_VEXT_FRED(vfredmax_vs_w, uint32_t, uint32_t, H4, H4, float32_maxnum) 4105 GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum) 4106 4107 /* Minimum value */ 4108 GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum) 4109 GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum) 4110 GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum) 4111 4112 /* Vector Widening Floating-Point Reduction Instructions */ 4113 /* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ 4114 void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, 4115 void *vs2, CPURISCVState *env, uint32_t desc) 4116 { 4117 uint32_t vm = vext_vm(desc); 4118 uint32_t vl = env->vl; 4119 uint32_t i; 4120 uint32_t s1 = *((uint32_t *)vs1 + H4(0)); 4121 4122 for (i = 0; i < vl; i++) { 4123 uint16_t s2 = *((uint16_t *)vs2 + H2(i)); 4124 if (!vm && !vext_elem_mask(v0, i)) { 4125 continue; 4126 } 4127 s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status), 4128 &env->fp_status); 4129 } 4130 *((uint32_t *)vd + H4(0)) = s1; 4131 } 4132 4133 void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, 4134 void *vs2, CPURISCVState *env, uint32_t desc) 4135 { 4136 uint32_t vm = vext_vm(desc); 4137 uint32_t vl = env->vl; 4138 uint32_t i; 4139 uint64_t s1 = *((uint64_t *)vs1); 4140 4141 for (i = 0; i < vl; i++) { 4142 uint32_t s2 = *((uint32_t *)vs2 + H4(i)); 4143 if (!vm && !vext_elem_mask(v0, i)) { 4144 continue; 4145 } 4146 s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status), 4147 &env->fp_status); 4148 } 4149 *((uint64_t *)vd) = s1; 4150 } 4151 4152 /* 4153 *** Vector Mask Operations 4154 */ 4155 /* Vector Mask-Register Logical Instructions */ 4156 #define GEN_VEXT_MASK_VV(NAME, OP) \ 4157 void HELPER(NAME)(void *vd, void *v0, void *vs1, \ 4158 void *vs2, CPURISCVState *env, \ 4159 uint32_t desc) \ 4160 { \ 4161 uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ 4162 uint32_t vl = env->vl; \ 4163 uint32_t i; \ 4164 int a, b; \ 4165 \ 4166 for (i = 0; i < vl; i++) { \ 4167 a = vext_elem_mask(vs1, i); \ 4168 b = vext_elem_mask(vs2, i); \ 4169 vext_set_elem_mask(vd, i, OP(b, a)); \ 4170 } \ 4171 for (; i < vlmax; i++) { \ 4172 vext_set_elem_mask(vd, i, 0); \ 4173 } \ 4174 } 4175 4176 #define DO_NAND(N, M) (!(N & M)) 4177 #define DO_ANDNOT(N, M) (N & !M) 4178 #define DO_NOR(N, M) (!(N | M)) 4179 #define DO_ORNOT(N, M) (N | !M) 4180 #define DO_XNOR(N, M) (!(N ^ M)) 4181 4182 GEN_VEXT_MASK_VV(vmand_mm, DO_AND) 4183 GEN_VEXT_MASK_VV(vmnand_mm, DO_NAND) 4184 GEN_VEXT_MASK_VV(vmandnot_mm, DO_ANDNOT) 4185 GEN_VEXT_MASK_VV(vmxor_mm, DO_XOR) 4186 GEN_VEXT_MASK_VV(vmor_mm, DO_OR) 4187 GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) 4188 GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) 4189 GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) 4190 4191 /* Vector mask population count vmpopc */ 4192 target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, 4193 uint32_t desc) 4194 { 4195 target_ulong cnt = 0; 4196 uint32_t vm = vext_vm(desc); 4197 uint32_t vl = env->vl; 4198 int i; 4199 4200 for (i = 0; i < vl; i++) { 4201 if (vm || vext_elem_mask(v0, i)) { 4202 if (vext_elem_mask(vs2, i)) { 4203 cnt++; 4204 } 4205 } 4206 } 4207 return cnt; 4208 } 4209 4210 /* vmfirst find-first-set mask bit*/ 4211 target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env, 4212 uint32_t desc) 4213 { 4214 uint32_t vm = vext_vm(desc); 4215 uint32_t vl = env->vl; 4216 int i; 4217 4218 for (i = 0; i < vl; i++) { 4219 if (vm || vext_elem_mask(v0, i)) { 4220 if (vext_elem_mask(vs2, i)) { 4221 return i; 4222 } 4223 } 4224 } 4225 return -1LL; 4226 } 4227 4228 enum set_mask_type { 4229 ONLY_FIRST = 1, 4230 INCLUDE_FIRST, 4231 BEFORE_FIRST, 4232 }; 4233 4234 static void vmsetm(void *vd, void *v0, void *vs2, CPURISCVState *env, 4235 uint32_t desc, enum set_mask_type type) 4236 { 4237 uint32_t vlmax = env_archcpu(env)->cfg.vlen; 4238 uint32_t vm = vext_vm(desc); 4239 uint32_t vl = env->vl; 4240 int i; 4241 bool first_mask_bit = false; 4242 4243 for (i = 0; i < vl; i++) { 4244 if (!vm && !vext_elem_mask(v0, i)) { 4245 continue; 4246 } 4247 /* write a zero to all following active elements */ 4248 if (first_mask_bit) { 4249 vext_set_elem_mask(vd, i, 0); 4250 continue; 4251 } 4252 if (vext_elem_mask(vs2, i)) { 4253 first_mask_bit = true; 4254 if (type == BEFORE_FIRST) { 4255 vext_set_elem_mask(vd, i, 0); 4256 } else { 4257 vext_set_elem_mask(vd, i, 1); 4258 } 4259 } else { 4260 if (type == ONLY_FIRST) { 4261 vext_set_elem_mask(vd, i, 0); 4262 } else { 4263 vext_set_elem_mask(vd, i, 1); 4264 } 4265 } 4266 } 4267 for (; i < vlmax; i++) { 4268 vext_set_elem_mask(vd, i, 0); 4269 } 4270 } 4271 4272 void HELPER(vmsbf_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, 4273 uint32_t desc) 4274 { 4275 vmsetm(vd, v0, vs2, env, desc, BEFORE_FIRST); 4276 } 4277 4278 void HELPER(vmsif_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, 4279 uint32_t desc) 4280 { 4281 vmsetm(vd, v0, vs2, env, desc, INCLUDE_FIRST); 4282 } 4283 4284 void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env, 4285 uint32_t desc) 4286 { 4287 vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST); 4288 } 4289 4290 /* Vector Iota Instruction */ 4291 #define GEN_VEXT_VIOTA_M(NAME, ETYPE, H) \ 4292 void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \ 4293 uint32_t desc) \ 4294 { \ 4295 uint32_t vm = vext_vm(desc); \ 4296 uint32_t vl = env->vl; \ 4297 uint32_t sum = 0; \ 4298 int i; \ 4299 \ 4300 for (i = 0; i < vl; i++) { \ 4301 if (!vm && !vext_elem_mask(v0, i)) { \ 4302 continue; \ 4303 } \ 4304 *((ETYPE *)vd + H(i)) = sum; \ 4305 if (vext_elem_mask(vs2, i)) { \ 4306 sum++; \ 4307 } \ 4308 } \ 4309 } 4310 4311 GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1) 4312 GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2) 4313 GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4) 4314 GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8) 4315 4316 /* Vector Element Index Instruction */ 4317 #define GEN_VEXT_VID_V(NAME, ETYPE, H) \ 4318 void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \ 4319 { \ 4320 uint32_t vm = vext_vm(desc); \ 4321 uint32_t vl = env->vl; \ 4322 int i; \ 4323 \ 4324 for (i = 0; i < vl; i++) { \ 4325 if (!vm && !vext_elem_mask(v0, i)) { \ 4326 continue; \ 4327 } \ 4328 *((ETYPE *)vd + H(i)) = i; \ 4329 } \ 4330 } 4331 4332 GEN_VEXT_VID_V(vid_v_b, uint8_t, H1) 4333 GEN_VEXT_VID_V(vid_v_h, uint16_t, H2) 4334 GEN_VEXT_VID_V(vid_v_w, uint32_t, H4) 4335 GEN_VEXT_VID_V(vid_v_d, uint64_t, H8) 4336 4337 /* 4338 *** Vector Permutation Instructions 4339 */ 4340 4341 /* Vector Slide Instructions */ 4342 #define GEN_VEXT_VSLIDEUP_VX(NAME, ETYPE, H) \ 4343 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 4344 CPURISCVState *env, uint32_t desc) \ 4345 { \ 4346 uint32_t vm = vext_vm(desc); \ 4347 uint32_t vl = env->vl; \ 4348 target_ulong offset = s1, i; \ 4349 \ 4350 for (i = offset; i < vl; i++) { \ 4351 if (!vm && !vext_elem_mask(v0, i)) { \ 4352 continue; \ 4353 } \ 4354 *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - offset)); \ 4355 } \ 4356 } 4357 4358 /* vslideup.vx vd, vs2, rs1, vm # vd[i+rs1] = vs2[i] */ 4359 GEN_VEXT_VSLIDEUP_VX(vslideup_vx_b, uint8_t, H1) 4360 GEN_VEXT_VSLIDEUP_VX(vslideup_vx_h, uint16_t, H2) 4361 GEN_VEXT_VSLIDEUP_VX(vslideup_vx_w, uint32_t, H4) 4362 GEN_VEXT_VSLIDEUP_VX(vslideup_vx_d, uint64_t, H8) 4363 4364 #define GEN_VEXT_VSLIDEDOWN_VX(NAME, ETYPE, H) \ 4365 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 4366 CPURISCVState *env, uint32_t desc) \ 4367 { \ 4368 uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ 4369 uint32_t vm = vext_vm(desc); \ 4370 uint32_t vl = env->vl; \ 4371 target_ulong offset = s1, i; \ 4372 \ 4373 for (i = 0; i < vl; ++i) { \ 4374 target_ulong j = i + offset; \ 4375 if (!vm && !vext_elem_mask(v0, i)) { \ 4376 continue; \ 4377 } \ 4378 *((ETYPE *)vd + H(i)) = j >= vlmax ? 0 : *((ETYPE *)vs2 + H(j)); \ 4379 } \ 4380 } 4381 4382 /* vslidedown.vx vd, vs2, rs1, vm # vd[i] = vs2[i+rs1] */ 4383 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_b, uint8_t, H1) 4384 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_h, uint16_t, H2) 4385 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_w, uint32_t, H4) 4386 GEN_VEXT_VSLIDEDOWN_VX(vslidedown_vx_d, uint64_t, H8) 4387 4388 #define GEN_VEXT_VSLIDE1UP_VX(NAME, ETYPE, H) \ 4389 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 4390 CPURISCVState *env, uint32_t desc) \ 4391 { \ 4392 uint32_t vm = vext_vm(desc); \ 4393 uint32_t vl = env->vl; \ 4394 uint32_t i; \ 4395 \ 4396 for (i = 0; i < vl; i++) { \ 4397 if (!vm && !vext_elem_mask(v0, i)) { \ 4398 continue; \ 4399 } \ 4400 if (i == 0) { \ 4401 *((ETYPE *)vd + H(i)) = s1; \ 4402 } else { \ 4403 *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i - 1)); \ 4404 } \ 4405 } \ 4406 } 4407 4408 /* vslide1up.vx vd, vs2, rs1, vm # vd[0]=x[rs1], vd[i+1] = vs2[i] */ 4409 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_b, uint8_t, H1) 4410 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_h, uint16_t, H2) 4411 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_w, uint32_t, H4) 4412 GEN_VEXT_VSLIDE1UP_VX(vslide1up_vx_d, uint64_t, H8) 4413 4414 #define GEN_VEXT_VSLIDE1DOWN_VX(NAME, ETYPE, H) \ 4415 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 4416 CPURISCVState *env, uint32_t desc) \ 4417 { \ 4418 uint32_t vm = vext_vm(desc); \ 4419 uint32_t vl = env->vl; \ 4420 uint32_t i; \ 4421 \ 4422 for (i = 0; i < vl; i++) { \ 4423 if (!vm && !vext_elem_mask(v0, i)) { \ 4424 continue; \ 4425 } \ 4426 if (i == vl - 1) { \ 4427 *((ETYPE *)vd + H(i)) = s1; \ 4428 } else { \ 4429 *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(i + 1)); \ 4430 } \ 4431 } \ 4432 } 4433 4434 /* vslide1down.vx vd, vs2, rs1, vm # vd[i] = vs2[i+1], vd[vl-1]=x[rs1] */ 4435 GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_b, uint8_t, H1) 4436 GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_h, uint16_t, H2) 4437 GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_w, uint32_t, H4) 4438 GEN_VEXT_VSLIDE1DOWN_VX(vslide1down_vx_d, uint64_t, H8) 4439 4440 /* Vector Register Gather Instruction */ 4441 #define GEN_VEXT_VRGATHER_VV(NAME, ETYPE, H) \ 4442 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 4443 CPURISCVState *env, uint32_t desc) \ 4444 { \ 4445 uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ 4446 uint32_t vm = vext_vm(desc); \ 4447 uint32_t vl = env->vl; \ 4448 uint64_t index; \ 4449 uint32_t i; \ 4450 \ 4451 for (i = 0; i < vl; i++) { \ 4452 if (!vm && !vext_elem_mask(v0, i)) { \ 4453 continue; \ 4454 } \ 4455 index = *((ETYPE *)vs1 + H(i)); \ 4456 if (index >= vlmax) { \ 4457 *((ETYPE *)vd + H(i)) = 0; \ 4458 } else { \ 4459 *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ 4460 } \ 4461 } \ 4462 } 4463 4464 /* vd[i] = (vs1[i] >= VLMAX) ? 0 : vs2[vs1[i]]; */ 4465 GEN_VEXT_VRGATHER_VV(vrgather_vv_b, uint8_t, H1) 4466 GEN_VEXT_VRGATHER_VV(vrgather_vv_h, uint16_t, H2) 4467 GEN_VEXT_VRGATHER_VV(vrgather_vv_w, uint32_t, H4) 4468 GEN_VEXT_VRGATHER_VV(vrgather_vv_d, uint64_t, H8) 4469 4470 #define GEN_VEXT_VRGATHER_VX(NAME, ETYPE, H) \ 4471 void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ 4472 CPURISCVState *env, uint32_t desc) \ 4473 { \ 4474 uint32_t vlmax = env_archcpu(env)->cfg.vlen; \ 4475 uint32_t vm = vext_vm(desc); \ 4476 uint32_t vl = env->vl; \ 4477 uint64_t index = s1; \ 4478 uint32_t i; \ 4479 \ 4480 for (i = 0; i < vl; i++) { \ 4481 if (!vm && !vext_elem_mask(v0, i)) { \ 4482 continue; \ 4483 } \ 4484 if (index >= vlmax) { \ 4485 *((ETYPE *)vd + H(i)) = 0; \ 4486 } else { \ 4487 *((ETYPE *)vd + H(i)) = *((ETYPE *)vs2 + H(index)); \ 4488 } \ 4489 } \ 4490 } 4491 4492 /* vd[i] = (x[rs1] >= VLMAX) ? 0 : vs2[rs1] */ 4493 GEN_VEXT_VRGATHER_VX(vrgather_vx_b, uint8_t, H1) 4494 GEN_VEXT_VRGATHER_VX(vrgather_vx_h, uint16_t, H2) 4495 GEN_VEXT_VRGATHER_VX(vrgather_vx_w, uint32_t, H4) 4496 GEN_VEXT_VRGATHER_VX(vrgather_vx_d, uint64_t, H8) 4497 4498 /* Vector Compress Instruction */ 4499 #define GEN_VEXT_VCOMPRESS_VM(NAME, ETYPE, H) \ 4500 void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ 4501 CPURISCVState *env, uint32_t desc) \ 4502 { \ 4503 uint32_t vl = env->vl; \ 4504 uint32_t num = 0, i; \ 4505 \ 4506 for (i = 0; i < vl; i++) { \ 4507 if (!vext_elem_mask(vs1, i)) { \ 4508 continue; \ 4509 } \ 4510 *((ETYPE *)vd + H(num)) = *((ETYPE *)vs2 + H(i)); \ 4511 num++; \ 4512 } \ 4513 } 4514 4515 /* Compress into vd elements of vs2 where vs1 is enabled */ 4516 GEN_VEXT_VCOMPRESS_VM(vcompress_vm_b, uint8_t, H1) 4517 GEN_VEXT_VCOMPRESS_VM(vcompress_vm_h, uint16_t, H2) 4518 GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) 4519 GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) 4520