1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 uint8_t ntemp; 105 CPUState *cs; 106 TCGv zero; 107 /* Space for 3 operands plus 1 extra for address computation. */ 108 TCGv temp[4]; 109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 110 TCGv_i64 ftemp[4]; 111 uint8_t nftemp; 112 /* PointerMasking extension */ 113 bool pm_mask_enabled; 114 bool pm_base_enabled; 115 /* TCG of the current insn_start */ 116 TCGOp *insn_start; 117 } DisasContext; 118 119 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 120 { 121 return ctx->misa_ext & ext; 122 } 123 124 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 125 { 126 return true; 127 } 128 129 #define MATERIALISE_EXT_PREDICATE(ext) \ 130 static bool has_ ## ext ## _p(DisasContext *ctx) \ 131 { \ 132 return ctx->cfg_ptr->ext_ ## ext ; \ 133 } 134 135 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 136 137 #ifdef TARGET_RISCV32 138 #define get_xl(ctx) MXL_RV32 139 #elif defined(CONFIG_USER_ONLY) 140 #define get_xl(ctx) MXL_RV64 141 #else 142 #define get_xl(ctx) ((ctx)->xl) 143 #endif 144 145 /* The word size for this machine mode. */ 146 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 147 { 148 return 16 << get_xl(ctx); 149 } 150 151 /* The operation length, as opposed to the xlen. */ 152 #ifdef TARGET_RISCV32 153 #define get_ol(ctx) MXL_RV32 154 #else 155 #define get_ol(ctx) ((ctx)->ol) 156 #endif 157 158 static inline int get_olen(DisasContext *ctx) 159 { 160 return 16 << get_ol(ctx); 161 } 162 163 /* The maximum register length */ 164 #ifdef TARGET_RISCV32 165 #define get_xl_max(ctx) MXL_RV32 166 #else 167 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 168 #endif 169 170 /* 171 * RISC-V requires NaN-boxing of narrower width floating point values. 172 * This applies when a 32-bit value is assigned to a 64-bit FP register. 173 * For consistency and simplicity, we nanbox results even when the RVD 174 * extension is not present. 175 */ 176 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 177 { 178 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 179 } 180 181 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 182 { 183 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 184 } 185 186 /* 187 * A narrow n-bit operation, where n < FLEN, checks that input operands 188 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 189 * If so, the least-significant bits of the input are used, otherwise the 190 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 191 * 192 * Here, the result is always nan-boxed, even the canonical nan. 193 */ 194 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 195 { 196 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 197 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 198 199 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 200 tcg_temp_free_i64(t_max); 201 tcg_temp_free_i64(t_nan); 202 } 203 204 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 205 { 206 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 207 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 208 209 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 210 } 211 212 static void decode_save_opc(DisasContext *ctx) 213 { 214 assert(ctx->insn_start != NULL); 215 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 216 ctx->insn_start = NULL; 217 } 218 219 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 220 { 221 if (get_xl(ctx) == MXL_RV32) { 222 dest = (int32_t)dest; 223 } 224 tcg_gen_movi_tl(cpu_pc, dest); 225 } 226 227 static void gen_set_pc(DisasContext *ctx, TCGv dest) 228 { 229 if (get_xl(ctx) == MXL_RV32) { 230 tcg_gen_ext32s_tl(cpu_pc, dest); 231 } else { 232 tcg_gen_mov_tl(cpu_pc, dest); 233 } 234 } 235 236 static void generate_exception(DisasContext *ctx, int excp) 237 { 238 gen_set_pc_imm(ctx, ctx->base.pc_next); 239 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 240 ctx->base.is_jmp = DISAS_NORETURN; 241 } 242 243 static void gen_exception_illegal(DisasContext *ctx) 244 { 245 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 246 offsetof(CPURISCVState, bins)); 247 if (ctx->virt_inst_excp) { 248 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 249 } else { 250 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 251 } 252 } 253 254 static void gen_exception_inst_addr_mis(DisasContext *ctx) 255 { 256 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 257 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 258 } 259 260 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 261 { 262 if (translator_use_goto_tb(&ctx->base, dest)) { 263 tcg_gen_goto_tb(n); 264 gen_set_pc_imm(ctx, dest); 265 tcg_gen_exit_tb(ctx->base.tb, n); 266 } else { 267 gen_set_pc_imm(ctx, dest); 268 tcg_gen_lookup_and_goto_ptr(); 269 } 270 } 271 272 /* 273 * Wrappers for getting reg values. 274 * 275 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 276 * constant zero as a source, and an uninitialized sink as destination. 277 * 278 * Further, we may provide an extension for word operations. 279 */ 280 static TCGv temp_new(DisasContext *ctx) 281 { 282 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 283 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 284 } 285 286 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 287 { 288 TCGv t; 289 290 if (reg_num == 0) { 291 return ctx->zero; 292 } 293 294 switch (get_ol(ctx)) { 295 case MXL_RV32: 296 switch (ext) { 297 case EXT_NONE: 298 break; 299 case EXT_SIGN: 300 t = temp_new(ctx); 301 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 302 return t; 303 case EXT_ZERO: 304 t = temp_new(ctx); 305 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 306 return t; 307 default: 308 g_assert_not_reached(); 309 } 310 break; 311 case MXL_RV64: 312 case MXL_RV128: 313 break; 314 default: 315 g_assert_not_reached(); 316 } 317 return cpu_gpr[reg_num]; 318 } 319 320 static TCGv get_gprh(DisasContext *ctx, int reg_num) 321 { 322 assert(get_xl(ctx) == MXL_RV128); 323 if (reg_num == 0) { 324 return ctx->zero; 325 } 326 return cpu_gprh[reg_num]; 327 } 328 329 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 330 { 331 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 332 return temp_new(ctx); 333 } 334 return cpu_gpr[reg_num]; 335 } 336 337 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 338 { 339 if (reg_num == 0) { 340 return temp_new(ctx); 341 } 342 return cpu_gprh[reg_num]; 343 } 344 345 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 346 { 347 if (reg_num != 0) { 348 switch (get_ol(ctx)) { 349 case MXL_RV32: 350 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 351 break; 352 case MXL_RV64: 353 case MXL_RV128: 354 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 360 if (get_xl_max(ctx) == MXL_RV128) { 361 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 362 } 363 } 364 } 365 366 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 367 { 368 if (reg_num != 0) { 369 switch (get_ol(ctx)) { 370 case MXL_RV32: 371 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 372 break; 373 case MXL_RV64: 374 case MXL_RV128: 375 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 376 break; 377 default: 378 g_assert_not_reached(); 379 } 380 381 if (get_xl_max(ctx) == MXL_RV128) { 382 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 383 } 384 } 385 } 386 387 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 388 { 389 assert(get_ol(ctx) == MXL_RV128); 390 if (reg_num != 0) { 391 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 392 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 393 } 394 } 395 396 static TCGv_i64 ftemp_new(DisasContext *ctx) 397 { 398 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 399 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 400 } 401 402 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 403 { 404 if (!ctx->cfg_ptr->ext_zfinx) { 405 return cpu_fpr[reg_num]; 406 } 407 408 if (reg_num == 0) { 409 return tcg_constant_i64(0); 410 } 411 switch (get_xl(ctx)) { 412 case MXL_RV32: 413 #ifdef TARGET_RISCV32 414 { 415 TCGv_i64 t = ftemp_new(ctx); 416 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 417 return t; 418 } 419 #else 420 /* fall through */ 421 case MXL_RV64: 422 return cpu_gpr[reg_num]; 423 #endif 424 default: 425 g_assert_not_reached(); 426 } 427 } 428 429 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 430 { 431 if (!ctx->cfg_ptr->ext_zfinx) { 432 return cpu_fpr[reg_num]; 433 } 434 435 if (reg_num == 0) { 436 return tcg_constant_i64(0); 437 } 438 switch (get_xl(ctx)) { 439 case MXL_RV32: 440 { 441 TCGv_i64 t = ftemp_new(ctx); 442 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 443 return t; 444 } 445 #ifdef TARGET_RISCV64 446 case MXL_RV64: 447 return cpu_gpr[reg_num]; 448 #endif 449 default: 450 g_assert_not_reached(); 451 } 452 } 453 454 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 455 { 456 if (!ctx->cfg_ptr->ext_zfinx) { 457 return cpu_fpr[reg_num]; 458 } 459 460 if (reg_num == 0) { 461 return ftemp_new(ctx); 462 } 463 464 switch (get_xl(ctx)) { 465 case MXL_RV32: 466 return ftemp_new(ctx); 467 #ifdef TARGET_RISCV64 468 case MXL_RV64: 469 return cpu_gpr[reg_num]; 470 #endif 471 default: 472 g_assert_not_reached(); 473 } 474 } 475 476 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 477 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 478 { 479 if (!ctx->cfg_ptr->ext_zfinx) { 480 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 481 return; 482 } 483 if (reg_num != 0) { 484 switch (get_xl(ctx)) { 485 case MXL_RV32: 486 #ifdef TARGET_RISCV32 487 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 488 break; 489 #else 490 /* fall through */ 491 case MXL_RV64: 492 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 493 break; 494 #endif 495 default: 496 g_assert_not_reached(); 497 } 498 } 499 } 500 501 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 502 { 503 if (!ctx->cfg_ptr->ext_zfinx) { 504 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 505 return; 506 } 507 508 if (reg_num != 0) { 509 switch (get_xl(ctx)) { 510 case MXL_RV32: 511 #ifdef TARGET_RISCV32 512 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 513 break; 514 #else 515 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 516 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 517 break; 518 case MXL_RV64: 519 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 520 break; 521 #endif 522 default: 523 g_assert_not_reached(); 524 } 525 } 526 } 527 528 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 529 { 530 target_ulong next_pc; 531 532 /* check misaligned: */ 533 next_pc = ctx->base.pc_next + imm; 534 if (!has_ext(ctx, RVC)) { 535 if ((next_pc & 0x3) != 0) { 536 gen_exception_inst_addr_mis(ctx); 537 return; 538 } 539 } 540 541 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 542 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 543 ctx->base.is_jmp = DISAS_NORETURN; 544 } 545 546 /* Compute a canonical address from a register plus offset. */ 547 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 548 { 549 TCGv addr = temp_new(ctx); 550 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 551 552 tcg_gen_addi_tl(addr, src1, imm); 553 if (ctx->pm_mask_enabled) { 554 tcg_gen_andc_tl(addr, addr, pm_mask); 555 } else if (get_xl(ctx) == MXL_RV32) { 556 tcg_gen_ext32u_tl(addr, addr); 557 } 558 if (ctx->pm_base_enabled) { 559 tcg_gen_or_tl(addr, addr, pm_base); 560 } 561 return addr; 562 } 563 564 #ifndef CONFIG_USER_ONLY 565 /* The states of mstatus_fs are: 566 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 567 * We will have already diagnosed disabled state, 568 * and need to turn initial/clean into dirty. 569 */ 570 static void mark_fs_dirty(DisasContext *ctx) 571 { 572 TCGv tmp; 573 574 if (!has_ext(ctx, RVF)) { 575 return; 576 } 577 578 if (ctx->mstatus_fs != MSTATUS_FS) { 579 /* Remember the state change for the rest of the TB. */ 580 ctx->mstatus_fs = MSTATUS_FS; 581 582 tmp = tcg_temp_new(); 583 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 584 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 585 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 586 tcg_temp_free(tmp); 587 } 588 589 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 590 /* Remember the stage change for the rest of the TB. */ 591 ctx->mstatus_hs_fs = MSTATUS_FS; 592 593 tmp = tcg_temp_new(); 594 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 595 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 596 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 597 tcg_temp_free(tmp); 598 } 599 } 600 #else 601 static inline void mark_fs_dirty(DisasContext *ctx) { } 602 #endif 603 604 #ifndef CONFIG_USER_ONLY 605 /* The states of mstatus_vs are: 606 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 607 * We will have already diagnosed disabled state, 608 * and need to turn initial/clean into dirty. 609 */ 610 static void mark_vs_dirty(DisasContext *ctx) 611 { 612 TCGv tmp; 613 614 if (ctx->mstatus_vs != MSTATUS_VS) { 615 /* Remember the state change for the rest of the TB. */ 616 ctx->mstatus_vs = MSTATUS_VS; 617 618 tmp = tcg_temp_new(); 619 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 620 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 621 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 622 tcg_temp_free(tmp); 623 } 624 625 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 626 /* Remember the stage change for the rest of the TB. */ 627 ctx->mstatus_hs_vs = MSTATUS_VS; 628 629 tmp = tcg_temp_new(); 630 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 631 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 632 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 633 tcg_temp_free(tmp); 634 } 635 } 636 #else 637 static inline void mark_vs_dirty(DisasContext *ctx) { } 638 #endif 639 640 static void gen_set_rm(DisasContext *ctx, int rm) 641 { 642 if (ctx->frm == rm) { 643 return; 644 } 645 ctx->frm = rm; 646 647 if (rm == RISCV_FRM_ROD) { 648 gen_helper_set_rod_rounding_mode(cpu_env); 649 return; 650 } 651 652 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 653 decode_save_opc(ctx); 654 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 655 } 656 657 static int ex_plus_1(DisasContext *ctx, int nf) 658 { 659 return nf + 1; 660 } 661 662 #define EX_SH(amount) \ 663 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 664 { \ 665 return imm << amount; \ 666 } 667 EX_SH(1) 668 EX_SH(2) 669 EX_SH(3) 670 EX_SH(4) 671 EX_SH(12) 672 673 #define REQUIRE_EXT(ctx, ext) do { \ 674 if (!has_ext(ctx, ext)) { \ 675 return false; \ 676 } \ 677 } while (0) 678 679 #define REQUIRE_32BIT(ctx) do { \ 680 if (get_xl(ctx) != MXL_RV32) { \ 681 return false; \ 682 } \ 683 } while (0) 684 685 #define REQUIRE_64BIT(ctx) do { \ 686 if (get_xl(ctx) != MXL_RV64) { \ 687 return false; \ 688 } \ 689 } while (0) 690 691 #define REQUIRE_128BIT(ctx) do { \ 692 if (get_xl(ctx) != MXL_RV128) { \ 693 return false; \ 694 } \ 695 } while (0) 696 697 #define REQUIRE_64_OR_128BIT(ctx) do { \ 698 if (get_xl(ctx) == MXL_RV32) { \ 699 return false; \ 700 } \ 701 } while (0) 702 703 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 704 if (!ctx->cfg_ptr->ext_##A && \ 705 !ctx->cfg_ptr->ext_##B) { \ 706 return false; \ 707 } \ 708 } while (0) 709 710 static int ex_rvc_register(DisasContext *ctx, int reg) 711 { 712 return 8 + reg; 713 } 714 715 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 716 { 717 /* For RV128 a shamt of 0 means a shift by 64. */ 718 if (get_ol(ctx) == MXL_RV128) { 719 imm = imm ? imm : 64; 720 } 721 return imm; 722 } 723 724 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 725 { 726 /* 727 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 728 * shifts, the shamt is sign-extended. 729 */ 730 if (get_ol(ctx) == MXL_RV128) { 731 imm = imm | (imm & 32) << 1; 732 imm = imm ? imm : 64; 733 } 734 return imm; 735 } 736 737 /* Include the auto-generated decoder for 32 bit insn */ 738 #include "decode-insn32.c.inc" 739 740 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 741 void (*func)(TCGv, TCGv, target_long)) 742 { 743 TCGv dest = dest_gpr(ctx, a->rd); 744 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 745 746 func(dest, src1, a->imm); 747 748 if (get_xl(ctx) == MXL_RV128) { 749 TCGv src1h = get_gprh(ctx, a->rs1); 750 TCGv desth = dest_gprh(ctx, a->rd); 751 752 func(desth, src1h, -(a->imm < 0)); 753 gen_set_gpr128(ctx, a->rd, dest, desth); 754 } else { 755 gen_set_gpr(ctx, a->rd, dest); 756 } 757 758 return true; 759 } 760 761 static bool gen_logic(DisasContext *ctx, arg_r *a, 762 void (*func)(TCGv, TCGv, TCGv)) 763 { 764 TCGv dest = dest_gpr(ctx, a->rd); 765 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 766 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 767 768 func(dest, src1, src2); 769 770 if (get_xl(ctx) == MXL_RV128) { 771 TCGv src1h = get_gprh(ctx, a->rs1); 772 TCGv src2h = get_gprh(ctx, a->rs2); 773 TCGv desth = dest_gprh(ctx, a->rd); 774 775 func(desth, src1h, src2h); 776 gen_set_gpr128(ctx, a->rd, dest, desth); 777 } else { 778 gen_set_gpr(ctx, a->rd, dest); 779 } 780 781 return true; 782 } 783 784 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 785 void (*func)(TCGv, TCGv, target_long), 786 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 787 { 788 TCGv dest = dest_gpr(ctx, a->rd); 789 TCGv src1 = get_gpr(ctx, a->rs1, ext); 790 791 if (get_ol(ctx) < MXL_RV128) { 792 func(dest, src1, a->imm); 793 gen_set_gpr(ctx, a->rd, dest); 794 } else { 795 if (f128 == NULL) { 796 return false; 797 } 798 799 TCGv src1h = get_gprh(ctx, a->rs1); 800 TCGv desth = dest_gprh(ctx, a->rd); 801 802 f128(dest, desth, src1, src1h, a->imm); 803 gen_set_gpr128(ctx, a->rd, dest, desth); 804 } 805 return true; 806 } 807 808 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 809 void (*func)(TCGv, TCGv, TCGv), 810 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 811 { 812 TCGv dest = dest_gpr(ctx, a->rd); 813 TCGv src1 = get_gpr(ctx, a->rs1, ext); 814 TCGv src2 = tcg_constant_tl(a->imm); 815 816 if (get_ol(ctx) < MXL_RV128) { 817 func(dest, src1, src2); 818 gen_set_gpr(ctx, a->rd, dest); 819 } else { 820 if (f128 == NULL) { 821 return false; 822 } 823 824 TCGv src1h = get_gprh(ctx, a->rs1); 825 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 826 TCGv desth = dest_gprh(ctx, a->rd); 827 828 f128(dest, desth, src1, src1h, src2, src2h); 829 gen_set_gpr128(ctx, a->rd, dest, desth); 830 } 831 return true; 832 } 833 834 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 835 void (*func)(TCGv, TCGv, TCGv), 836 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 837 { 838 TCGv dest = dest_gpr(ctx, a->rd); 839 TCGv src1 = get_gpr(ctx, a->rs1, ext); 840 TCGv src2 = get_gpr(ctx, a->rs2, ext); 841 842 if (get_ol(ctx) < MXL_RV128) { 843 func(dest, src1, src2); 844 gen_set_gpr(ctx, a->rd, dest); 845 } else { 846 if (f128 == NULL) { 847 return false; 848 } 849 850 TCGv src1h = get_gprh(ctx, a->rs1); 851 TCGv src2h = get_gprh(ctx, a->rs2); 852 TCGv desth = dest_gprh(ctx, a->rd); 853 854 f128(dest, desth, src1, src1h, src2, src2h); 855 gen_set_gpr128(ctx, a->rd, dest, desth); 856 } 857 return true; 858 } 859 860 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 861 void (*f_tl)(TCGv, TCGv, TCGv), 862 void (*f_32)(TCGv, TCGv, TCGv), 863 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 864 { 865 int olen = get_olen(ctx); 866 867 if (olen != TARGET_LONG_BITS) { 868 if (olen == 32) { 869 f_tl = f_32; 870 } else if (olen != 128) { 871 g_assert_not_reached(); 872 } 873 } 874 return gen_arith(ctx, a, ext, f_tl, f_128); 875 } 876 877 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 878 void (*func)(TCGv, TCGv, target_long), 879 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 880 { 881 TCGv dest, src1; 882 int max_len = get_olen(ctx); 883 884 if (a->shamt >= max_len) { 885 return false; 886 } 887 888 dest = dest_gpr(ctx, a->rd); 889 src1 = get_gpr(ctx, a->rs1, ext); 890 891 if (max_len < 128) { 892 func(dest, src1, a->shamt); 893 gen_set_gpr(ctx, a->rd, dest); 894 } else { 895 TCGv src1h = get_gprh(ctx, a->rs1); 896 TCGv desth = dest_gprh(ctx, a->rd); 897 898 if (f128 == NULL) { 899 return false; 900 } 901 f128(dest, desth, src1, src1h, a->shamt); 902 gen_set_gpr128(ctx, a->rd, dest, desth); 903 } 904 return true; 905 } 906 907 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 908 DisasExtend ext, 909 void (*f_tl)(TCGv, TCGv, target_long), 910 void (*f_32)(TCGv, TCGv, target_long), 911 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 912 target_long)) 913 { 914 int olen = get_olen(ctx); 915 if (olen != TARGET_LONG_BITS) { 916 if (olen == 32) { 917 f_tl = f_32; 918 } else if (olen != 128) { 919 g_assert_not_reached(); 920 } 921 } 922 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 923 } 924 925 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 926 void (*func)(TCGv, TCGv, TCGv)) 927 { 928 TCGv dest, src1, src2; 929 int max_len = get_olen(ctx); 930 931 if (a->shamt >= max_len) { 932 return false; 933 } 934 935 dest = dest_gpr(ctx, a->rd); 936 src1 = get_gpr(ctx, a->rs1, ext); 937 src2 = tcg_constant_tl(a->shamt); 938 939 func(dest, src1, src2); 940 941 gen_set_gpr(ctx, a->rd, dest); 942 return true; 943 } 944 945 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 946 void (*func)(TCGv, TCGv, TCGv), 947 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 948 { 949 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 950 TCGv ext2 = tcg_temp_new(); 951 int max_len = get_olen(ctx); 952 953 tcg_gen_andi_tl(ext2, src2, max_len - 1); 954 955 TCGv dest = dest_gpr(ctx, a->rd); 956 TCGv src1 = get_gpr(ctx, a->rs1, ext); 957 958 if (max_len < 128) { 959 func(dest, src1, ext2); 960 gen_set_gpr(ctx, a->rd, dest); 961 } else { 962 TCGv src1h = get_gprh(ctx, a->rs1); 963 TCGv desth = dest_gprh(ctx, a->rd); 964 965 if (f128 == NULL) { 966 return false; 967 } 968 f128(dest, desth, src1, src1h, ext2); 969 gen_set_gpr128(ctx, a->rd, dest, desth); 970 } 971 tcg_temp_free(ext2); 972 return true; 973 } 974 975 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 976 void (*f_tl)(TCGv, TCGv, TCGv), 977 void (*f_32)(TCGv, TCGv, TCGv), 978 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 979 { 980 int olen = get_olen(ctx); 981 if (olen != TARGET_LONG_BITS) { 982 if (olen == 32) { 983 f_tl = f_32; 984 } else if (olen != 128) { 985 g_assert_not_reached(); 986 } 987 } 988 return gen_shift(ctx, a, ext, f_tl, f_128); 989 } 990 991 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 992 void (*func)(TCGv, TCGv)) 993 { 994 TCGv dest = dest_gpr(ctx, a->rd); 995 TCGv src1 = get_gpr(ctx, a->rs1, ext); 996 997 func(dest, src1); 998 999 gen_set_gpr(ctx, a->rd, dest); 1000 return true; 1001 } 1002 1003 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1004 void (*f_tl)(TCGv, TCGv), 1005 void (*f_32)(TCGv, TCGv)) 1006 { 1007 int olen = get_olen(ctx); 1008 1009 if (olen != TARGET_LONG_BITS) { 1010 if (olen == 32) { 1011 f_tl = f_32; 1012 } else { 1013 g_assert_not_reached(); 1014 } 1015 } 1016 return gen_unary(ctx, a, ext, f_tl); 1017 } 1018 1019 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1020 { 1021 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1022 CPUState *cpu = ctx->cs; 1023 CPURISCVState *env = cpu->env_ptr; 1024 1025 return cpu_ldl_code(env, pc); 1026 } 1027 1028 /* Include insn module translation function */ 1029 #include "insn_trans/trans_rvi.c.inc" 1030 #include "insn_trans/trans_rvm.c.inc" 1031 #include "insn_trans/trans_rva.c.inc" 1032 #include "insn_trans/trans_rvf.c.inc" 1033 #include "insn_trans/trans_rvd.c.inc" 1034 #include "insn_trans/trans_rvh.c.inc" 1035 #include "insn_trans/trans_rvv.c.inc" 1036 #include "insn_trans/trans_rvb.c.inc" 1037 #include "insn_trans/trans_rvzfh.c.inc" 1038 #include "insn_trans/trans_rvk.c.inc" 1039 #include "insn_trans/trans_privileged.c.inc" 1040 #include "insn_trans/trans_svinval.c.inc" 1041 #include "insn_trans/trans_xventanacondops.c.inc" 1042 1043 /* Include the auto-generated decoder for 16 bit insn */ 1044 #include "decode-insn16.c.inc" 1045 /* Include decoders for factored-out extensions */ 1046 #include "decode-XVentanaCondOps.c.inc" 1047 1048 /* The specification allows for longer insns, but not supported by qemu. */ 1049 #define MAX_INSN_LEN 4 1050 1051 static inline int insn_len(uint16_t first_word) 1052 { 1053 return (first_word & 3) == 3 ? 4 : 2; 1054 } 1055 1056 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1057 { 1058 /* 1059 * A table with predicate (i.e., guard) functions and decoder functions 1060 * that are tested in-order until a decoder matches onto the opcode. 1061 */ 1062 static const struct { 1063 bool (*guard_func)(DisasContext *); 1064 bool (*decode_func)(DisasContext *, uint32_t); 1065 } decoders[] = { 1066 { always_true_p, decode_insn32 }, 1067 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1068 }; 1069 1070 ctx->virt_inst_excp = false; 1071 /* Check for compressed insn */ 1072 if (insn_len(opcode) == 2) { 1073 if (!has_ext(ctx, RVC)) { 1074 gen_exception_illegal(ctx); 1075 } else { 1076 ctx->opcode = opcode; 1077 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1078 if (decode_insn16(ctx, opcode)) { 1079 return; 1080 } 1081 } 1082 } else { 1083 uint32_t opcode32 = opcode; 1084 opcode32 = deposit32(opcode32, 16, 16, 1085 translator_lduw(env, &ctx->base, 1086 ctx->base.pc_next + 2)); 1087 ctx->opcode = opcode32; 1088 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1089 1090 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1091 if (decoders[i].guard_func(ctx) && 1092 decoders[i].decode_func(ctx, opcode32)) { 1093 return; 1094 } 1095 } 1096 } 1097 1098 gen_exception_illegal(ctx); 1099 } 1100 1101 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1102 { 1103 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1104 CPURISCVState *env = cs->env_ptr; 1105 RISCVCPU *cpu = RISCV_CPU(cs); 1106 uint32_t tb_flags = ctx->base.tb->flags; 1107 1108 ctx->pc_succ_insn = ctx->base.pc_first; 1109 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1110 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1111 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1112 ctx->priv_ver = env->priv_ver; 1113 #if !defined(CONFIG_USER_ONLY) 1114 if (riscv_has_ext(env, RVH)) { 1115 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1116 } else { 1117 ctx->virt_enabled = false; 1118 } 1119 #else 1120 ctx->virt_enabled = false; 1121 #endif 1122 ctx->misa_ext = env->misa_ext; 1123 ctx->frm = -1; /* unknown rounding mode */ 1124 ctx->cfg_ptr = &(cpu->cfg); 1125 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1126 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1127 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1128 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1129 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1130 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1131 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1132 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1133 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1134 ctx->vstart = env->vstart; 1135 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1136 ctx->misa_mxl_max = env->misa_mxl_max; 1137 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1138 ctx->cs = cs; 1139 ctx->ntemp = 0; 1140 memset(ctx->temp, 0, sizeof(ctx->temp)); 1141 ctx->nftemp = 0; 1142 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1143 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1144 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1145 ctx->zero = tcg_constant_tl(0); 1146 } 1147 1148 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1149 { 1150 } 1151 1152 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1153 { 1154 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1155 1156 tcg_gen_insn_start(ctx->base.pc_next, 0); 1157 ctx->insn_start = tcg_last_op(); 1158 } 1159 1160 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1161 { 1162 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1163 CPURISCVState *env = cpu->env_ptr; 1164 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1165 int i; 1166 1167 ctx->ol = ctx->xl; 1168 decode_opc(env, ctx, opcode16); 1169 ctx->base.pc_next = ctx->pc_succ_insn; 1170 1171 for (i = ctx->ntemp - 1; i >= 0; --i) { 1172 tcg_temp_free(ctx->temp[i]); 1173 ctx->temp[i] = NULL; 1174 } 1175 ctx->ntemp = 0; 1176 for (i = ctx->nftemp - 1; i >= 0; --i) { 1177 tcg_temp_free_i64(ctx->ftemp[i]); 1178 ctx->ftemp[i] = NULL; 1179 } 1180 ctx->nftemp = 0; 1181 1182 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1183 if (ctx->base.is_jmp == DISAS_NEXT) { 1184 if (!is_same_page(&ctx->base, ctx->base.pc_next)) { 1185 ctx->base.is_jmp = DISAS_TOO_MANY; 1186 } else { 1187 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1188 1189 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1190 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1191 int len = insn_len(next_insn); 1192 1193 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1194 ctx->base.is_jmp = DISAS_TOO_MANY; 1195 } 1196 } 1197 } 1198 } 1199 } 1200 1201 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1202 { 1203 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1204 1205 switch (ctx->base.is_jmp) { 1206 case DISAS_TOO_MANY: 1207 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1208 break; 1209 case DISAS_NORETURN: 1210 break; 1211 default: 1212 g_assert_not_reached(); 1213 } 1214 } 1215 1216 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1217 CPUState *cpu, FILE *logfile) 1218 { 1219 #ifndef CONFIG_USER_ONLY 1220 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1221 CPURISCVState *env = &rvcpu->env; 1222 #endif 1223 1224 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1225 #ifndef CONFIG_USER_ONLY 1226 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1227 env->priv, env->virt); 1228 #endif 1229 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1230 } 1231 1232 static const TranslatorOps riscv_tr_ops = { 1233 .init_disas_context = riscv_tr_init_disas_context, 1234 .tb_start = riscv_tr_tb_start, 1235 .insn_start = riscv_tr_insn_start, 1236 .translate_insn = riscv_tr_translate_insn, 1237 .tb_stop = riscv_tr_tb_stop, 1238 .disas_log = riscv_tr_disas_log, 1239 }; 1240 1241 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1242 target_ulong pc, void *host_pc) 1243 { 1244 DisasContext ctx; 1245 1246 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1247 } 1248 1249 void riscv_translate_init(void) 1250 { 1251 int i; 1252 1253 /* 1254 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1255 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1256 * unless you specifically block reads/writes to reg 0. 1257 */ 1258 cpu_gpr[0] = NULL; 1259 cpu_gprh[0] = NULL; 1260 1261 for (i = 1; i < 32; i++) { 1262 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1263 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1264 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1265 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1266 } 1267 1268 for (i = 0; i < 32; i++) { 1269 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1270 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1271 } 1272 1273 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1274 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1275 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1276 "vstart"); 1277 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1278 "load_res"); 1279 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1280 "load_val"); 1281 /* Assign PM CSRs to tcg globals */ 1282 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1283 "pmmask"); 1284 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1285 "pmbase"); 1286 } 1287