1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL xl; 63 uint32_t misa_ext; 64 uint32_t opcode; 65 uint32_t mstatus_fs; 66 uint32_t mstatus_vs; 67 uint32_t mstatus_hs_fs; 68 uint32_t mstatus_hs_vs; 69 uint32_t mem_idx; 70 /* Remember the rounding mode encoded in the previous fp instruction, 71 which we have already installed into env->fp_status. Or -1 for 72 no previous fp instruction. Note that we exit the TB when writing 73 to any system register, which includes CSR_FRM, so we do not have 74 to reset this known value. */ 75 int frm; 76 RISCVMXL ol; 77 bool virt_enabled; 78 bool ext_ifencei; 79 bool ext_zfh; 80 bool ext_zfhmin; 81 bool hlsx; 82 /* vector extension */ 83 bool vill; 84 /* 85 * Encode LMUL to lmul as follows: 86 * LMUL vlmul lmul 87 * 1 000 0 88 * 2 001 1 89 * 4 010 2 90 * 8 011 3 91 * - 100 - 92 * 1/8 101 -3 93 * 1/4 110 -2 94 * 1/2 111 -1 95 */ 96 int8_t lmul; 97 uint8_t sew; 98 uint16_t vlen; 99 target_ulong vstart; 100 bool vl_eq_vlmax; 101 uint8_t ntemp; 102 CPUState *cs; 103 TCGv zero; 104 /* Space for 3 operands plus 1 extra for address computation. */ 105 TCGv temp[4]; 106 /* PointerMasking extension */ 107 bool pm_enabled; 108 TCGv pm_mask; 109 TCGv pm_base; 110 } DisasContext; 111 112 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 113 { 114 return ctx->misa_ext & ext; 115 } 116 117 #ifdef TARGET_RISCV32 118 #define get_xl(ctx) MXL_RV32 119 #elif defined(CONFIG_USER_ONLY) 120 #define get_xl(ctx) MXL_RV64 121 #else 122 #define get_xl(ctx) ((ctx)->xl) 123 #endif 124 125 /* The word size for this machine mode. */ 126 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 127 { 128 return 16 << get_xl(ctx); 129 } 130 131 /* The operation length, as opposed to the xlen. */ 132 #ifdef TARGET_RISCV32 133 #define get_ol(ctx) MXL_RV32 134 #else 135 #define get_ol(ctx) ((ctx)->ol) 136 #endif 137 138 static inline int get_olen(DisasContext *ctx) 139 { 140 return 16 << get_ol(ctx); 141 } 142 143 /* 144 * RISC-V requires NaN-boxing of narrower width floating point values. 145 * This applies when a 32-bit value is assigned to a 64-bit FP register. 146 * For consistency and simplicity, we nanbox results even when the RVD 147 * extension is not present. 148 */ 149 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 150 { 151 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 152 } 153 154 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 155 { 156 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 157 } 158 159 /* 160 * A narrow n-bit operation, where n < FLEN, checks that input operands 161 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 162 * If so, the least-significant bits of the input are used, otherwise the 163 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 164 * 165 * Here, the result is always nan-boxed, even the canonical nan. 166 */ 167 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 168 { 169 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 170 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 171 172 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 173 tcg_temp_free_i64(t_max); 174 tcg_temp_free_i64(t_nan); 175 } 176 177 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 178 { 179 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 180 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 181 182 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 183 } 184 185 static void generate_exception(DisasContext *ctx, int excp) 186 { 187 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 188 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 189 ctx->base.is_jmp = DISAS_NORETURN; 190 } 191 192 static void generate_exception_mtval(DisasContext *ctx, int excp) 193 { 194 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 195 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 196 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 197 ctx->base.is_jmp = DISAS_NORETURN; 198 } 199 200 static void gen_exception_illegal(DisasContext *ctx) 201 { 202 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 203 } 204 205 static void gen_exception_inst_addr_mis(DisasContext *ctx) 206 { 207 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 208 } 209 210 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 211 { 212 if (translator_use_goto_tb(&ctx->base, dest)) { 213 tcg_gen_goto_tb(n); 214 tcg_gen_movi_tl(cpu_pc, dest); 215 tcg_gen_exit_tb(ctx->base.tb, n); 216 } else { 217 tcg_gen_movi_tl(cpu_pc, dest); 218 tcg_gen_lookup_and_goto_ptr(); 219 } 220 } 221 222 /* 223 * Wrappers for getting reg values. 224 * 225 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 226 * constant zero as a source, and an uninitialized sink as destination. 227 * 228 * Further, we may provide an extension for word operations. 229 */ 230 static TCGv temp_new(DisasContext *ctx) 231 { 232 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 233 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 234 } 235 236 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 237 { 238 TCGv t; 239 240 if (reg_num == 0) { 241 return ctx->zero; 242 } 243 244 switch (get_ol(ctx)) { 245 case MXL_RV32: 246 switch (ext) { 247 case EXT_NONE: 248 break; 249 case EXT_SIGN: 250 t = temp_new(ctx); 251 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 252 return t; 253 case EXT_ZERO: 254 t = temp_new(ctx); 255 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 256 return t; 257 default: 258 g_assert_not_reached(); 259 } 260 break; 261 case MXL_RV64: 262 break; 263 default: 264 g_assert_not_reached(); 265 } 266 return cpu_gpr[reg_num]; 267 } 268 269 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 270 { 271 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 272 return temp_new(ctx); 273 } 274 return cpu_gpr[reg_num]; 275 } 276 277 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 278 { 279 if (reg_num != 0) { 280 switch (get_ol(ctx)) { 281 case MXL_RV32: 282 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 283 break; 284 case MXL_RV64: 285 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 286 break; 287 default: 288 g_assert_not_reached(); 289 } 290 } 291 } 292 293 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 294 { 295 target_ulong next_pc; 296 297 /* check misaligned: */ 298 next_pc = ctx->base.pc_next + imm; 299 if (!has_ext(ctx, RVC)) { 300 if ((next_pc & 0x3) != 0) { 301 gen_exception_inst_addr_mis(ctx); 302 return; 303 } 304 } 305 if (rd != 0) { 306 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 307 } 308 309 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 310 ctx->base.is_jmp = DISAS_NORETURN; 311 } 312 313 /* 314 * Generates address adjustment for PointerMasking 315 */ 316 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 317 { 318 TCGv temp; 319 if (!s->pm_enabled) { 320 /* Load unmodified address */ 321 return src; 322 } else { 323 temp = temp_new(s); 324 tcg_gen_andc_tl(temp, src, s->pm_mask); 325 tcg_gen_or_tl(temp, temp, s->pm_base); 326 return temp; 327 } 328 } 329 330 #ifndef CONFIG_USER_ONLY 331 /* The states of mstatus_fs are: 332 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 333 * We will have already diagnosed disabled state, 334 * and need to turn initial/clean into dirty. 335 */ 336 static void mark_fs_dirty(DisasContext *ctx) 337 { 338 TCGv tmp; 339 340 if (ctx->mstatus_fs != MSTATUS_FS) { 341 /* Remember the state change for the rest of the TB. */ 342 ctx->mstatus_fs = MSTATUS_FS; 343 344 tmp = tcg_temp_new(); 345 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 346 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 347 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 348 tcg_temp_free(tmp); 349 } 350 351 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 352 /* Remember the stage change for the rest of the TB. */ 353 ctx->mstatus_hs_fs = MSTATUS_FS; 354 355 tmp = tcg_temp_new(); 356 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 357 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 358 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 359 tcg_temp_free(tmp); 360 } 361 } 362 #else 363 static inline void mark_fs_dirty(DisasContext *ctx) { } 364 #endif 365 366 #ifndef CONFIG_USER_ONLY 367 /* The states of mstatus_vs are: 368 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 369 * We will have already diagnosed disabled state, 370 * and need to turn initial/clean into dirty. 371 */ 372 static void mark_vs_dirty(DisasContext *ctx) 373 { 374 TCGv tmp; 375 376 if (ctx->mstatus_vs != MSTATUS_VS) { 377 /* Remember the state change for the rest of the TB. */ 378 ctx->mstatus_vs = MSTATUS_VS; 379 380 tmp = tcg_temp_new(); 381 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 382 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 383 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 384 tcg_temp_free(tmp); 385 } 386 387 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 388 /* Remember the stage change for the rest of the TB. */ 389 ctx->mstatus_hs_vs = MSTATUS_VS; 390 391 tmp = tcg_temp_new(); 392 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 393 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 394 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 395 tcg_temp_free(tmp); 396 } 397 } 398 #else 399 static inline void mark_vs_dirty(DisasContext *ctx) { } 400 #endif 401 402 static void gen_set_rm(DisasContext *ctx, int rm) 403 { 404 if (ctx->frm == rm) { 405 return; 406 } 407 ctx->frm = rm; 408 409 if (rm == RISCV_FRM_ROD) { 410 gen_helper_set_rod_rounding_mode(cpu_env); 411 return; 412 } 413 414 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 415 } 416 417 static int ex_plus_1(DisasContext *ctx, int nf) 418 { 419 return nf + 1; 420 } 421 422 #define EX_SH(amount) \ 423 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 424 { \ 425 return imm << amount; \ 426 } 427 EX_SH(1) 428 EX_SH(2) 429 EX_SH(3) 430 EX_SH(4) 431 EX_SH(12) 432 433 #define REQUIRE_EXT(ctx, ext) do { \ 434 if (!has_ext(ctx, ext)) { \ 435 return false; \ 436 } \ 437 } while (0) 438 439 #define REQUIRE_32BIT(ctx) do { \ 440 if (get_xl(ctx) != MXL_RV32) { \ 441 return false; \ 442 } \ 443 } while (0) 444 445 #define REQUIRE_64BIT(ctx) do { \ 446 if (get_xl(ctx) < MXL_RV64) { \ 447 return false; \ 448 } \ 449 } while (0) 450 451 static int ex_rvc_register(DisasContext *ctx, int reg) 452 { 453 return 8 + reg; 454 } 455 456 static int ex_rvc_shifti(DisasContext *ctx, int imm) 457 { 458 /* For RV128 a shamt of 0 means a shift by 64. */ 459 return imm ? imm : 64; 460 } 461 462 /* Include the auto-generated decoder for 32 bit insn */ 463 #include "decode-insn32.c.inc" 464 465 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 466 void (*func)(TCGv, TCGv, target_long)) 467 { 468 TCGv dest = dest_gpr(ctx, a->rd); 469 TCGv src1 = get_gpr(ctx, a->rs1, ext); 470 471 func(dest, src1, a->imm); 472 473 gen_set_gpr(ctx, a->rd, dest); 474 return true; 475 } 476 477 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 478 void (*func)(TCGv, TCGv, TCGv)) 479 { 480 TCGv dest = dest_gpr(ctx, a->rd); 481 TCGv src1 = get_gpr(ctx, a->rs1, ext); 482 TCGv src2 = tcg_constant_tl(a->imm); 483 484 func(dest, src1, src2); 485 486 gen_set_gpr(ctx, a->rd, dest); 487 return true; 488 } 489 490 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 491 void (*func)(TCGv, TCGv, TCGv)) 492 { 493 TCGv dest = dest_gpr(ctx, a->rd); 494 TCGv src1 = get_gpr(ctx, a->rs1, ext); 495 TCGv src2 = get_gpr(ctx, a->rs2, ext); 496 497 func(dest, src1, src2); 498 499 gen_set_gpr(ctx, a->rd, dest); 500 return true; 501 } 502 503 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 504 void (*f_tl)(TCGv, TCGv, TCGv), 505 void (*f_32)(TCGv, TCGv, TCGv)) 506 { 507 int olen = get_olen(ctx); 508 509 if (olen != TARGET_LONG_BITS) { 510 if (olen == 32) { 511 f_tl = f_32; 512 } else { 513 g_assert_not_reached(); 514 } 515 } 516 return gen_arith(ctx, a, ext, f_tl); 517 } 518 519 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 520 void (*func)(TCGv, TCGv, target_long)) 521 { 522 TCGv dest, src1; 523 int max_len = get_olen(ctx); 524 525 if (a->shamt >= max_len) { 526 return false; 527 } 528 529 dest = dest_gpr(ctx, a->rd); 530 src1 = get_gpr(ctx, a->rs1, ext); 531 532 func(dest, src1, a->shamt); 533 534 gen_set_gpr(ctx, a->rd, dest); 535 return true; 536 } 537 538 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 539 DisasExtend ext, 540 void (*f_tl)(TCGv, TCGv, target_long), 541 void (*f_32)(TCGv, TCGv, target_long)) 542 { 543 int olen = get_olen(ctx); 544 if (olen != TARGET_LONG_BITS) { 545 if (olen == 32) { 546 f_tl = f_32; 547 } else { 548 g_assert_not_reached(); 549 } 550 } 551 return gen_shift_imm_fn(ctx, a, ext, f_tl); 552 } 553 554 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 555 void (*func)(TCGv, TCGv, TCGv)) 556 { 557 TCGv dest, src1, src2; 558 int max_len = get_olen(ctx); 559 560 if (a->shamt >= max_len) { 561 return false; 562 } 563 564 dest = dest_gpr(ctx, a->rd); 565 src1 = get_gpr(ctx, a->rs1, ext); 566 src2 = tcg_constant_tl(a->shamt); 567 568 func(dest, src1, src2); 569 570 gen_set_gpr(ctx, a->rd, dest); 571 return true; 572 } 573 574 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 575 void (*func)(TCGv, TCGv, TCGv)) 576 { 577 TCGv dest = dest_gpr(ctx, a->rd); 578 TCGv src1 = get_gpr(ctx, a->rs1, ext); 579 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 580 TCGv ext2 = tcg_temp_new(); 581 582 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 583 func(dest, src1, ext2); 584 585 gen_set_gpr(ctx, a->rd, dest); 586 tcg_temp_free(ext2); 587 return true; 588 } 589 590 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 591 void (*f_tl)(TCGv, TCGv, TCGv), 592 void (*f_32)(TCGv, TCGv, TCGv)) 593 { 594 int olen = get_olen(ctx); 595 if (olen != TARGET_LONG_BITS) { 596 if (olen == 32) { 597 f_tl = f_32; 598 } else { 599 g_assert_not_reached(); 600 } 601 } 602 return gen_shift(ctx, a, ext, f_tl); 603 } 604 605 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 606 void (*func)(TCGv, TCGv)) 607 { 608 TCGv dest = dest_gpr(ctx, a->rd); 609 TCGv src1 = get_gpr(ctx, a->rs1, ext); 610 611 func(dest, src1); 612 613 gen_set_gpr(ctx, a->rd, dest); 614 return true; 615 } 616 617 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 618 void (*f_tl)(TCGv, TCGv), 619 void (*f_32)(TCGv, TCGv)) 620 { 621 int olen = get_olen(ctx); 622 623 if (olen != TARGET_LONG_BITS) { 624 if (olen == 32) { 625 f_tl = f_32; 626 } else { 627 g_assert_not_reached(); 628 } 629 } 630 return gen_unary(ctx, a, ext, f_tl); 631 } 632 633 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 634 { 635 DisasContext *ctx = container_of(dcbase, DisasContext, base); 636 CPUState *cpu = ctx->cs; 637 CPURISCVState *env = cpu->env_ptr; 638 639 return cpu_ldl_code(env, pc); 640 } 641 642 /* Include insn module translation function */ 643 #include "insn_trans/trans_rvi.c.inc" 644 #include "insn_trans/trans_rvm.c.inc" 645 #include "insn_trans/trans_rva.c.inc" 646 #include "insn_trans/trans_rvf.c.inc" 647 #include "insn_trans/trans_rvd.c.inc" 648 #include "insn_trans/trans_rvh.c.inc" 649 #include "insn_trans/trans_rvv.c.inc" 650 #include "insn_trans/trans_rvb.c.inc" 651 #include "insn_trans/trans_rvzfh.c.inc" 652 #include "insn_trans/trans_privileged.c.inc" 653 654 /* Include the auto-generated decoder for 16 bit insn */ 655 #include "decode-insn16.c.inc" 656 657 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 658 { 659 /* check for compressed insn */ 660 if (extract16(opcode, 0, 2) != 3) { 661 if (!has_ext(ctx, RVC)) { 662 gen_exception_illegal(ctx); 663 } else { 664 ctx->pc_succ_insn = ctx->base.pc_next + 2; 665 if (!decode_insn16(ctx, opcode)) { 666 gen_exception_illegal(ctx); 667 } 668 } 669 } else { 670 uint32_t opcode32 = opcode; 671 opcode32 = deposit32(opcode32, 16, 16, 672 translator_lduw(env, &ctx->base, 673 ctx->base.pc_next + 2)); 674 ctx->pc_succ_insn = ctx->base.pc_next + 4; 675 if (!decode_insn32(ctx, opcode32)) { 676 gen_exception_illegal(ctx); 677 } 678 } 679 } 680 681 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 682 { 683 DisasContext *ctx = container_of(dcbase, DisasContext, base); 684 CPURISCVState *env = cs->env_ptr; 685 RISCVCPU *cpu = RISCV_CPU(cs); 686 uint32_t tb_flags = ctx->base.tb->flags; 687 688 ctx->pc_succ_insn = ctx->base.pc_first; 689 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 690 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 691 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 692 ctx->priv_ver = env->priv_ver; 693 #if !defined(CONFIG_USER_ONLY) 694 if (riscv_has_ext(env, RVH)) { 695 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 696 } else { 697 ctx->virt_enabled = false; 698 } 699 #else 700 ctx->virt_enabled = false; 701 #endif 702 ctx->misa_ext = env->misa_ext; 703 ctx->frm = -1; /* unknown rounding mode */ 704 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 705 ctx->ext_zfh = cpu->cfg.ext_zfh; 706 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 707 ctx->vlen = cpu->cfg.vlen; 708 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 709 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 710 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 711 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 712 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 713 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 714 ctx->vstart = env->vstart; 715 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 716 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 717 ctx->cs = cs; 718 ctx->ntemp = 0; 719 memset(ctx->temp, 0, sizeof(ctx->temp)); 720 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 721 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 722 ctx->pm_mask = pm_mask[priv]; 723 ctx->pm_base = pm_base[priv]; 724 725 ctx->zero = tcg_constant_tl(0); 726 } 727 728 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 729 { 730 } 731 732 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 733 { 734 DisasContext *ctx = container_of(dcbase, DisasContext, base); 735 736 tcg_gen_insn_start(ctx->base.pc_next); 737 } 738 739 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 740 { 741 DisasContext *ctx = container_of(dcbase, DisasContext, base); 742 CPURISCVState *env = cpu->env_ptr; 743 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 744 745 ctx->ol = ctx->xl; 746 decode_opc(env, ctx, opcode16); 747 ctx->base.pc_next = ctx->pc_succ_insn; 748 749 for (int i = ctx->ntemp - 1; i >= 0; --i) { 750 tcg_temp_free(ctx->temp[i]); 751 ctx->temp[i] = NULL; 752 } 753 ctx->ntemp = 0; 754 755 if (ctx->base.is_jmp == DISAS_NEXT) { 756 target_ulong page_start; 757 758 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 759 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 760 ctx->base.is_jmp = DISAS_TOO_MANY; 761 } 762 } 763 } 764 765 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 766 { 767 DisasContext *ctx = container_of(dcbase, DisasContext, base); 768 769 switch (ctx->base.is_jmp) { 770 case DISAS_TOO_MANY: 771 gen_goto_tb(ctx, 0, ctx->base.pc_next); 772 break; 773 case DISAS_NORETURN: 774 break; 775 default: 776 g_assert_not_reached(); 777 } 778 } 779 780 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 781 { 782 #ifndef CONFIG_USER_ONLY 783 RISCVCPU *rvcpu = RISCV_CPU(cpu); 784 CPURISCVState *env = &rvcpu->env; 785 #endif 786 787 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 788 #ifndef CONFIG_USER_ONLY 789 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 790 #endif 791 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 792 } 793 794 static const TranslatorOps riscv_tr_ops = { 795 .init_disas_context = riscv_tr_init_disas_context, 796 .tb_start = riscv_tr_tb_start, 797 .insn_start = riscv_tr_insn_start, 798 .translate_insn = riscv_tr_translate_insn, 799 .tb_stop = riscv_tr_tb_stop, 800 .disas_log = riscv_tr_disas_log, 801 }; 802 803 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 804 { 805 DisasContext ctx; 806 807 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 808 } 809 810 void riscv_translate_init(void) 811 { 812 int i; 813 814 /* 815 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 816 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 817 * unless you specifically block reads/writes to reg 0. 818 */ 819 cpu_gpr[0] = NULL; 820 821 for (i = 1; i < 32; i++) { 822 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 823 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 824 } 825 826 for (i = 0; i < 32; i++) { 827 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 828 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 829 } 830 831 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 832 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 833 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 834 "vstart"); 835 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 836 "load_res"); 837 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 838 "load_val"); 839 #ifndef CONFIG_USER_ONLY 840 /* Assign PM CSRs to tcg globals */ 841 pm_mask[PRV_U] = 842 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 843 pm_base[PRV_U] = 844 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 845 pm_mask[PRV_S] = 846 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 847 pm_base[PRV_S] = 848 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 849 pm_mask[PRV_M] = 850 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 851 pm_base[PRV_M] = 852 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 853 #endif 854 } 855