1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 uint8_t vta; 98 target_ulong vstart; 99 bool vl_eq_vlmax; 100 uint8_t ntemp; 101 CPUState *cs; 102 TCGv zero; 103 /* Space for 3 operands plus 1 extra for address computation. */ 104 TCGv temp[4]; 105 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 106 TCGv_i64 ftemp[4]; 107 uint8_t nftemp; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* TCG of the current insn_start */ 112 TCGOp *insn_start; 113 } DisasContext; 114 115 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 116 { 117 return ctx->misa_ext & ext; 118 } 119 120 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 121 { 122 return true; 123 } 124 125 #define MATERIALISE_EXT_PREDICATE(ext) \ 126 static bool has_ ## ext ## _p(DisasContext *ctx) \ 127 { \ 128 return ctx->cfg_ptr->ext_ ## ext ; \ 129 } 130 131 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 132 133 #ifdef TARGET_RISCV32 134 #define get_xl(ctx) MXL_RV32 135 #elif defined(CONFIG_USER_ONLY) 136 #define get_xl(ctx) MXL_RV64 137 #else 138 #define get_xl(ctx) ((ctx)->xl) 139 #endif 140 141 /* The word size for this machine mode. */ 142 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 143 { 144 return 16 << get_xl(ctx); 145 } 146 147 /* The operation length, as opposed to the xlen. */ 148 #ifdef TARGET_RISCV32 149 #define get_ol(ctx) MXL_RV32 150 #else 151 #define get_ol(ctx) ((ctx)->ol) 152 #endif 153 154 static inline int get_olen(DisasContext *ctx) 155 { 156 return 16 << get_ol(ctx); 157 } 158 159 /* The maximum register length */ 160 #ifdef TARGET_RISCV32 161 #define get_xl_max(ctx) MXL_RV32 162 #else 163 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 164 #endif 165 166 /* 167 * RISC-V requires NaN-boxing of narrower width floating point values. 168 * This applies when a 32-bit value is assigned to a 64-bit FP register. 169 * For consistency and simplicity, we nanbox results even when the RVD 170 * extension is not present. 171 */ 172 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 173 { 174 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 175 } 176 177 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 178 { 179 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 180 } 181 182 /* 183 * A narrow n-bit operation, where n < FLEN, checks that input operands 184 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 185 * If so, the least-significant bits of the input are used, otherwise the 186 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 187 * 188 * Here, the result is always nan-boxed, even the canonical nan. 189 */ 190 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 191 { 192 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 193 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 194 195 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 196 tcg_temp_free_i64(t_max); 197 tcg_temp_free_i64(t_nan); 198 } 199 200 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 201 { 202 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 203 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 204 205 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 206 } 207 208 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 209 { 210 if (get_xl(ctx) == MXL_RV32) { 211 dest = (int32_t)dest; 212 } 213 tcg_gen_movi_tl(cpu_pc, dest); 214 } 215 216 static void gen_set_pc(DisasContext *ctx, TCGv dest) 217 { 218 if (get_xl(ctx) == MXL_RV32) { 219 tcg_gen_ext32s_tl(cpu_pc, dest); 220 } else { 221 tcg_gen_mov_tl(cpu_pc, dest); 222 } 223 } 224 225 static void generate_exception(DisasContext *ctx, int excp) 226 { 227 gen_set_pc_imm(ctx, ctx->base.pc_next); 228 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 229 ctx->base.is_jmp = DISAS_NORETURN; 230 } 231 232 static void generate_exception_mtval(DisasContext *ctx, int excp) 233 { 234 gen_set_pc_imm(ctx, ctx->base.pc_next); 235 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 236 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 237 ctx->base.is_jmp = DISAS_NORETURN; 238 } 239 240 static void gen_exception_illegal(DisasContext *ctx) 241 { 242 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 243 } 244 245 static void gen_exception_inst_addr_mis(DisasContext *ctx) 246 { 247 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 248 } 249 250 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 251 { 252 if (translator_use_goto_tb(&ctx->base, dest)) { 253 tcg_gen_goto_tb(n); 254 gen_set_pc_imm(ctx, dest); 255 tcg_gen_exit_tb(ctx->base.tb, n); 256 } else { 257 gen_set_pc_imm(ctx, dest); 258 tcg_gen_lookup_and_goto_ptr(); 259 } 260 } 261 262 /* 263 * Wrappers for getting reg values. 264 * 265 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 266 * constant zero as a source, and an uninitialized sink as destination. 267 * 268 * Further, we may provide an extension for word operations. 269 */ 270 static TCGv temp_new(DisasContext *ctx) 271 { 272 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 273 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 274 } 275 276 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 277 { 278 TCGv t; 279 280 if (reg_num == 0) { 281 return ctx->zero; 282 } 283 284 switch (get_ol(ctx)) { 285 case MXL_RV32: 286 switch (ext) { 287 case EXT_NONE: 288 break; 289 case EXT_SIGN: 290 t = temp_new(ctx); 291 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 292 return t; 293 case EXT_ZERO: 294 t = temp_new(ctx); 295 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 296 return t; 297 default: 298 g_assert_not_reached(); 299 } 300 break; 301 case MXL_RV64: 302 case MXL_RV128: 303 break; 304 default: 305 g_assert_not_reached(); 306 } 307 return cpu_gpr[reg_num]; 308 } 309 310 static TCGv get_gprh(DisasContext *ctx, int reg_num) 311 { 312 assert(get_xl(ctx) == MXL_RV128); 313 if (reg_num == 0) { 314 return ctx->zero; 315 } 316 return cpu_gprh[reg_num]; 317 } 318 319 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 320 { 321 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 322 return temp_new(ctx); 323 } 324 return cpu_gpr[reg_num]; 325 } 326 327 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 328 { 329 if (reg_num == 0) { 330 return temp_new(ctx); 331 } 332 return cpu_gprh[reg_num]; 333 } 334 335 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 336 { 337 if (reg_num != 0) { 338 switch (get_ol(ctx)) { 339 case MXL_RV32: 340 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 341 break; 342 case MXL_RV64: 343 case MXL_RV128: 344 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 345 break; 346 default: 347 g_assert_not_reached(); 348 } 349 350 if (get_xl_max(ctx) == MXL_RV128) { 351 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 352 } 353 } 354 } 355 356 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 357 { 358 if (reg_num != 0) { 359 switch (get_ol(ctx)) { 360 case MXL_RV32: 361 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 362 break; 363 case MXL_RV64: 364 case MXL_RV128: 365 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 366 break; 367 default: 368 g_assert_not_reached(); 369 } 370 371 if (get_xl_max(ctx) == MXL_RV128) { 372 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 373 } 374 } 375 } 376 377 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 378 { 379 assert(get_ol(ctx) == MXL_RV128); 380 if (reg_num != 0) { 381 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 382 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 383 } 384 } 385 386 static TCGv_i64 ftemp_new(DisasContext *ctx) 387 { 388 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 389 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 390 } 391 392 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 393 { 394 if (!ctx->cfg_ptr->ext_zfinx) { 395 return cpu_fpr[reg_num]; 396 } 397 398 if (reg_num == 0) { 399 return tcg_constant_i64(0); 400 } 401 switch (get_xl(ctx)) { 402 case MXL_RV32: 403 #ifdef TARGET_RISCV32 404 { 405 TCGv_i64 t = ftemp_new(ctx); 406 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 407 return t; 408 } 409 #else 410 /* fall through */ 411 case MXL_RV64: 412 return cpu_gpr[reg_num]; 413 #endif 414 default: 415 g_assert_not_reached(); 416 } 417 } 418 419 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 420 { 421 if (!ctx->cfg_ptr->ext_zfinx) { 422 return cpu_fpr[reg_num]; 423 } 424 425 if (reg_num == 0) { 426 return tcg_constant_i64(0); 427 } 428 switch (get_xl(ctx)) { 429 case MXL_RV32: 430 { 431 TCGv_i64 t = ftemp_new(ctx); 432 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 433 return t; 434 } 435 #ifdef TARGET_RISCV64 436 case MXL_RV64: 437 return cpu_gpr[reg_num]; 438 #endif 439 default: 440 g_assert_not_reached(); 441 } 442 } 443 444 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 445 { 446 if (!ctx->cfg_ptr->ext_zfinx) { 447 return cpu_fpr[reg_num]; 448 } 449 450 if (reg_num == 0) { 451 return ftemp_new(ctx); 452 } 453 454 switch (get_xl(ctx)) { 455 case MXL_RV32: 456 return ftemp_new(ctx); 457 #ifdef TARGET_RISCV64 458 case MXL_RV64: 459 return cpu_gpr[reg_num]; 460 #endif 461 default: 462 g_assert_not_reached(); 463 } 464 } 465 466 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 467 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 468 { 469 if (!ctx->cfg_ptr->ext_zfinx) { 470 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 471 return; 472 } 473 if (reg_num != 0) { 474 switch (get_xl(ctx)) { 475 case MXL_RV32: 476 #ifdef TARGET_RISCV32 477 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 478 break; 479 #else 480 /* fall through */ 481 case MXL_RV64: 482 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 483 break; 484 #endif 485 default: 486 g_assert_not_reached(); 487 } 488 } 489 } 490 491 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 492 { 493 if (!ctx->cfg_ptr->ext_zfinx) { 494 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 495 return; 496 } 497 498 if (reg_num != 0) { 499 switch (get_xl(ctx)) { 500 case MXL_RV32: 501 #ifdef TARGET_RISCV32 502 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 503 break; 504 #else 505 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 506 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 507 break; 508 case MXL_RV64: 509 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 510 break; 511 #endif 512 default: 513 g_assert_not_reached(); 514 } 515 } 516 } 517 518 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 519 { 520 target_ulong next_pc; 521 522 /* check misaligned: */ 523 next_pc = ctx->base.pc_next + imm; 524 if (!has_ext(ctx, RVC)) { 525 if ((next_pc & 0x3) != 0) { 526 gen_exception_inst_addr_mis(ctx); 527 return; 528 } 529 } 530 531 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 532 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 533 ctx->base.is_jmp = DISAS_NORETURN; 534 } 535 536 /* Compute a canonical address from a register plus offset. */ 537 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 538 { 539 TCGv addr = temp_new(ctx); 540 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 541 542 tcg_gen_addi_tl(addr, src1, imm); 543 if (ctx->pm_mask_enabled) { 544 tcg_gen_and_tl(addr, addr, pm_mask); 545 } else if (get_xl(ctx) == MXL_RV32) { 546 tcg_gen_ext32u_tl(addr, addr); 547 } 548 if (ctx->pm_base_enabled) { 549 tcg_gen_or_tl(addr, addr, pm_base); 550 } 551 return addr; 552 } 553 554 #ifndef CONFIG_USER_ONLY 555 /* The states of mstatus_fs are: 556 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 557 * We will have already diagnosed disabled state, 558 * and need to turn initial/clean into dirty. 559 */ 560 static void mark_fs_dirty(DisasContext *ctx) 561 { 562 TCGv tmp; 563 564 if (!has_ext(ctx, RVF)) { 565 return; 566 } 567 568 if (ctx->mstatus_fs != MSTATUS_FS) { 569 /* Remember the state change for the rest of the TB. */ 570 ctx->mstatus_fs = MSTATUS_FS; 571 572 tmp = tcg_temp_new(); 573 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 574 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 575 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 576 tcg_temp_free(tmp); 577 } 578 579 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 580 /* Remember the stage change for the rest of the TB. */ 581 ctx->mstatus_hs_fs = MSTATUS_FS; 582 583 tmp = tcg_temp_new(); 584 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 585 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 586 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 587 tcg_temp_free(tmp); 588 } 589 } 590 #else 591 static inline void mark_fs_dirty(DisasContext *ctx) { } 592 #endif 593 594 #ifndef CONFIG_USER_ONLY 595 /* The states of mstatus_vs are: 596 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 597 * We will have already diagnosed disabled state, 598 * and need to turn initial/clean into dirty. 599 */ 600 static void mark_vs_dirty(DisasContext *ctx) 601 { 602 TCGv tmp; 603 604 if (ctx->mstatus_vs != MSTATUS_VS) { 605 /* Remember the state change for the rest of the TB. */ 606 ctx->mstatus_vs = MSTATUS_VS; 607 608 tmp = tcg_temp_new(); 609 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 610 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 611 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 612 tcg_temp_free(tmp); 613 } 614 615 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 616 /* Remember the stage change for the rest of the TB. */ 617 ctx->mstatus_hs_vs = MSTATUS_VS; 618 619 tmp = tcg_temp_new(); 620 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 621 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 622 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 623 tcg_temp_free(tmp); 624 } 625 } 626 #else 627 static inline void mark_vs_dirty(DisasContext *ctx) { } 628 #endif 629 630 static void gen_set_rm(DisasContext *ctx, int rm) 631 { 632 if (ctx->frm == rm) { 633 return; 634 } 635 ctx->frm = rm; 636 637 if (rm == RISCV_FRM_ROD) { 638 gen_helper_set_rod_rounding_mode(cpu_env); 639 return; 640 } 641 642 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 643 } 644 645 static int ex_plus_1(DisasContext *ctx, int nf) 646 { 647 return nf + 1; 648 } 649 650 #define EX_SH(amount) \ 651 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 652 { \ 653 return imm << amount; \ 654 } 655 EX_SH(1) 656 EX_SH(2) 657 EX_SH(3) 658 EX_SH(4) 659 EX_SH(12) 660 661 #define REQUIRE_EXT(ctx, ext) do { \ 662 if (!has_ext(ctx, ext)) { \ 663 return false; \ 664 } \ 665 } while (0) 666 667 #define REQUIRE_32BIT(ctx) do { \ 668 if (get_xl(ctx) != MXL_RV32) { \ 669 return false; \ 670 } \ 671 } while (0) 672 673 #define REQUIRE_64BIT(ctx) do { \ 674 if (get_xl(ctx) != MXL_RV64) { \ 675 return false; \ 676 } \ 677 } while (0) 678 679 #define REQUIRE_128BIT(ctx) do { \ 680 if (get_xl(ctx) != MXL_RV128) { \ 681 return false; \ 682 } \ 683 } while (0) 684 685 #define REQUIRE_64_OR_128BIT(ctx) do { \ 686 if (get_xl(ctx) == MXL_RV32) { \ 687 return false; \ 688 } \ 689 } while (0) 690 691 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 692 if (!ctx->cfg_ptr->ext_##A && \ 693 !ctx->cfg_ptr->ext_##B) { \ 694 return false; \ 695 } \ 696 } while (0) 697 698 static int ex_rvc_register(DisasContext *ctx, int reg) 699 { 700 return 8 + reg; 701 } 702 703 static int ex_rvc_shifti(DisasContext *ctx, int imm) 704 { 705 /* For RV128 a shamt of 0 means a shift by 64. */ 706 return imm ? imm : 64; 707 } 708 709 /* Include the auto-generated decoder for 32 bit insn */ 710 #include "decode-insn32.c.inc" 711 712 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 713 void (*func)(TCGv, TCGv, target_long)) 714 { 715 TCGv dest = dest_gpr(ctx, a->rd); 716 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 717 718 func(dest, src1, a->imm); 719 720 if (get_xl(ctx) == MXL_RV128) { 721 TCGv src1h = get_gprh(ctx, a->rs1); 722 TCGv desth = dest_gprh(ctx, a->rd); 723 724 func(desth, src1h, -(a->imm < 0)); 725 gen_set_gpr128(ctx, a->rd, dest, desth); 726 } else { 727 gen_set_gpr(ctx, a->rd, dest); 728 } 729 730 return true; 731 } 732 733 static bool gen_logic(DisasContext *ctx, arg_r *a, 734 void (*func)(TCGv, TCGv, TCGv)) 735 { 736 TCGv dest = dest_gpr(ctx, a->rd); 737 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 738 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 739 740 func(dest, src1, src2); 741 742 if (get_xl(ctx) == MXL_RV128) { 743 TCGv src1h = get_gprh(ctx, a->rs1); 744 TCGv src2h = get_gprh(ctx, a->rs2); 745 TCGv desth = dest_gprh(ctx, a->rd); 746 747 func(desth, src1h, src2h); 748 gen_set_gpr128(ctx, a->rd, dest, desth); 749 } else { 750 gen_set_gpr(ctx, a->rd, dest); 751 } 752 753 return true; 754 } 755 756 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 757 void (*func)(TCGv, TCGv, target_long), 758 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 759 { 760 TCGv dest = dest_gpr(ctx, a->rd); 761 TCGv src1 = get_gpr(ctx, a->rs1, ext); 762 763 if (get_ol(ctx) < MXL_RV128) { 764 func(dest, src1, a->imm); 765 gen_set_gpr(ctx, a->rd, dest); 766 } else { 767 if (f128 == NULL) { 768 return false; 769 } 770 771 TCGv src1h = get_gprh(ctx, a->rs1); 772 TCGv desth = dest_gprh(ctx, a->rd); 773 774 f128(dest, desth, src1, src1h, a->imm); 775 gen_set_gpr128(ctx, a->rd, dest, desth); 776 } 777 return true; 778 } 779 780 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 781 void (*func)(TCGv, TCGv, TCGv), 782 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 783 { 784 TCGv dest = dest_gpr(ctx, a->rd); 785 TCGv src1 = get_gpr(ctx, a->rs1, ext); 786 TCGv src2 = tcg_constant_tl(a->imm); 787 788 if (get_ol(ctx) < MXL_RV128) { 789 func(dest, src1, src2); 790 gen_set_gpr(ctx, a->rd, dest); 791 } else { 792 if (f128 == NULL) { 793 return false; 794 } 795 796 TCGv src1h = get_gprh(ctx, a->rs1); 797 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 798 TCGv desth = dest_gprh(ctx, a->rd); 799 800 f128(dest, desth, src1, src1h, src2, src2h); 801 gen_set_gpr128(ctx, a->rd, dest, desth); 802 } 803 return true; 804 } 805 806 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 807 void (*func)(TCGv, TCGv, TCGv), 808 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 809 { 810 TCGv dest = dest_gpr(ctx, a->rd); 811 TCGv src1 = get_gpr(ctx, a->rs1, ext); 812 TCGv src2 = get_gpr(ctx, a->rs2, ext); 813 814 if (get_ol(ctx) < MXL_RV128) { 815 func(dest, src1, src2); 816 gen_set_gpr(ctx, a->rd, dest); 817 } else { 818 if (f128 == NULL) { 819 return false; 820 } 821 822 TCGv src1h = get_gprh(ctx, a->rs1); 823 TCGv src2h = get_gprh(ctx, a->rs2); 824 TCGv desth = dest_gprh(ctx, a->rd); 825 826 f128(dest, desth, src1, src1h, src2, src2h); 827 gen_set_gpr128(ctx, a->rd, dest, desth); 828 } 829 return true; 830 } 831 832 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 833 void (*f_tl)(TCGv, TCGv, TCGv), 834 void (*f_32)(TCGv, TCGv, TCGv), 835 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 836 { 837 int olen = get_olen(ctx); 838 839 if (olen != TARGET_LONG_BITS) { 840 if (olen == 32) { 841 f_tl = f_32; 842 } else if (olen != 128) { 843 g_assert_not_reached(); 844 } 845 } 846 return gen_arith(ctx, a, ext, f_tl, f_128); 847 } 848 849 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 850 void (*func)(TCGv, TCGv, target_long), 851 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 852 { 853 TCGv dest, src1; 854 int max_len = get_olen(ctx); 855 856 if (a->shamt >= max_len) { 857 return false; 858 } 859 860 dest = dest_gpr(ctx, a->rd); 861 src1 = get_gpr(ctx, a->rs1, ext); 862 863 if (max_len < 128) { 864 func(dest, src1, a->shamt); 865 gen_set_gpr(ctx, a->rd, dest); 866 } else { 867 TCGv src1h = get_gprh(ctx, a->rs1); 868 TCGv desth = dest_gprh(ctx, a->rd); 869 870 if (f128 == NULL) { 871 return false; 872 } 873 f128(dest, desth, src1, src1h, a->shamt); 874 gen_set_gpr128(ctx, a->rd, dest, desth); 875 } 876 return true; 877 } 878 879 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 880 DisasExtend ext, 881 void (*f_tl)(TCGv, TCGv, target_long), 882 void (*f_32)(TCGv, TCGv, target_long), 883 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 884 target_long)) 885 { 886 int olen = get_olen(ctx); 887 if (olen != TARGET_LONG_BITS) { 888 if (olen == 32) { 889 f_tl = f_32; 890 } else if (olen != 128) { 891 g_assert_not_reached(); 892 } 893 } 894 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 895 } 896 897 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 898 void (*func)(TCGv, TCGv, TCGv)) 899 { 900 TCGv dest, src1, src2; 901 int max_len = get_olen(ctx); 902 903 if (a->shamt >= max_len) { 904 return false; 905 } 906 907 dest = dest_gpr(ctx, a->rd); 908 src1 = get_gpr(ctx, a->rs1, ext); 909 src2 = tcg_constant_tl(a->shamt); 910 911 func(dest, src1, src2); 912 913 gen_set_gpr(ctx, a->rd, dest); 914 return true; 915 } 916 917 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 918 void (*func)(TCGv, TCGv, TCGv), 919 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 920 { 921 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 922 TCGv ext2 = tcg_temp_new(); 923 int max_len = get_olen(ctx); 924 925 tcg_gen_andi_tl(ext2, src2, max_len - 1); 926 927 TCGv dest = dest_gpr(ctx, a->rd); 928 TCGv src1 = get_gpr(ctx, a->rs1, ext); 929 930 if (max_len < 128) { 931 func(dest, src1, ext2); 932 gen_set_gpr(ctx, a->rd, dest); 933 } else { 934 TCGv src1h = get_gprh(ctx, a->rs1); 935 TCGv desth = dest_gprh(ctx, a->rd); 936 937 if (f128 == NULL) { 938 return false; 939 } 940 f128(dest, desth, src1, src1h, ext2); 941 gen_set_gpr128(ctx, a->rd, dest, desth); 942 } 943 tcg_temp_free(ext2); 944 return true; 945 } 946 947 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 948 void (*f_tl)(TCGv, TCGv, TCGv), 949 void (*f_32)(TCGv, TCGv, TCGv), 950 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 951 { 952 int olen = get_olen(ctx); 953 if (olen != TARGET_LONG_BITS) { 954 if (olen == 32) { 955 f_tl = f_32; 956 } else if (olen != 128) { 957 g_assert_not_reached(); 958 } 959 } 960 return gen_shift(ctx, a, ext, f_tl, f_128); 961 } 962 963 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 964 void (*func)(TCGv, TCGv)) 965 { 966 TCGv dest = dest_gpr(ctx, a->rd); 967 TCGv src1 = get_gpr(ctx, a->rs1, ext); 968 969 func(dest, src1); 970 971 gen_set_gpr(ctx, a->rd, dest); 972 return true; 973 } 974 975 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 976 void (*f_tl)(TCGv, TCGv), 977 void (*f_32)(TCGv, TCGv)) 978 { 979 int olen = get_olen(ctx); 980 981 if (olen != TARGET_LONG_BITS) { 982 if (olen == 32) { 983 f_tl = f_32; 984 } else { 985 g_assert_not_reached(); 986 } 987 } 988 return gen_unary(ctx, a, ext, f_tl); 989 } 990 991 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 992 { 993 DisasContext *ctx = container_of(dcbase, DisasContext, base); 994 CPUState *cpu = ctx->cs; 995 CPURISCVState *env = cpu->env_ptr; 996 997 return cpu_ldl_code(env, pc); 998 } 999 1000 /* Include insn module translation function */ 1001 #include "insn_trans/trans_rvi.c.inc" 1002 #include "insn_trans/trans_rvm.c.inc" 1003 #include "insn_trans/trans_rva.c.inc" 1004 #include "insn_trans/trans_rvf.c.inc" 1005 #include "insn_trans/trans_rvd.c.inc" 1006 #include "insn_trans/trans_rvh.c.inc" 1007 #include "insn_trans/trans_rvv.c.inc" 1008 #include "insn_trans/trans_rvb.c.inc" 1009 #include "insn_trans/trans_rvzfh.c.inc" 1010 #include "insn_trans/trans_rvk.c.inc" 1011 #include "insn_trans/trans_privileged.c.inc" 1012 #include "insn_trans/trans_svinval.c.inc" 1013 #include "insn_trans/trans_xventanacondops.c.inc" 1014 1015 /* Include the auto-generated decoder for 16 bit insn */ 1016 #include "decode-insn16.c.inc" 1017 /* Include decoders for factored-out extensions */ 1018 #include "decode-XVentanaCondOps.c.inc" 1019 1020 static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) 1021 { 1022 assert(ctx->insn_start != NULL); 1023 tcg_set_insn_start_param(ctx->insn_start, 1, opc); 1024 ctx->insn_start = NULL; 1025 } 1026 1027 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1028 { 1029 /* 1030 * A table with predicate (i.e., guard) functions and decoder functions 1031 * that are tested in-order until a decoder matches onto the opcode. 1032 */ 1033 static const struct { 1034 bool (*guard_func)(DisasContext *); 1035 bool (*decode_func)(DisasContext *, uint32_t); 1036 } decoders[] = { 1037 { always_true_p, decode_insn32 }, 1038 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1039 }; 1040 1041 /* Check for compressed insn */ 1042 if (extract16(opcode, 0, 2) != 3) { 1043 decode_save_opc(ctx, opcode); 1044 if (!has_ext(ctx, RVC)) { 1045 gen_exception_illegal(ctx); 1046 } else { 1047 ctx->opcode = opcode; 1048 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1049 if (decode_insn16(ctx, opcode)) { 1050 return; 1051 } 1052 } 1053 } else { 1054 uint32_t opcode32 = opcode; 1055 opcode32 = deposit32(opcode32, 16, 16, 1056 translator_lduw(env, &ctx->base, 1057 ctx->base.pc_next + 2)); 1058 decode_save_opc(ctx, opcode32); 1059 ctx->opcode = opcode32; 1060 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1061 1062 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1063 if (decoders[i].guard_func(ctx) && 1064 decoders[i].decode_func(ctx, opcode32)) { 1065 return; 1066 } 1067 } 1068 } 1069 1070 gen_exception_illegal(ctx); 1071 } 1072 1073 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1074 { 1075 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1076 CPURISCVState *env = cs->env_ptr; 1077 RISCVCPU *cpu = RISCV_CPU(cs); 1078 uint32_t tb_flags = ctx->base.tb->flags; 1079 1080 ctx->pc_succ_insn = ctx->base.pc_first; 1081 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1082 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1083 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1084 ctx->priv_ver = env->priv_ver; 1085 #if !defined(CONFIG_USER_ONLY) 1086 if (riscv_has_ext(env, RVH)) { 1087 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1088 } else { 1089 ctx->virt_enabled = false; 1090 } 1091 #else 1092 ctx->virt_enabled = false; 1093 #endif 1094 ctx->misa_ext = env->misa_ext; 1095 ctx->frm = -1; /* unknown rounding mode */ 1096 ctx->cfg_ptr = &(cpu->cfg); 1097 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1098 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1099 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1100 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1101 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1102 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1103 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1104 ctx->vstart = env->vstart; 1105 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1106 ctx->misa_mxl_max = env->misa_mxl_max; 1107 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1108 ctx->cs = cs; 1109 ctx->ntemp = 0; 1110 memset(ctx->temp, 0, sizeof(ctx->temp)); 1111 ctx->nftemp = 0; 1112 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1113 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1114 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1115 ctx->zero = tcg_constant_tl(0); 1116 } 1117 1118 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1119 { 1120 } 1121 1122 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1123 { 1124 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1125 1126 tcg_gen_insn_start(ctx->base.pc_next, 0); 1127 ctx->insn_start = tcg_last_op(); 1128 } 1129 1130 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1131 { 1132 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1133 CPURISCVState *env = cpu->env_ptr; 1134 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1135 int i; 1136 1137 ctx->ol = ctx->xl; 1138 decode_opc(env, ctx, opcode16); 1139 ctx->base.pc_next = ctx->pc_succ_insn; 1140 1141 for (i = ctx->ntemp - 1; i >= 0; --i) { 1142 tcg_temp_free(ctx->temp[i]); 1143 ctx->temp[i] = NULL; 1144 } 1145 ctx->ntemp = 0; 1146 for (i = ctx->nftemp - 1; i >= 0; --i) { 1147 tcg_temp_free_i64(ctx->ftemp[i]); 1148 ctx->ftemp[i] = NULL; 1149 } 1150 ctx->nftemp = 0; 1151 1152 if (ctx->base.is_jmp == DISAS_NEXT) { 1153 target_ulong page_start; 1154 1155 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1156 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 1157 ctx->base.is_jmp = DISAS_TOO_MANY; 1158 } 1159 } 1160 } 1161 1162 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1163 { 1164 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1165 1166 switch (ctx->base.is_jmp) { 1167 case DISAS_TOO_MANY: 1168 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1169 break; 1170 case DISAS_NORETURN: 1171 break; 1172 default: 1173 g_assert_not_reached(); 1174 } 1175 } 1176 1177 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1178 CPUState *cpu, FILE *logfile) 1179 { 1180 #ifndef CONFIG_USER_ONLY 1181 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1182 CPURISCVState *env = &rvcpu->env; 1183 #endif 1184 1185 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1186 #ifndef CONFIG_USER_ONLY 1187 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1188 env->priv, env->virt); 1189 #endif 1190 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1191 } 1192 1193 static const TranslatorOps riscv_tr_ops = { 1194 .init_disas_context = riscv_tr_init_disas_context, 1195 .tb_start = riscv_tr_tb_start, 1196 .insn_start = riscv_tr_insn_start, 1197 .translate_insn = riscv_tr_translate_insn, 1198 .tb_stop = riscv_tr_tb_stop, 1199 .disas_log = riscv_tr_disas_log, 1200 }; 1201 1202 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1203 { 1204 DisasContext ctx; 1205 1206 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1207 } 1208 1209 void riscv_translate_init(void) 1210 { 1211 int i; 1212 1213 /* 1214 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1215 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1216 * unless you specifically block reads/writes to reg 0. 1217 */ 1218 cpu_gpr[0] = NULL; 1219 cpu_gprh[0] = NULL; 1220 1221 for (i = 1; i < 32; i++) { 1222 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1223 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1224 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1225 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1226 } 1227 1228 for (i = 0; i < 32; i++) { 1229 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1230 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1231 } 1232 1233 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1234 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1235 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1236 "vstart"); 1237 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1238 "load_res"); 1239 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1240 "load_val"); 1241 /* Assign PM CSRs to tcg globals */ 1242 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1243 "pmmask"); 1244 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1245 "pmbase"); 1246 } 1247