xref: /openbmc/qemu/target/riscv/translate.c (revision f1966390)
1 /*
2  * RISC-V emulation for qemu: main translation routines.
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  *
6  * This program is free software; you can redistribute it and/or modify it
7  * under the terms and conditions of the GNU General Public License,
8  * version 2 or later, as published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope it will be useful, but WITHOUT
11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  * more details.
14  *
15  * You should have received a copy of the GNU General Public License along with
16  * this program.  If not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include "qemu/osdep.h"
20 #include "qemu/log.h"
21 #include "cpu.h"
22 #include "tcg/tcg-op.h"
23 #include "disas/disas.h"
24 #include "exec/cpu_ldst.h"
25 #include "exec/exec-all.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28 
29 #include "exec/translator.h"
30 #include "exec/log.h"
31 #include "semihosting/semihost.h"
32 
33 #include "instmap.h"
34 #include "internals.h"
35 
36 /* global register indices */
37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart;
38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
39 static TCGv load_res;
40 static TCGv load_val;
41 /* globals for PM CSRs */
42 static TCGv pm_mask;
43 static TCGv pm_base;
44 
45 #include "exec/gen-icount.h"
46 
47 /*
48  * If an operation is being performed on less than TARGET_LONG_BITS,
49  * it may require the inputs to be sign- or zero-extended; which will
50  * depend on the exact operation being performed.
51  */
52 typedef enum {
53     EXT_NONE,
54     EXT_SIGN,
55     EXT_ZERO,
56 } DisasExtend;
57 
58 typedef struct DisasContext {
59     DisasContextBase base;
60     /* pc_succ_insn points to the instruction following base.pc_next */
61     target_ulong pc_succ_insn;
62     target_ulong priv_ver;
63     RISCVMXL misa_mxl_max;
64     RISCVMXL xl;
65     uint32_t misa_ext;
66     uint32_t opcode;
67     uint32_t mstatus_fs;
68     uint32_t mstatus_vs;
69     uint32_t mstatus_hs_fs;
70     uint32_t mstatus_hs_vs;
71     uint32_t mem_idx;
72     /*
73      * Remember the rounding mode encoded in the previous fp instruction,
74      * which we have already installed into env->fp_status.  Or -1 for
75      * no previous fp instruction.  Note that we exit the TB when writing
76      * to any system register, which includes CSR_FRM, so we do not have
77      * to reset this known value.
78      */
79     int frm;
80     RISCVMXL ol;
81     bool virt_inst_excp;
82     bool virt_enabled;
83     const RISCVCPUConfig *cfg_ptr;
84     bool hlsx;
85     /* vector extension */
86     bool vill;
87     /*
88      * Encode LMUL to lmul as follows:
89      *     LMUL    vlmul    lmul
90      *      1       000       0
91      *      2       001       1
92      *      4       010       2
93      *      8       011       3
94      *      -       100       -
95      *     1/8      101      -3
96      *     1/4      110      -2
97      *     1/2      111      -1
98      */
99     int8_t lmul;
100     uint8_t sew;
101     uint8_t vta;
102     uint8_t vma;
103     bool cfg_vta_all_1s;
104     target_ulong vstart;
105     bool vl_eq_vlmax;
106     CPUState *cs;
107     TCGv zero;
108     /* PointerMasking extension */
109     bool pm_mask_enabled;
110     bool pm_base_enabled;
111     /* Use icount trigger for native debug */
112     bool itrigger;
113     /* FRM is known to contain a valid value. */
114     bool frm_valid;
115     /* TCG of the current insn_start */
116     TCGOp *insn_start;
117 } DisasContext;
118 
119 static inline bool has_ext(DisasContext *ctx, uint32_t ext)
120 {
121     return ctx->misa_ext & ext;
122 }
123 
124 static bool always_true_p(DisasContext *ctx  __attribute__((__unused__)))
125 {
126     return true;
127 }
128 
129 static bool has_xthead_p(DisasContext *ctx  __attribute__((__unused__)))
130 {
131     return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb ||
132            ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo ||
133            ctx->cfg_ptr->ext_xtheadcondmov ||
134            ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv ||
135            ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx ||
136            ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync;
137 }
138 
139 #define MATERIALISE_EXT_PREDICATE(ext)  \
140     static bool has_ ## ext ## _p(DisasContext *ctx)    \
141     { \
142         return ctx->cfg_ptr->ext_ ## ext ; \
143     }
144 
145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
146 
147 #ifdef TARGET_RISCV32
148 #define get_xl(ctx)    MXL_RV32
149 #elif defined(CONFIG_USER_ONLY)
150 #define get_xl(ctx)    MXL_RV64
151 #else
152 #define get_xl(ctx)    ((ctx)->xl)
153 #endif
154 
155 /* The word size for this machine mode. */
156 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx)
157 {
158     return 16 << get_xl(ctx);
159 }
160 
161 /* The operation length, as opposed to the xlen. */
162 #ifdef TARGET_RISCV32
163 #define get_ol(ctx)    MXL_RV32
164 #else
165 #define get_ol(ctx)    ((ctx)->ol)
166 #endif
167 
168 static inline int get_olen(DisasContext *ctx)
169 {
170     return 16 << get_ol(ctx);
171 }
172 
173 /* The maximum register length */
174 #ifdef TARGET_RISCV32
175 #define get_xl_max(ctx)    MXL_RV32
176 #else
177 #define get_xl_max(ctx)    ((ctx)->misa_mxl_max)
178 #endif
179 
180 /*
181  * RISC-V requires NaN-boxing of narrower width floating point values.
182  * This applies when a 32-bit value is assigned to a 64-bit FP register.
183  * For consistency and simplicity, we nanbox results even when the RVD
184  * extension is not present.
185  */
186 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in)
187 {
188     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32));
189 }
190 
191 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in)
192 {
193     tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48));
194 }
195 
196 /*
197  * A narrow n-bit operation, where n < FLEN, checks that input operands
198  * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1.
199  * If so, the least-significant bits of the input are used, otherwise the
200  * input value is treated as an n-bit canonical NaN (v2.2 section 9.2).
201  *
202  * Here, the result is always nan-boxed, even the canonical nan.
203  */
204 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in)
205 {
206     TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull);
207     TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull);
208 
209     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
210 }
211 
212 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
213 {
214     TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull);
215     TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull);
216 
217     tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
218 }
219 
220 static void decode_save_opc(DisasContext *ctx)
221 {
222     assert(ctx->insn_start != NULL);
223     tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode);
224     ctx->insn_start = NULL;
225 }
226 
227 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest)
228 {
229     if (get_xl(ctx) == MXL_RV32) {
230         dest = (int32_t)dest;
231     }
232     tcg_gen_movi_tl(cpu_pc, dest);
233 }
234 
235 static void gen_set_pc(DisasContext *ctx, TCGv dest)
236 {
237     if (get_xl(ctx) == MXL_RV32) {
238         tcg_gen_ext32s_tl(cpu_pc, dest);
239     } else {
240         tcg_gen_mov_tl(cpu_pc, dest);
241     }
242 }
243 
244 static void generate_exception(DisasContext *ctx, int excp)
245 {
246     gen_set_pc_imm(ctx, ctx->base.pc_next);
247     gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
248     ctx->base.is_jmp = DISAS_NORETURN;
249 }
250 
251 static void gen_exception_illegal(DisasContext *ctx)
252 {
253     tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env,
254                    offsetof(CPURISCVState, bins));
255     if (ctx->virt_inst_excp) {
256         generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT);
257     } else {
258         generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
259     }
260 }
261 
262 static void gen_exception_inst_addr_mis(DisasContext *ctx)
263 {
264     tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr));
265     generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS);
266 }
267 
268 static void lookup_and_goto_ptr(DisasContext *ctx)
269 {
270 #ifndef CONFIG_USER_ONLY
271     if (ctx->itrigger) {
272         gen_helper_itrigger_match(cpu_env);
273     }
274 #endif
275     tcg_gen_lookup_and_goto_ptr();
276 }
277 
278 static void exit_tb(DisasContext *ctx)
279 {
280 #ifndef CONFIG_USER_ONLY
281     if (ctx->itrigger) {
282         gen_helper_itrigger_match(cpu_env);
283     }
284 #endif
285     tcg_gen_exit_tb(NULL, 0);
286 }
287 
288 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
289 {
290      /*
291       * Under itrigger, instruction executes one by one like singlestep,
292       * direct block chain benefits will be small.
293       */
294     if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) {
295         tcg_gen_goto_tb(n);
296         gen_set_pc_imm(ctx, dest);
297         tcg_gen_exit_tb(ctx->base.tb, n);
298     } else {
299         gen_set_pc_imm(ctx, dest);
300         lookup_and_goto_ptr(ctx);
301     }
302 }
303 
304 /*
305  * Wrappers for getting reg values.
306  *
307  * The $zero register does not have cpu_gpr[0] allocated -- we supply the
308  * constant zero as a source, and an uninitialized sink as destination.
309  *
310  * Further, we may provide an extension for word operations.
311  */
312 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext)
313 {
314     TCGv t;
315 
316     if (reg_num == 0) {
317         return ctx->zero;
318     }
319 
320     switch (get_ol(ctx)) {
321     case MXL_RV32:
322         switch (ext) {
323         case EXT_NONE:
324             break;
325         case EXT_SIGN:
326             t = tcg_temp_new();
327             tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]);
328             return t;
329         case EXT_ZERO:
330             t = tcg_temp_new();
331             tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]);
332             return t;
333         default:
334             g_assert_not_reached();
335         }
336         break;
337     case MXL_RV64:
338     case MXL_RV128:
339         break;
340     default:
341         g_assert_not_reached();
342     }
343     return cpu_gpr[reg_num];
344 }
345 
346 static TCGv get_gprh(DisasContext *ctx, int reg_num)
347 {
348     assert(get_xl(ctx) == MXL_RV128);
349     if (reg_num == 0) {
350         return ctx->zero;
351     }
352     return cpu_gprh[reg_num];
353 }
354 
355 static TCGv dest_gpr(DisasContext *ctx, int reg_num)
356 {
357     if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) {
358         return tcg_temp_new();
359     }
360     return cpu_gpr[reg_num];
361 }
362 
363 static TCGv dest_gprh(DisasContext *ctx, int reg_num)
364 {
365     if (reg_num == 0) {
366         return tcg_temp_new();
367     }
368     return cpu_gprh[reg_num];
369 }
370 
371 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t)
372 {
373     if (reg_num != 0) {
374         switch (get_ol(ctx)) {
375         case MXL_RV32:
376             tcg_gen_ext32s_tl(cpu_gpr[reg_num], t);
377             break;
378         case MXL_RV64:
379         case MXL_RV128:
380             tcg_gen_mov_tl(cpu_gpr[reg_num], t);
381             break;
382         default:
383             g_assert_not_reached();
384         }
385 
386         if (get_xl_max(ctx) == MXL_RV128) {
387             tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63);
388         }
389     }
390 }
391 
392 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm)
393 {
394     if (reg_num != 0) {
395         switch (get_ol(ctx)) {
396         case MXL_RV32:
397             tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm);
398             break;
399         case MXL_RV64:
400         case MXL_RV128:
401             tcg_gen_movi_tl(cpu_gpr[reg_num], imm);
402             break;
403         default:
404             g_assert_not_reached();
405         }
406 
407         if (get_xl_max(ctx) == MXL_RV128) {
408             tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0));
409         }
410     }
411 }
412 
413 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh)
414 {
415     assert(get_ol(ctx) == MXL_RV128);
416     if (reg_num != 0) {
417         tcg_gen_mov_tl(cpu_gpr[reg_num], rl);
418         tcg_gen_mov_tl(cpu_gprh[reg_num], rh);
419     }
420 }
421 
422 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num)
423 {
424     if (!ctx->cfg_ptr->ext_zfinx) {
425         return cpu_fpr[reg_num];
426     }
427 
428     if (reg_num == 0) {
429         return tcg_constant_i64(0);
430     }
431     switch (get_xl(ctx)) {
432     case MXL_RV32:
433 #ifdef TARGET_RISCV32
434     {
435         TCGv_i64 t = tcg_temp_new_i64();
436         tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]);
437         return t;
438     }
439 #else
440     /* fall through */
441     case MXL_RV64:
442         return cpu_gpr[reg_num];
443 #endif
444     default:
445         g_assert_not_reached();
446     }
447 }
448 
449 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num)
450 {
451     if (!ctx->cfg_ptr->ext_zfinx) {
452         return cpu_fpr[reg_num];
453     }
454 
455     if (reg_num == 0) {
456         return tcg_constant_i64(0);
457     }
458     switch (get_xl(ctx)) {
459     case MXL_RV32:
460     {
461         TCGv_i64 t = tcg_temp_new_i64();
462         tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]);
463         return t;
464     }
465 #ifdef TARGET_RISCV64
466     case MXL_RV64:
467         return cpu_gpr[reg_num];
468 #endif
469     default:
470         g_assert_not_reached();
471     }
472 }
473 
474 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num)
475 {
476     if (!ctx->cfg_ptr->ext_zfinx) {
477         return cpu_fpr[reg_num];
478     }
479 
480     if (reg_num == 0) {
481         return tcg_temp_new_i64();
482     }
483 
484     switch (get_xl(ctx)) {
485     case MXL_RV32:
486         return tcg_temp_new_i64();
487 #ifdef TARGET_RISCV64
488     case MXL_RV64:
489         return cpu_gpr[reg_num];
490 #endif
491     default:
492         g_assert_not_reached();
493     }
494 }
495 
496 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */
497 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t)
498 {
499     if (!ctx->cfg_ptr->ext_zfinx) {
500         tcg_gen_mov_i64(cpu_fpr[reg_num], t);
501         return;
502     }
503     if (reg_num != 0) {
504         switch (get_xl(ctx)) {
505         case MXL_RV32:
506 #ifdef TARGET_RISCV32
507             tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t);
508             break;
509 #else
510         /* fall through */
511         case MXL_RV64:
512             tcg_gen_mov_i64(cpu_gpr[reg_num], t);
513             break;
514 #endif
515         default:
516             g_assert_not_reached();
517         }
518     }
519 }
520 
521 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t)
522 {
523     if (!ctx->cfg_ptr->ext_zfinx) {
524         tcg_gen_mov_i64(cpu_fpr[reg_num], t);
525         return;
526     }
527 
528     if (reg_num != 0) {
529         switch (get_xl(ctx)) {
530         case MXL_RV32:
531 #ifdef TARGET_RISCV32
532             tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t);
533             break;
534 #else
535             tcg_gen_ext32s_i64(cpu_gpr[reg_num], t);
536             tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32);
537             break;
538         case MXL_RV64:
539             tcg_gen_mov_i64(cpu_gpr[reg_num], t);
540             break;
541 #endif
542         default:
543             g_assert_not_reached();
544         }
545     }
546 }
547 
548 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
549 {
550     target_ulong next_pc;
551 
552     /* check misaligned: */
553     next_pc = ctx->base.pc_next + imm;
554     if (!ctx->cfg_ptr->ext_zca) {
555         if ((next_pc & 0x3) != 0) {
556             gen_exception_inst_addr_mis(ctx);
557             return;
558         }
559     }
560 
561     gen_set_gpri(ctx, rd, ctx->pc_succ_insn);
562     gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */
563     ctx->base.is_jmp = DISAS_NORETURN;
564 }
565 
566 /* Compute a canonical address from a register plus offset. */
567 static TCGv get_address(DisasContext *ctx, int rs1, int imm)
568 {
569     TCGv addr = tcg_temp_new();
570     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
571 
572     tcg_gen_addi_tl(addr, src1, imm);
573     if (ctx->pm_mask_enabled) {
574         tcg_gen_andc_tl(addr, addr, pm_mask);
575     } else if (get_xl(ctx) == MXL_RV32) {
576         tcg_gen_ext32u_tl(addr, addr);
577     }
578     if (ctx->pm_base_enabled) {
579         tcg_gen_or_tl(addr, addr, pm_base);
580     }
581     return addr;
582 }
583 
584 /* Compute a canonical address from a register plus reg offset. */
585 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs)
586 {
587     TCGv addr = tcg_temp_new();
588     TCGv src1 = get_gpr(ctx, rs1, EXT_NONE);
589 
590     tcg_gen_add_tl(addr, src1, offs);
591     if (ctx->pm_mask_enabled) {
592         tcg_gen_andc_tl(addr, addr, pm_mask);
593     } else if (get_xl(ctx) == MXL_RV32) {
594         tcg_gen_ext32u_tl(addr, addr);
595     }
596     if (ctx->pm_base_enabled) {
597         tcg_gen_or_tl(addr, addr, pm_base);
598     }
599     return addr;
600 }
601 
602 #ifndef CONFIG_USER_ONLY
603 /*
604  * The states of mstatus_fs are:
605  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
606  * We will have already diagnosed disabled state,
607  * and need to turn initial/clean into dirty.
608  */
609 static void mark_fs_dirty(DisasContext *ctx)
610 {
611     TCGv tmp;
612 
613     if (!has_ext(ctx, RVF)) {
614         return;
615     }
616 
617     if (ctx->mstatus_fs != MSTATUS_FS) {
618         /* Remember the state change for the rest of the TB. */
619         ctx->mstatus_fs = MSTATUS_FS;
620 
621         tmp = tcg_temp_new();
622         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
623         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
624         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
625     }
626 
627     if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) {
628         /* Remember the stage change for the rest of the TB. */
629         ctx->mstatus_hs_fs = MSTATUS_FS;
630 
631         tmp = tcg_temp_new();
632         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
633         tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
634         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
635     }
636 }
637 #else
638 static inline void mark_fs_dirty(DisasContext *ctx) { }
639 #endif
640 
641 #ifndef CONFIG_USER_ONLY
642 /*
643  * The states of mstatus_vs are:
644  * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
645  * We will have already diagnosed disabled state,
646  * and need to turn initial/clean into dirty.
647  */
648 static void mark_vs_dirty(DisasContext *ctx)
649 {
650     TCGv tmp;
651 
652     if (ctx->mstatus_vs != MSTATUS_VS) {
653         /* Remember the state change for the rest of the TB.  */
654         ctx->mstatus_vs = MSTATUS_VS;
655 
656         tmp = tcg_temp_new();
657         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
658         tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
659         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
660     }
661 
662     if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) {
663         /* Remember the stage change for the rest of the TB. */
664         ctx->mstatus_hs_vs = MSTATUS_VS;
665 
666         tmp = tcg_temp_new();
667         tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
668         tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS);
669         tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
670     }
671 }
672 #else
673 static inline void mark_vs_dirty(DisasContext *ctx) { }
674 #endif
675 
676 static void gen_set_rm(DisasContext *ctx, int rm)
677 {
678     if (ctx->frm == rm) {
679         return;
680     }
681     ctx->frm = rm;
682 
683     if (rm == RISCV_FRM_DYN) {
684         /* The helper will return only if frm valid. */
685         ctx->frm_valid = true;
686     }
687 
688     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
689     decode_save_opc(ctx);
690     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
691 }
692 
693 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
694 {
695     if (ctx->frm == rm && ctx->frm_valid) {
696         return;
697     }
698     ctx->frm = rm;
699     ctx->frm_valid = true;
700 
701     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
702     decode_save_opc(ctx);
703     gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
704 }
705 
706 static int ex_plus_1(DisasContext *ctx, int nf)
707 {
708     return nf + 1;
709 }
710 
711 #define EX_SH(amount) \
712     static int ex_shift_##amount(DisasContext *ctx, int imm) \
713     {                                         \
714         return imm << amount;                 \
715     }
716 EX_SH(1)
717 EX_SH(2)
718 EX_SH(3)
719 EX_SH(4)
720 EX_SH(12)
721 
722 #define REQUIRE_EXT(ctx, ext) do { \
723     if (!has_ext(ctx, ext)) {      \
724         return false;              \
725     }                              \
726 } while (0)
727 
728 #define REQUIRE_32BIT(ctx) do {    \
729     if (get_xl(ctx) != MXL_RV32) { \
730         return false;              \
731     }                              \
732 } while (0)
733 
734 #define REQUIRE_64BIT(ctx) do {     \
735     if (get_xl(ctx) != MXL_RV64) {  \
736         return false;               \
737     }                               \
738 } while (0)
739 
740 #define REQUIRE_128BIT(ctx) do {    \
741     if (get_xl(ctx) != MXL_RV128) { \
742         return false;               \
743     }                               \
744 } while (0)
745 
746 #define REQUIRE_64_OR_128BIT(ctx) do { \
747     if (get_xl(ctx) == MXL_RV32) {     \
748         return false;                  \
749     }                                  \
750 } while (0)
751 
752 #define REQUIRE_EITHER_EXT(ctx, A, B) do {       \
753     if (!ctx->cfg_ptr->ext_##A &&                \
754         !ctx->cfg_ptr->ext_##B) {                \
755         return false;                            \
756     }                                            \
757 } while (0)
758 
759 static int ex_rvc_register(DisasContext *ctx, int reg)
760 {
761     return 8 + reg;
762 }
763 
764 static int ex_sreg_register(DisasContext *ctx, int reg)
765 {
766     return reg < 2 ? reg + 8 : reg + 16;
767 }
768 
769 static int ex_rvc_shiftli(DisasContext *ctx, int imm)
770 {
771     /* For RV128 a shamt of 0 means a shift by 64. */
772     if (get_ol(ctx) == MXL_RV128) {
773         imm = imm ? imm : 64;
774     }
775     return imm;
776 }
777 
778 static int ex_rvc_shiftri(DisasContext *ctx, int imm)
779 {
780     /*
781      * For RV128 a shamt of 0 means a shift by 64, furthermore, for right
782      * shifts, the shamt is sign-extended.
783      */
784     if (get_ol(ctx) == MXL_RV128) {
785         imm = imm | (imm & 32) << 1;
786         imm = imm ? imm : 64;
787     }
788     return imm;
789 }
790 
791 /* Include the auto-generated decoder for 32 bit insn */
792 #include "decode-insn32.c.inc"
793 
794 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
795                              void (*func)(TCGv, TCGv, target_long))
796 {
797     TCGv dest = dest_gpr(ctx, a->rd);
798     TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
799 
800     func(dest, src1, a->imm);
801 
802     if (get_xl(ctx) == MXL_RV128) {
803         TCGv src1h = get_gprh(ctx, a->rs1);
804         TCGv desth = dest_gprh(ctx, a->rd);
805 
806         func(desth, src1h, -(a->imm < 0));
807         gen_set_gpr128(ctx, a->rd, dest, desth);
808     } else {
809         gen_set_gpr(ctx, a->rd, dest);
810     }
811 
812     return true;
813 }
814 
815 static bool gen_logic(DisasContext *ctx, arg_r *a,
816                       void (*func)(TCGv, TCGv, TCGv))
817 {
818     TCGv dest = dest_gpr(ctx, a->rd);
819     TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
820     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
821 
822     func(dest, src1, src2);
823 
824     if (get_xl(ctx) == MXL_RV128) {
825         TCGv src1h = get_gprh(ctx, a->rs1);
826         TCGv src2h = get_gprh(ctx, a->rs2);
827         TCGv desth = dest_gprh(ctx, a->rd);
828 
829         func(desth, src1h, src2h);
830         gen_set_gpr128(ctx, a->rd, dest, desth);
831     } else {
832         gen_set_gpr(ctx, a->rd, dest);
833     }
834 
835     return true;
836 }
837 
838 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext,
839                              void (*func)(TCGv, TCGv, target_long),
840                              void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
841 {
842     TCGv dest = dest_gpr(ctx, a->rd);
843     TCGv src1 = get_gpr(ctx, a->rs1, ext);
844 
845     if (get_ol(ctx) < MXL_RV128) {
846         func(dest, src1, a->imm);
847         gen_set_gpr(ctx, a->rd, dest);
848     } else {
849         if (f128 == NULL) {
850             return false;
851         }
852 
853         TCGv src1h = get_gprh(ctx, a->rs1);
854         TCGv desth = dest_gprh(ctx, a->rd);
855 
856         f128(dest, desth, src1, src1h, a->imm);
857         gen_set_gpr128(ctx, a->rd, dest, desth);
858     }
859     return true;
860 }
861 
862 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext,
863                              void (*func)(TCGv, TCGv, TCGv),
864                              void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
865 {
866     TCGv dest = dest_gpr(ctx, a->rd);
867     TCGv src1 = get_gpr(ctx, a->rs1, ext);
868     TCGv src2 = tcg_constant_tl(a->imm);
869 
870     if (get_ol(ctx) < MXL_RV128) {
871         func(dest, src1, src2);
872         gen_set_gpr(ctx, a->rd, dest);
873     } else {
874         if (f128 == NULL) {
875             return false;
876         }
877 
878         TCGv src1h = get_gprh(ctx, a->rs1);
879         TCGv src2h = tcg_constant_tl(-(a->imm < 0));
880         TCGv desth = dest_gprh(ctx, a->rd);
881 
882         f128(dest, desth, src1, src1h, src2, src2h);
883         gen_set_gpr128(ctx, a->rd, dest, desth);
884     }
885     return true;
886 }
887 
888 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext,
889                       void (*func)(TCGv, TCGv, TCGv),
890                       void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
891 {
892     TCGv dest = dest_gpr(ctx, a->rd);
893     TCGv src1 = get_gpr(ctx, a->rs1, ext);
894     TCGv src2 = get_gpr(ctx, a->rs2, ext);
895 
896     if (get_ol(ctx) < MXL_RV128) {
897         func(dest, src1, src2);
898         gen_set_gpr(ctx, a->rd, dest);
899     } else {
900         if (f128 == NULL) {
901             return false;
902         }
903 
904         TCGv src1h = get_gprh(ctx, a->rs1);
905         TCGv src2h = get_gprh(ctx, a->rs2);
906         TCGv desth = dest_gprh(ctx, a->rd);
907 
908         f128(dest, desth, src1, src1h, src2, src2h);
909         gen_set_gpr128(ctx, a->rd, dest, desth);
910     }
911     return true;
912 }
913 
914 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
915                              void (*f_tl)(TCGv, TCGv, TCGv),
916                              void (*f_32)(TCGv, TCGv, TCGv),
917                              void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv))
918 {
919     int olen = get_olen(ctx);
920 
921     if (olen != TARGET_LONG_BITS) {
922         if (olen == 32) {
923             f_tl = f_32;
924         } else if (olen != 128) {
925             g_assert_not_reached();
926         }
927     }
928     return gen_arith(ctx, a, ext, f_tl, f_128);
929 }
930 
931 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext,
932                              void (*func)(TCGv, TCGv, target_long),
933                              void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long))
934 {
935     TCGv dest, src1;
936     int max_len = get_olen(ctx);
937 
938     if (a->shamt >= max_len) {
939         return false;
940     }
941 
942     dest = dest_gpr(ctx, a->rd);
943     src1 = get_gpr(ctx, a->rs1, ext);
944 
945     if (max_len < 128) {
946         func(dest, src1, a->shamt);
947         gen_set_gpr(ctx, a->rd, dest);
948     } else {
949         TCGv src1h = get_gprh(ctx, a->rs1);
950         TCGv desth = dest_gprh(ctx, a->rd);
951 
952         if (f128 == NULL) {
953             return false;
954         }
955         f128(dest, desth, src1, src1h, a->shamt);
956         gen_set_gpr128(ctx, a->rd, dest, desth);
957     }
958     return true;
959 }
960 
961 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a,
962                                     DisasExtend ext,
963                                     void (*f_tl)(TCGv, TCGv, target_long),
964                                     void (*f_32)(TCGv, TCGv, target_long),
965                                     void (*f_128)(TCGv, TCGv, TCGv, TCGv,
966                                                   target_long))
967 {
968     int olen = get_olen(ctx);
969     if (olen != TARGET_LONG_BITS) {
970         if (olen == 32) {
971             f_tl = f_32;
972         } else if (olen != 128) {
973             g_assert_not_reached();
974         }
975     }
976     return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128);
977 }
978 
979 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext,
980                              void (*func)(TCGv, TCGv, TCGv))
981 {
982     TCGv dest, src1, src2;
983     int max_len = get_olen(ctx);
984 
985     if (a->shamt >= max_len) {
986         return false;
987     }
988 
989     dest = dest_gpr(ctx, a->rd);
990     src1 = get_gpr(ctx, a->rs1, ext);
991     src2 = tcg_constant_tl(a->shamt);
992 
993     func(dest, src1, src2);
994 
995     gen_set_gpr(ctx, a->rd, dest);
996     return true;
997 }
998 
999 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext,
1000                       void (*func)(TCGv, TCGv, TCGv),
1001                       void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv))
1002 {
1003     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
1004     TCGv ext2 = tcg_temp_new();
1005     int max_len = get_olen(ctx);
1006 
1007     tcg_gen_andi_tl(ext2, src2, max_len - 1);
1008 
1009     TCGv dest = dest_gpr(ctx, a->rd);
1010     TCGv src1 = get_gpr(ctx, a->rs1, ext);
1011 
1012     if (max_len < 128) {
1013         func(dest, src1, ext2);
1014         gen_set_gpr(ctx, a->rd, dest);
1015     } else {
1016         TCGv src1h = get_gprh(ctx, a->rs1);
1017         TCGv desth = dest_gprh(ctx, a->rd);
1018 
1019         if (f128 == NULL) {
1020             return false;
1021         }
1022         f128(dest, desth, src1, src1h, ext2);
1023         gen_set_gpr128(ctx, a->rd, dest, desth);
1024     }
1025     return true;
1026 }
1027 
1028 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext,
1029                              void (*f_tl)(TCGv, TCGv, TCGv),
1030                              void (*f_32)(TCGv, TCGv, TCGv),
1031                              void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv))
1032 {
1033     int olen = get_olen(ctx);
1034     if (olen != TARGET_LONG_BITS) {
1035         if (olen == 32) {
1036             f_tl = f_32;
1037         } else if (olen != 128) {
1038             g_assert_not_reached();
1039         }
1040     }
1041     return gen_shift(ctx, a, ext, f_tl, f_128);
1042 }
1043 
1044 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
1045                       void (*func)(TCGv, TCGv))
1046 {
1047     TCGv dest = dest_gpr(ctx, a->rd);
1048     TCGv src1 = get_gpr(ctx, a->rs1, ext);
1049 
1050     func(dest, src1);
1051 
1052     gen_set_gpr(ctx, a->rd, dest);
1053     return true;
1054 }
1055 
1056 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
1057                              void (*f_tl)(TCGv, TCGv),
1058                              void (*f_32)(TCGv, TCGv))
1059 {
1060     int olen = get_olen(ctx);
1061 
1062     if (olen != TARGET_LONG_BITS) {
1063         if (olen == 32) {
1064             f_tl = f_32;
1065         } else {
1066             g_assert_not_reached();
1067         }
1068     }
1069     return gen_unary(ctx, a, ext, f_tl);
1070 }
1071 
1072 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
1073 {
1074     DisasContext *ctx = container_of(dcbase, DisasContext, base);
1075     CPUState *cpu = ctx->cs;
1076     CPURISCVState *env = cpu->env_ptr;
1077 
1078     return cpu_ldl_code(env, pc);
1079 }
1080 
1081 /* Include insn module translation function */
1082 #include "insn_trans/trans_rvi.c.inc"
1083 #include "insn_trans/trans_rvm.c.inc"
1084 #include "insn_trans/trans_rva.c.inc"
1085 #include "insn_trans/trans_rvf.c.inc"
1086 #include "insn_trans/trans_rvd.c.inc"
1087 #include "insn_trans/trans_rvh.c.inc"
1088 #include "insn_trans/trans_rvv.c.inc"
1089 #include "insn_trans/trans_rvb.c.inc"
1090 #include "insn_trans/trans_rvzicond.c.inc"
1091 #include "insn_trans/trans_rvzawrs.c.inc"
1092 #include "insn_trans/trans_rvzicbo.c.inc"
1093 #include "insn_trans/trans_rvzfh.c.inc"
1094 #include "insn_trans/trans_rvk.c.inc"
1095 #include "insn_trans/trans_privileged.c.inc"
1096 #include "insn_trans/trans_svinval.c.inc"
1097 #include "decode-xthead.c.inc"
1098 #include "insn_trans/trans_xthead.c.inc"
1099 #include "insn_trans/trans_xventanacondops.c.inc"
1100 
1101 /* Include the auto-generated decoder for 16 bit insn */
1102 #include "decode-insn16.c.inc"
1103 #include "insn_trans/trans_rvzce.c.inc"
1104 
1105 /* Include decoders for factored-out extensions */
1106 #include "decode-XVentanaCondOps.c.inc"
1107 
1108 /* The specification allows for longer insns, but not supported by qemu. */
1109 #define MAX_INSN_LEN  4
1110 
1111 static inline int insn_len(uint16_t first_word)
1112 {
1113     return (first_word & 3) == 3 ? 4 : 2;
1114 }
1115 
1116 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
1117 {
1118     /*
1119      * A table with predicate (i.e., guard) functions and decoder functions
1120      * that are tested in-order until a decoder matches onto the opcode.
1121      */
1122     static const struct {
1123         bool (*guard_func)(DisasContext *);
1124         bool (*decode_func)(DisasContext *, uint32_t);
1125     } decoders[] = {
1126         { always_true_p,  decode_insn32 },
1127         { has_xthead_p, decode_xthead },
1128         { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
1129     };
1130 
1131     ctx->virt_inst_excp = false;
1132     /* Check for compressed insn */
1133     if (insn_len(opcode) == 2) {
1134         ctx->opcode = opcode;
1135         ctx->pc_succ_insn = ctx->base.pc_next + 2;
1136         /*
1137          * The Zca extension is added as way to refer to instructions in the C
1138          * extension that do not include the floating-point loads and stores
1139          */
1140         if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) {
1141             return;
1142         }
1143     } else {
1144         uint32_t opcode32 = opcode;
1145         opcode32 = deposit32(opcode32, 16, 16,
1146                              translator_lduw(env, &ctx->base,
1147                                              ctx->base.pc_next + 2));
1148         ctx->opcode = opcode32;
1149         ctx->pc_succ_insn = ctx->base.pc_next + 4;
1150 
1151         for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) {
1152             if (decoders[i].guard_func(ctx) &&
1153                 decoders[i].decode_func(ctx, opcode32)) {
1154                 return;
1155             }
1156         }
1157     }
1158 
1159     gen_exception_illegal(ctx);
1160 }
1161 
1162 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
1163 {
1164     DisasContext *ctx = container_of(dcbase, DisasContext, base);
1165     CPURISCVState *env = cs->env_ptr;
1166     RISCVCPU *cpu = RISCV_CPU(cs);
1167     uint32_t tb_flags = ctx->base.tb->flags;
1168 
1169     ctx->pc_succ_insn = ctx->base.pc_first;
1170     ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX);
1171     ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS;
1172     ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS;
1173     ctx->priv_ver = env->priv_ver;
1174     ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED);
1175     ctx->misa_ext = env->misa_ext;
1176     ctx->frm = -1;  /* unknown rounding mode */
1177     ctx->cfg_ptr = &(cpu->cfg);
1178     ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS);
1179     ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS);
1180     ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX);
1181     ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL);
1182     ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW);
1183     ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3);
1184     ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s;
1185     ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s;
1186     ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s;
1187     ctx->vstart = env->vstart;
1188     ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX);
1189     ctx->misa_mxl_max = env->misa_mxl_max;
1190     ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL);
1191     ctx->cs = cs;
1192     ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED);
1193     ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED);
1194     ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER);
1195     ctx->zero = tcg_constant_tl(0);
1196     ctx->virt_inst_excp = false;
1197 }
1198 
1199 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu)
1200 {
1201 }
1202 
1203 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
1204 {
1205     DisasContext *ctx = container_of(dcbase, DisasContext, base);
1206 
1207     tcg_gen_insn_start(ctx->base.pc_next, 0);
1208     ctx->insn_start = tcg_last_op();
1209 }
1210 
1211 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
1212 {
1213     DisasContext *ctx = container_of(dcbase, DisasContext, base);
1214     CPURISCVState *env = cpu->env_ptr;
1215     uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next);
1216 
1217     ctx->ol = ctx->xl;
1218     decode_opc(env, ctx, opcode16);
1219     ctx->base.pc_next = ctx->pc_succ_insn;
1220 
1221     /* Only the first insn within a TB is allowed to cross a page boundary. */
1222     if (ctx->base.is_jmp == DISAS_NEXT) {
1223         if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) {
1224             ctx->base.is_jmp = DISAS_TOO_MANY;
1225         } else {
1226             unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
1227 
1228             if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
1229                 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next);
1230                 int len = insn_len(next_insn);
1231 
1232                 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {
1233                     ctx->base.is_jmp = DISAS_TOO_MANY;
1234                 }
1235             }
1236         }
1237     }
1238 }
1239 
1240 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
1241 {
1242     DisasContext *ctx = container_of(dcbase, DisasContext, base);
1243 
1244     switch (ctx->base.is_jmp) {
1245     case DISAS_TOO_MANY:
1246         gen_goto_tb(ctx, 0, ctx->base.pc_next);
1247         break;
1248     case DISAS_NORETURN:
1249         break;
1250     default:
1251         g_assert_not_reached();
1252     }
1253 }
1254 
1255 static void riscv_tr_disas_log(const DisasContextBase *dcbase,
1256                                CPUState *cpu, FILE *logfile)
1257 {
1258 #ifndef CONFIG_USER_ONLY
1259     RISCVCPU *rvcpu = RISCV_CPU(cpu);
1260     CPURISCVState *env = &rvcpu->env;
1261 #endif
1262 
1263     fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first));
1264 #ifndef CONFIG_USER_ONLY
1265     fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n",
1266             env->priv, env->virt_enabled);
1267 #endif
1268     target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size);
1269 }
1270 
1271 static const TranslatorOps riscv_tr_ops = {
1272     .init_disas_context = riscv_tr_init_disas_context,
1273     .tb_start           = riscv_tr_tb_start,
1274     .insn_start         = riscv_tr_insn_start,
1275     .translate_insn     = riscv_tr_translate_insn,
1276     .tb_stop            = riscv_tr_tb_stop,
1277     .disas_log          = riscv_tr_disas_log,
1278 };
1279 
1280 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns,
1281                            target_ulong pc, void *host_pc)
1282 {
1283     DisasContext ctx;
1284 
1285     translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base);
1286 }
1287 
1288 void riscv_translate_init(void)
1289 {
1290     int i;
1291 
1292     /*
1293      * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
1294      * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
1295      * unless you specifically block reads/writes to reg 0.
1296      */
1297     cpu_gpr[0] = NULL;
1298     cpu_gprh[0] = NULL;
1299 
1300     for (i = 1; i < 32; i++) {
1301         cpu_gpr[i] = tcg_global_mem_new(cpu_env,
1302             offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
1303         cpu_gprh[i] = tcg_global_mem_new(cpu_env,
1304             offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
1305     }
1306 
1307     for (i = 0; i < 32; i++) {
1308         cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env,
1309             offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]);
1310     }
1311 
1312     cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc");
1313     cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl");
1314     cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart),
1315                             "vstart");
1316     load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res),
1317                              "load_res");
1318     load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val),
1319                              "load_val");
1320     /* Assign PM CSRs to tcg globals */
1321     pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask),
1322                                  "pmmask");
1323     pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase),
1324                                  "pmbase");
1325 }
1326