1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 RISCVExtStatus mstatus_fs; 68 RISCVExtStatus mstatus_vs; 69 RISCVExtStatus mstatus_hs_fs; 70 RISCVExtStatus mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* 73 * Remember the rounding mode encoded in the previous fp instruction, 74 * which we have already installed into env->fp_status. Or -1 for 75 * no previous fp instruction. Note that we exit the TB when writing 76 * to any system register, which includes CSR_FRM, so we do not have 77 * to reset this known value. 78 */ 79 int frm; 80 RISCVMXL ol; 81 bool virt_inst_excp; 82 bool virt_enabled; 83 const RISCVCPUConfig *cfg_ptr; 84 bool hlsx; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint8_t vta; 102 uint8_t vma; 103 bool cfg_vta_all_1s; 104 target_ulong vstart; 105 bool vl_eq_vlmax; 106 CPUState *cs; 107 TCGv zero; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* Use icount trigger for native debug */ 112 bool itrigger; 113 /* FRM is known to contain a valid value. */ 114 bool frm_valid; 115 /* TCG of the current insn_start */ 116 TCGOp *insn_start; 117 } DisasContext; 118 119 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 120 { 121 return ctx->misa_ext & ext; 122 } 123 124 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 125 { 126 return true; 127 } 128 129 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 130 { 131 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 132 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 133 ctx->cfg_ptr->ext_xtheadcondmov || 134 ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || 135 ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || 136 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 137 } 138 139 #define MATERIALISE_EXT_PREDICATE(ext) \ 140 static bool has_ ## ext ## _p(DisasContext *ctx) \ 141 { \ 142 return ctx->cfg_ptr->ext_ ## ext ; \ 143 } 144 145 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 146 147 #ifdef TARGET_RISCV32 148 #define get_xl(ctx) MXL_RV32 149 #elif defined(CONFIG_USER_ONLY) 150 #define get_xl(ctx) MXL_RV64 151 #else 152 #define get_xl(ctx) ((ctx)->xl) 153 #endif 154 155 /* The word size for this machine mode. */ 156 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 157 { 158 return 16 << get_xl(ctx); 159 } 160 161 /* The operation length, as opposed to the xlen. */ 162 #ifdef TARGET_RISCV32 163 #define get_ol(ctx) MXL_RV32 164 #else 165 #define get_ol(ctx) ((ctx)->ol) 166 #endif 167 168 static inline int get_olen(DisasContext *ctx) 169 { 170 return 16 << get_ol(ctx); 171 } 172 173 /* The maximum register length */ 174 #ifdef TARGET_RISCV32 175 #define get_xl_max(ctx) MXL_RV32 176 #else 177 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 178 #endif 179 180 /* 181 * RISC-V requires NaN-boxing of narrower width floating point values. 182 * This applies when a 32-bit value is assigned to a 64-bit FP register. 183 * For consistency and simplicity, we nanbox results even when the RVD 184 * extension is not present. 185 */ 186 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 189 } 190 191 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 194 } 195 196 /* 197 * A narrow n-bit operation, where n < FLEN, checks that input operands 198 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 199 * If so, the least-significant bits of the input are used, otherwise the 200 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 201 * 202 * Here, the result is always nan-boxed, even the canonical nan. 203 */ 204 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 205 { 206 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 207 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 208 209 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 210 } 211 212 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 213 { 214 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 215 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 216 217 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 218 } 219 220 static void decode_save_opc(DisasContext *ctx) 221 { 222 assert(ctx->insn_start != NULL); 223 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 224 ctx->insn_start = NULL; 225 } 226 227 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 228 { 229 if (get_xl(ctx) == MXL_RV32) { 230 dest = (int32_t)dest; 231 } 232 tcg_gen_movi_tl(cpu_pc, dest); 233 } 234 235 static void gen_set_pc(DisasContext *ctx, TCGv dest) 236 { 237 if (get_xl(ctx) == MXL_RV32) { 238 tcg_gen_ext32s_tl(cpu_pc, dest); 239 } else { 240 tcg_gen_mov_tl(cpu_pc, dest); 241 } 242 } 243 244 static void generate_exception(DisasContext *ctx, int excp) 245 { 246 gen_set_pc_imm(ctx, ctx->base.pc_next); 247 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 248 ctx->base.is_jmp = DISAS_NORETURN; 249 } 250 251 static void gen_exception_illegal(DisasContext *ctx) 252 { 253 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 254 offsetof(CPURISCVState, bins)); 255 if (ctx->virt_inst_excp) { 256 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 257 } else { 258 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 259 } 260 } 261 262 static void gen_exception_inst_addr_mis(DisasContext *ctx) 263 { 264 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 265 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 266 } 267 268 static void lookup_and_goto_ptr(DisasContext *ctx) 269 { 270 #ifndef CONFIG_USER_ONLY 271 if (ctx->itrigger) { 272 gen_helper_itrigger_match(cpu_env); 273 } 274 #endif 275 tcg_gen_lookup_and_goto_ptr(); 276 } 277 278 static void exit_tb(DisasContext *ctx) 279 { 280 #ifndef CONFIG_USER_ONLY 281 if (ctx->itrigger) { 282 gen_helper_itrigger_match(cpu_env); 283 } 284 #endif 285 tcg_gen_exit_tb(NULL, 0); 286 } 287 288 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 289 { 290 /* 291 * Under itrigger, instruction executes one by one like singlestep, 292 * direct block chain benefits will be small. 293 */ 294 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 295 tcg_gen_goto_tb(n); 296 gen_set_pc_imm(ctx, dest); 297 tcg_gen_exit_tb(ctx->base.tb, n); 298 } else { 299 gen_set_pc_imm(ctx, dest); 300 lookup_and_goto_ptr(ctx); 301 } 302 } 303 304 /* 305 * Wrappers for getting reg values. 306 * 307 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 308 * constant zero as a source, and an uninitialized sink as destination. 309 * 310 * Further, we may provide an extension for word operations. 311 */ 312 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 313 { 314 TCGv t; 315 316 if (reg_num == 0) { 317 return ctx->zero; 318 } 319 320 switch (get_ol(ctx)) { 321 case MXL_RV32: 322 switch (ext) { 323 case EXT_NONE: 324 break; 325 case EXT_SIGN: 326 t = tcg_temp_new(); 327 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 328 return t; 329 case EXT_ZERO: 330 t = tcg_temp_new(); 331 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 332 return t; 333 default: 334 g_assert_not_reached(); 335 } 336 break; 337 case MXL_RV64: 338 case MXL_RV128: 339 break; 340 default: 341 g_assert_not_reached(); 342 } 343 return cpu_gpr[reg_num]; 344 } 345 346 static TCGv get_gprh(DisasContext *ctx, int reg_num) 347 { 348 assert(get_xl(ctx) == MXL_RV128); 349 if (reg_num == 0) { 350 return ctx->zero; 351 } 352 return cpu_gprh[reg_num]; 353 } 354 355 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 356 { 357 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 358 return tcg_temp_new(); 359 } 360 return cpu_gpr[reg_num]; 361 } 362 363 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 364 { 365 if (reg_num == 0) { 366 return tcg_temp_new(); 367 } 368 return cpu_gprh[reg_num]; 369 } 370 371 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 372 { 373 if (reg_num != 0) { 374 switch (get_ol(ctx)) { 375 case MXL_RV32: 376 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 377 break; 378 case MXL_RV64: 379 case MXL_RV128: 380 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 381 break; 382 default: 383 g_assert_not_reached(); 384 } 385 386 if (get_xl_max(ctx) == MXL_RV128) { 387 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 388 } 389 } 390 } 391 392 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 393 { 394 if (reg_num != 0) { 395 switch (get_ol(ctx)) { 396 case MXL_RV32: 397 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 398 break; 399 case MXL_RV64: 400 case MXL_RV128: 401 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 402 break; 403 default: 404 g_assert_not_reached(); 405 } 406 407 if (get_xl_max(ctx) == MXL_RV128) { 408 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 409 } 410 } 411 } 412 413 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 414 { 415 assert(get_ol(ctx) == MXL_RV128); 416 if (reg_num != 0) { 417 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 418 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 419 } 420 } 421 422 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 423 { 424 if (!ctx->cfg_ptr->ext_zfinx) { 425 return cpu_fpr[reg_num]; 426 } 427 428 if (reg_num == 0) { 429 return tcg_constant_i64(0); 430 } 431 switch (get_xl(ctx)) { 432 case MXL_RV32: 433 #ifdef TARGET_RISCV32 434 { 435 TCGv_i64 t = tcg_temp_new_i64(); 436 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 437 return t; 438 } 439 #else 440 /* fall through */ 441 case MXL_RV64: 442 return cpu_gpr[reg_num]; 443 #endif 444 default: 445 g_assert_not_reached(); 446 } 447 } 448 449 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 450 { 451 if (!ctx->cfg_ptr->ext_zfinx) { 452 return cpu_fpr[reg_num]; 453 } 454 455 if (reg_num == 0) { 456 return tcg_constant_i64(0); 457 } 458 switch (get_xl(ctx)) { 459 case MXL_RV32: 460 { 461 TCGv_i64 t = tcg_temp_new_i64(); 462 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 463 return t; 464 } 465 #ifdef TARGET_RISCV64 466 case MXL_RV64: 467 return cpu_gpr[reg_num]; 468 #endif 469 default: 470 g_assert_not_reached(); 471 } 472 } 473 474 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 475 { 476 if (!ctx->cfg_ptr->ext_zfinx) { 477 return cpu_fpr[reg_num]; 478 } 479 480 if (reg_num == 0) { 481 return tcg_temp_new_i64(); 482 } 483 484 switch (get_xl(ctx)) { 485 case MXL_RV32: 486 return tcg_temp_new_i64(); 487 #ifdef TARGET_RISCV64 488 case MXL_RV64: 489 return cpu_gpr[reg_num]; 490 #endif 491 default: 492 g_assert_not_reached(); 493 } 494 } 495 496 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 497 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 498 { 499 if (!ctx->cfg_ptr->ext_zfinx) { 500 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 501 return; 502 } 503 if (reg_num != 0) { 504 switch (get_xl(ctx)) { 505 case MXL_RV32: 506 #ifdef TARGET_RISCV32 507 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 508 break; 509 #else 510 /* fall through */ 511 case MXL_RV64: 512 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 513 break; 514 #endif 515 default: 516 g_assert_not_reached(); 517 } 518 } 519 } 520 521 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 522 { 523 if (!ctx->cfg_ptr->ext_zfinx) { 524 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 525 return; 526 } 527 528 if (reg_num != 0) { 529 switch (get_xl(ctx)) { 530 case MXL_RV32: 531 #ifdef TARGET_RISCV32 532 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 533 break; 534 #else 535 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 536 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 537 break; 538 case MXL_RV64: 539 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 540 break; 541 #endif 542 default: 543 g_assert_not_reached(); 544 } 545 } 546 } 547 548 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 549 { 550 target_ulong next_pc; 551 552 /* check misaligned: */ 553 next_pc = ctx->base.pc_next + imm; 554 if (!ctx->cfg_ptr->ext_zca) { 555 if ((next_pc & 0x3) != 0) { 556 gen_exception_inst_addr_mis(ctx); 557 return; 558 } 559 } 560 561 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 562 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 563 ctx->base.is_jmp = DISAS_NORETURN; 564 } 565 566 /* Compute a canonical address from a register plus offset. */ 567 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 568 { 569 TCGv addr = tcg_temp_new(); 570 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 571 572 tcg_gen_addi_tl(addr, src1, imm); 573 if (ctx->pm_mask_enabled) { 574 tcg_gen_andc_tl(addr, addr, pm_mask); 575 } else if (get_xl(ctx) == MXL_RV32) { 576 tcg_gen_ext32u_tl(addr, addr); 577 } 578 if (ctx->pm_base_enabled) { 579 tcg_gen_or_tl(addr, addr, pm_base); 580 } 581 return addr; 582 } 583 584 /* Compute a canonical address from a register plus reg offset. */ 585 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 586 { 587 TCGv addr = tcg_temp_new(); 588 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 589 590 tcg_gen_add_tl(addr, src1, offs); 591 if (ctx->pm_mask_enabled) { 592 tcg_gen_andc_tl(addr, addr, pm_mask); 593 } else if (get_xl(ctx) == MXL_RV32) { 594 tcg_gen_ext32u_tl(addr, addr); 595 } 596 if (ctx->pm_base_enabled) { 597 tcg_gen_or_tl(addr, addr, pm_base); 598 } 599 return addr; 600 } 601 602 #ifndef CONFIG_USER_ONLY 603 /* 604 * We will have already diagnosed disabled state, 605 * and need to turn initial/clean into dirty. 606 */ 607 static void mark_fs_dirty(DisasContext *ctx) 608 { 609 TCGv tmp; 610 611 if (!has_ext(ctx, RVF)) { 612 return; 613 } 614 615 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 616 /* Remember the state change for the rest of the TB. */ 617 ctx->mstatus_fs = EXT_STATUS_DIRTY; 618 619 tmp = tcg_temp_new(); 620 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 621 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 622 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 623 } 624 625 if (ctx->virt_enabled && ctx->mstatus_hs_fs != EXT_STATUS_DIRTY) { 626 /* Remember the stage change for the rest of the TB. */ 627 ctx->mstatus_hs_fs = EXT_STATUS_DIRTY; 628 629 tmp = tcg_temp_new(); 630 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 631 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 632 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 633 } 634 } 635 #else 636 static inline void mark_fs_dirty(DisasContext *ctx) { } 637 #endif 638 639 #ifndef CONFIG_USER_ONLY 640 /* 641 * We will have already diagnosed disabled state, 642 * and need to turn initial/clean into dirty. 643 */ 644 static void mark_vs_dirty(DisasContext *ctx) 645 { 646 TCGv tmp; 647 648 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 649 /* Remember the state change for the rest of the TB. */ 650 ctx->mstatus_vs = EXT_STATUS_DIRTY; 651 652 tmp = tcg_temp_new(); 653 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 654 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 655 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 656 } 657 658 if (ctx->virt_enabled && ctx->mstatus_hs_vs != EXT_STATUS_DIRTY) { 659 /* Remember the stage change for the rest of the TB. */ 660 ctx->mstatus_hs_vs = EXT_STATUS_DIRTY; 661 662 tmp = tcg_temp_new(); 663 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 664 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 665 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 666 } 667 } 668 #else 669 static inline void mark_vs_dirty(DisasContext *ctx) { } 670 #endif 671 672 static void gen_set_rm(DisasContext *ctx, int rm) 673 { 674 if (ctx->frm == rm) { 675 return; 676 } 677 ctx->frm = rm; 678 679 if (rm == RISCV_FRM_DYN) { 680 /* The helper will return only if frm valid. */ 681 ctx->frm_valid = true; 682 } 683 684 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 685 decode_save_opc(ctx); 686 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 687 } 688 689 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 690 { 691 if (ctx->frm == rm && ctx->frm_valid) { 692 return; 693 } 694 ctx->frm = rm; 695 ctx->frm_valid = true; 696 697 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 698 decode_save_opc(ctx); 699 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 700 } 701 702 static int ex_plus_1(DisasContext *ctx, int nf) 703 { 704 return nf + 1; 705 } 706 707 #define EX_SH(amount) \ 708 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 709 { \ 710 return imm << amount; \ 711 } 712 EX_SH(1) 713 EX_SH(2) 714 EX_SH(3) 715 EX_SH(4) 716 EX_SH(12) 717 718 #define REQUIRE_EXT(ctx, ext) do { \ 719 if (!has_ext(ctx, ext)) { \ 720 return false; \ 721 } \ 722 } while (0) 723 724 #define REQUIRE_32BIT(ctx) do { \ 725 if (get_xl(ctx) != MXL_RV32) { \ 726 return false; \ 727 } \ 728 } while (0) 729 730 #define REQUIRE_64BIT(ctx) do { \ 731 if (get_xl(ctx) != MXL_RV64) { \ 732 return false; \ 733 } \ 734 } while (0) 735 736 #define REQUIRE_128BIT(ctx) do { \ 737 if (get_xl(ctx) != MXL_RV128) { \ 738 return false; \ 739 } \ 740 } while (0) 741 742 #define REQUIRE_64_OR_128BIT(ctx) do { \ 743 if (get_xl(ctx) == MXL_RV32) { \ 744 return false; \ 745 } \ 746 } while (0) 747 748 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 749 if (!ctx->cfg_ptr->ext_##A && \ 750 !ctx->cfg_ptr->ext_##B) { \ 751 return false; \ 752 } \ 753 } while (0) 754 755 static int ex_rvc_register(DisasContext *ctx, int reg) 756 { 757 return 8 + reg; 758 } 759 760 static int ex_sreg_register(DisasContext *ctx, int reg) 761 { 762 return reg < 2 ? reg + 8 : reg + 16; 763 } 764 765 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 766 { 767 /* For RV128 a shamt of 0 means a shift by 64. */ 768 if (get_ol(ctx) == MXL_RV128) { 769 imm = imm ? imm : 64; 770 } 771 return imm; 772 } 773 774 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 775 { 776 /* 777 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 778 * shifts, the shamt is sign-extended. 779 */ 780 if (get_ol(ctx) == MXL_RV128) { 781 imm = imm | (imm & 32) << 1; 782 imm = imm ? imm : 64; 783 } 784 return imm; 785 } 786 787 /* Include the auto-generated decoder for 32 bit insn */ 788 #include "decode-insn32.c.inc" 789 790 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 791 void (*func)(TCGv, TCGv, target_long)) 792 { 793 TCGv dest = dest_gpr(ctx, a->rd); 794 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 795 796 func(dest, src1, a->imm); 797 798 if (get_xl(ctx) == MXL_RV128) { 799 TCGv src1h = get_gprh(ctx, a->rs1); 800 TCGv desth = dest_gprh(ctx, a->rd); 801 802 func(desth, src1h, -(a->imm < 0)); 803 gen_set_gpr128(ctx, a->rd, dest, desth); 804 } else { 805 gen_set_gpr(ctx, a->rd, dest); 806 } 807 808 return true; 809 } 810 811 static bool gen_logic(DisasContext *ctx, arg_r *a, 812 void (*func)(TCGv, TCGv, TCGv)) 813 { 814 TCGv dest = dest_gpr(ctx, a->rd); 815 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 816 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 817 818 func(dest, src1, src2); 819 820 if (get_xl(ctx) == MXL_RV128) { 821 TCGv src1h = get_gprh(ctx, a->rs1); 822 TCGv src2h = get_gprh(ctx, a->rs2); 823 TCGv desth = dest_gprh(ctx, a->rd); 824 825 func(desth, src1h, src2h); 826 gen_set_gpr128(ctx, a->rd, dest, desth); 827 } else { 828 gen_set_gpr(ctx, a->rd, dest); 829 } 830 831 return true; 832 } 833 834 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 835 void (*func)(TCGv, TCGv, target_long), 836 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 837 { 838 TCGv dest = dest_gpr(ctx, a->rd); 839 TCGv src1 = get_gpr(ctx, a->rs1, ext); 840 841 if (get_ol(ctx) < MXL_RV128) { 842 func(dest, src1, a->imm); 843 gen_set_gpr(ctx, a->rd, dest); 844 } else { 845 if (f128 == NULL) { 846 return false; 847 } 848 849 TCGv src1h = get_gprh(ctx, a->rs1); 850 TCGv desth = dest_gprh(ctx, a->rd); 851 852 f128(dest, desth, src1, src1h, a->imm); 853 gen_set_gpr128(ctx, a->rd, dest, desth); 854 } 855 return true; 856 } 857 858 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 859 void (*func)(TCGv, TCGv, TCGv), 860 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 861 { 862 TCGv dest = dest_gpr(ctx, a->rd); 863 TCGv src1 = get_gpr(ctx, a->rs1, ext); 864 TCGv src2 = tcg_constant_tl(a->imm); 865 866 if (get_ol(ctx) < MXL_RV128) { 867 func(dest, src1, src2); 868 gen_set_gpr(ctx, a->rd, dest); 869 } else { 870 if (f128 == NULL) { 871 return false; 872 } 873 874 TCGv src1h = get_gprh(ctx, a->rs1); 875 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 876 TCGv desth = dest_gprh(ctx, a->rd); 877 878 f128(dest, desth, src1, src1h, src2, src2h); 879 gen_set_gpr128(ctx, a->rd, dest, desth); 880 } 881 return true; 882 } 883 884 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 885 void (*func)(TCGv, TCGv, TCGv), 886 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 887 { 888 TCGv dest = dest_gpr(ctx, a->rd); 889 TCGv src1 = get_gpr(ctx, a->rs1, ext); 890 TCGv src2 = get_gpr(ctx, a->rs2, ext); 891 892 if (get_ol(ctx) < MXL_RV128) { 893 func(dest, src1, src2); 894 gen_set_gpr(ctx, a->rd, dest); 895 } else { 896 if (f128 == NULL) { 897 return false; 898 } 899 900 TCGv src1h = get_gprh(ctx, a->rs1); 901 TCGv src2h = get_gprh(ctx, a->rs2); 902 TCGv desth = dest_gprh(ctx, a->rd); 903 904 f128(dest, desth, src1, src1h, src2, src2h); 905 gen_set_gpr128(ctx, a->rd, dest, desth); 906 } 907 return true; 908 } 909 910 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 911 void (*f_tl)(TCGv, TCGv, TCGv), 912 void (*f_32)(TCGv, TCGv, TCGv), 913 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 914 { 915 int olen = get_olen(ctx); 916 917 if (olen != TARGET_LONG_BITS) { 918 if (olen == 32) { 919 f_tl = f_32; 920 } else if (olen != 128) { 921 g_assert_not_reached(); 922 } 923 } 924 return gen_arith(ctx, a, ext, f_tl, f_128); 925 } 926 927 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 928 void (*func)(TCGv, TCGv, target_long), 929 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 930 { 931 TCGv dest, src1; 932 int max_len = get_olen(ctx); 933 934 if (a->shamt >= max_len) { 935 return false; 936 } 937 938 dest = dest_gpr(ctx, a->rd); 939 src1 = get_gpr(ctx, a->rs1, ext); 940 941 if (max_len < 128) { 942 func(dest, src1, a->shamt); 943 gen_set_gpr(ctx, a->rd, dest); 944 } else { 945 TCGv src1h = get_gprh(ctx, a->rs1); 946 TCGv desth = dest_gprh(ctx, a->rd); 947 948 if (f128 == NULL) { 949 return false; 950 } 951 f128(dest, desth, src1, src1h, a->shamt); 952 gen_set_gpr128(ctx, a->rd, dest, desth); 953 } 954 return true; 955 } 956 957 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 958 DisasExtend ext, 959 void (*f_tl)(TCGv, TCGv, target_long), 960 void (*f_32)(TCGv, TCGv, target_long), 961 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 962 target_long)) 963 { 964 int olen = get_olen(ctx); 965 if (olen != TARGET_LONG_BITS) { 966 if (olen == 32) { 967 f_tl = f_32; 968 } else if (olen != 128) { 969 g_assert_not_reached(); 970 } 971 } 972 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 973 } 974 975 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 976 void (*func)(TCGv, TCGv, TCGv)) 977 { 978 TCGv dest, src1, src2; 979 int max_len = get_olen(ctx); 980 981 if (a->shamt >= max_len) { 982 return false; 983 } 984 985 dest = dest_gpr(ctx, a->rd); 986 src1 = get_gpr(ctx, a->rs1, ext); 987 src2 = tcg_constant_tl(a->shamt); 988 989 func(dest, src1, src2); 990 991 gen_set_gpr(ctx, a->rd, dest); 992 return true; 993 } 994 995 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 996 void (*func)(TCGv, TCGv, TCGv), 997 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 998 { 999 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1000 TCGv ext2 = tcg_temp_new(); 1001 int max_len = get_olen(ctx); 1002 1003 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1004 1005 TCGv dest = dest_gpr(ctx, a->rd); 1006 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1007 1008 if (max_len < 128) { 1009 func(dest, src1, ext2); 1010 gen_set_gpr(ctx, a->rd, dest); 1011 } else { 1012 TCGv src1h = get_gprh(ctx, a->rs1); 1013 TCGv desth = dest_gprh(ctx, a->rd); 1014 1015 if (f128 == NULL) { 1016 return false; 1017 } 1018 f128(dest, desth, src1, src1h, ext2); 1019 gen_set_gpr128(ctx, a->rd, dest, desth); 1020 } 1021 return true; 1022 } 1023 1024 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1025 void (*f_tl)(TCGv, TCGv, TCGv), 1026 void (*f_32)(TCGv, TCGv, TCGv), 1027 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1028 { 1029 int olen = get_olen(ctx); 1030 if (olen != TARGET_LONG_BITS) { 1031 if (olen == 32) { 1032 f_tl = f_32; 1033 } else if (olen != 128) { 1034 g_assert_not_reached(); 1035 } 1036 } 1037 return gen_shift(ctx, a, ext, f_tl, f_128); 1038 } 1039 1040 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1041 void (*func)(TCGv, TCGv)) 1042 { 1043 TCGv dest = dest_gpr(ctx, a->rd); 1044 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1045 1046 func(dest, src1); 1047 1048 gen_set_gpr(ctx, a->rd, dest); 1049 return true; 1050 } 1051 1052 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1053 void (*f_tl)(TCGv, TCGv), 1054 void (*f_32)(TCGv, TCGv)) 1055 { 1056 int olen = get_olen(ctx); 1057 1058 if (olen != TARGET_LONG_BITS) { 1059 if (olen == 32) { 1060 f_tl = f_32; 1061 } else { 1062 g_assert_not_reached(); 1063 } 1064 } 1065 return gen_unary(ctx, a, ext, f_tl); 1066 } 1067 1068 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1069 { 1070 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1071 CPUState *cpu = ctx->cs; 1072 CPURISCVState *env = cpu->env_ptr; 1073 1074 return cpu_ldl_code(env, pc); 1075 } 1076 1077 /* Include insn module translation function */ 1078 #include "insn_trans/trans_rvi.c.inc" 1079 #include "insn_trans/trans_rvm.c.inc" 1080 #include "insn_trans/trans_rva.c.inc" 1081 #include "insn_trans/trans_rvf.c.inc" 1082 #include "insn_trans/trans_rvd.c.inc" 1083 #include "insn_trans/trans_rvh.c.inc" 1084 #include "insn_trans/trans_rvv.c.inc" 1085 #include "insn_trans/trans_rvb.c.inc" 1086 #include "insn_trans/trans_rvzicond.c.inc" 1087 #include "insn_trans/trans_rvzawrs.c.inc" 1088 #include "insn_trans/trans_rvzicbo.c.inc" 1089 #include "insn_trans/trans_rvzfh.c.inc" 1090 #include "insn_trans/trans_rvk.c.inc" 1091 #include "insn_trans/trans_privileged.c.inc" 1092 #include "insn_trans/trans_svinval.c.inc" 1093 #include "decode-xthead.c.inc" 1094 #include "insn_trans/trans_xthead.c.inc" 1095 #include "insn_trans/trans_xventanacondops.c.inc" 1096 1097 /* Include the auto-generated decoder for 16 bit insn */ 1098 #include "decode-insn16.c.inc" 1099 #include "insn_trans/trans_rvzce.c.inc" 1100 1101 /* Include decoders for factored-out extensions */ 1102 #include "decode-XVentanaCondOps.c.inc" 1103 1104 /* The specification allows for longer insns, but not supported by qemu. */ 1105 #define MAX_INSN_LEN 4 1106 1107 static inline int insn_len(uint16_t first_word) 1108 { 1109 return (first_word & 3) == 3 ? 4 : 2; 1110 } 1111 1112 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1113 { 1114 /* 1115 * A table with predicate (i.e., guard) functions and decoder functions 1116 * that are tested in-order until a decoder matches onto the opcode. 1117 */ 1118 static const struct { 1119 bool (*guard_func)(DisasContext *); 1120 bool (*decode_func)(DisasContext *, uint32_t); 1121 } decoders[] = { 1122 { always_true_p, decode_insn32 }, 1123 { has_xthead_p, decode_xthead }, 1124 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1125 }; 1126 1127 ctx->virt_inst_excp = false; 1128 /* Check for compressed insn */ 1129 if (insn_len(opcode) == 2) { 1130 ctx->opcode = opcode; 1131 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1132 /* 1133 * The Zca extension is added as way to refer to instructions in the C 1134 * extension that do not include the floating-point loads and stores 1135 */ 1136 if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { 1137 return; 1138 } 1139 } else { 1140 uint32_t opcode32 = opcode; 1141 opcode32 = deposit32(opcode32, 16, 16, 1142 translator_lduw(env, &ctx->base, 1143 ctx->base.pc_next + 2)); 1144 ctx->opcode = opcode32; 1145 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1146 1147 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1148 if (decoders[i].guard_func(ctx) && 1149 decoders[i].decode_func(ctx, opcode32)) { 1150 return; 1151 } 1152 } 1153 } 1154 1155 gen_exception_illegal(ctx); 1156 } 1157 1158 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1159 { 1160 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1161 CPURISCVState *env = cs->env_ptr; 1162 RISCVCPU *cpu = RISCV_CPU(cs); 1163 uint32_t tb_flags = ctx->base.tb->flags; 1164 1165 ctx->pc_succ_insn = ctx->base.pc_first; 1166 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1167 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1168 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1169 ctx->priv_ver = env->priv_ver; 1170 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1171 ctx->misa_ext = env->misa_ext; 1172 ctx->frm = -1; /* unknown rounding mode */ 1173 ctx->cfg_ptr = &(cpu->cfg); 1174 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1175 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1176 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1177 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1178 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1179 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1180 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1181 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1182 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1183 ctx->vstart = env->vstart; 1184 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1185 ctx->misa_mxl_max = env->misa_mxl_max; 1186 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1187 ctx->cs = cs; 1188 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1189 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1190 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1191 ctx->zero = tcg_constant_tl(0); 1192 ctx->virt_inst_excp = false; 1193 } 1194 1195 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1196 { 1197 } 1198 1199 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1200 { 1201 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1202 1203 tcg_gen_insn_start(ctx->base.pc_next, 0); 1204 ctx->insn_start = tcg_last_op(); 1205 } 1206 1207 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1208 { 1209 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1210 CPURISCVState *env = cpu->env_ptr; 1211 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1212 1213 ctx->ol = ctx->xl; 1214 decode_opc(env, ctx, opcode16); 1215 ctx->base.pc_next = ctx->pc_succ_insn; 1216 1217 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1218 if (ctx->base.is_jmp == DISAS_NEXT) { 1219 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1220 ctx->base.is_jmp = DISAS_TOO_MANY; 1221 } else { 1222 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1223 1224 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1225 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1226 int len = insn_len(next_insn); 1227 1228 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1229 ctx->base.is_jmp = DISAS_TOO_MANY; 1230 } 1231 } 1232 } 1233 } 1234 } 1235 1236 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1237 { 1238 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1239 1240 switch (ctx->base.is_jmp) { 1241 case DISAS_TOO_MANY: 1242 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1243 break; 1244 case DISAS_NORETURN: 1245 break; 1246 default: 1247 g_assert_not_reached(); 1248 } 1249 } 1250 1251 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1252 CPUState *cpu, FILE *logfile) 1253 { 1254 #ifndef CONFIG_USER_ONLY 1255 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1256 CPURISCVState *env = &rvcpu->env; 1257 #endif 1258 1259 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1260 #ifndef CONFIG_USER_ONLY 1261 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: %d\n", 1262 env->priv, env->virt_enabled); 1263 #endif 1264 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1265 } 1266 1267 static const TranslatorOps riscv_tr_ops = { 1268 .init_disas_context = riscv_tr_init_disas_context, 1269 .tb_start = riscv_tr_tb_start, 1270 .insn_start = riscv_tr_insn_start, 1271 .translate_insn = riscv_tr_translate_insn, 1272 .tb_stop = riscv_tr_tb_stop, 1273 .disas_log = riscv_tr_disas_log, 1274 }; 1275 1276 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1277 target_ulong pc, void *host_pc) 1278 { 1279 DisasContext ctx; 1280 1281 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1282 } 1283 1284 void riscv_translate_init(void) 1285 { 1286 int i; 1287 1288 /* 1289 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1290 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1291 * unless you specifically block reads/writes to reg 0. 1292 */ 1293 cpu_gpr[0] = NULL; 1294 cpu_gprh[0] = NULL; 1295 1296 for (i = 1; i < 32; i++) { 1297 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1298 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1299 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1300 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1301 } 1302 1303 for (i = 0; i < 32; i++) { 1304 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1305 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1306 } 1307 1308 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1309 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1310 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1311 "vstart"); 1312 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1313 "load_res"); 1314 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1315 "load_val"); 1316 /* Assign PM CSRs to tcg globals */ 1317 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1318 "pmmask"); 1319 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1320 "pmbase"); 1321 } 1322