1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 105 TCGv_i64 ftemp[4]; 106 uint8_t nftemp; 107 /* PointerMasking extension */ 108 bool pm_mask_enabled; 109 bool pm_base_enabled; 110 } DisasContext; 111 112 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 113 { 114 return ctx->misa_ext & ext; 115 } 116 117 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 118 { 119 return true; 120 } 121 122 #define MATERIALISE_EXT_PREDICATE(ext) \ 123 static bool has_ ## ext ## _p(DisasContext *ctx) \ 124 { \ 125 return ctx->cfg_ptr->ext_ ## ext ; \ 126 } 127 128 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 129 130 #ifdef TARGET_RISCV32 131 #define get_xl(ctx) MXL_RV32 132 #elif defined(CONFIG_USER_ONLY) 133 #define get_xl(ctx) MXL_RV64 134 #else 135 #define get_xl(ctx) ((ctx)->xl) 136 #endif 137 138 /* The word size for this machine mode. */ 139 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 140 { 141 return 16 << get_xl(ctx); 142 } 143 144 /* The operation length, as opposed to the xlen. */ 145 #ifdef TARGET_RISCV32 146 #define get_ol(ctx) MXL_RV32 147 #else 148 #define get_ol(ctx) ((ctx)->ol) 149 #endif 150 151 static inline int get_olen(DisasContext *ctx) 152 { 153 return 16 << get_ol(ctx); 154 } 155 156 /* The maximum register length */ 157 #ifdef TARGET_RISCV32 158 #define get_xl_max(ctx) MXL_RV32 159 #else 160 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 161 #endif 162 163 /* 164 * RISC-V requires NaN-boxing of narrower width floating point values. 165 * This applies when a 32-bit value is assigned to a 64-bit FP register. 166 * For consistency and simplicity, we nanbox results even when the RVD 167 * extension is not present. 168 */ 169 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 170 { 171 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 172 } 173 174 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 175 { 176 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 177 } 178 179 /* 180 * A narrow n-bit operation, where n < FLEN, checks that input operands 181 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 182 * If so, the least-significant bits of the input are used, otherwise the 183 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 184 * 185 * Here, the result is always nan-boxed, even the canonical nan. 186 */ 187 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 188 { 189 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 190 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 191 192 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 193 tcg_temp_free_i64(t_max); 194 tcg_temp_free_i64(t_nan); 195 } 196 197 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 198 { 199 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 200 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 201 202 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 203 } 204 205 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 206 { 207 if (get_xl(ctx) == MXL_RV32) { 208 dest = (int32_t)dest; 209 } 210 tcg_gen_movi_tl(cpu_pc, dest); 211 } 212 213 static void gen_set_pc(DisasContext *ctx, TCGv dest) 214 { 215 if (get_xl(ctx) == MXL_RV32) { 216 tcg_gen_ext32s_tl(cpu_pc, dest); 217 } else { 218 tcg_gen_mov_tl(cpu_pc, dest); 219 } 220 } 221 222 static void generate_exception(DisasContext *ctx, int excp) 223 { 224 gen_set_pc_imm(ctx, ctx->base.pc_next); 225 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 226 ctx->base.is_jmp = DISAS_NORETURN; 227 } 228 229 static void generate_exception_mtval(DisasContext *ctx, int excp) 230 { 231 gen_set_pc_imm(ctx, ctx->base.pc_next); 232 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 233 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 234 ctx->base.is_jmp = DISAS_NORETURN; 235 } 236 237 static void gen_exception_illegal(DisasContext *ctx) 238 { 239 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 240 offsetof(CPURISCVState, bins)); 241 242 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 243 } 244 245 static void gen_exception_inst_addr_mis(DisasContext *ctx) 246 { 247 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 248 } 249 250 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 251 { 252 if (translator_use_goto_tb(&ctx->base, dest)) { 253 tcg_gen_goto_tb(n); 254 gen_set_pc_imm(ctx, dest); 255 tcg_gen_exit_tb(ctx->base.tb, n); 256 } else { 257 gen_set_pc_imm(ctx, dest); 258 tcg_gen_lookup_and_goto_ptr(); 259 } 260 } 261 262 /* 263 * Wrappers for getting reg values. 264 * 265 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 266 * constant zero as a source, and an uninitialized sink as destination. 267 * 268 * Further, we may provide an extension for word operations. 269 */ 270 static TCGv temp_new(DisasContext *ctx) 271 { 272 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 273 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 274 } 275 276 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 277 { 278 TCGv t; 279 280 if (reg_num == 0) { 281 return ctx->zero; 282 } 283 284 switch (get_ol(ctx)) { 285 case MXL_RV32: 286 switch (ext) { 287 case EXT_NONE: 288 break; 289 case EXT_SIGN: 290 t = temp_new(ctx); 291 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 292 return t; 293 case EXT_ZERO: 294 t = temp_new(ctx); 295 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 296 return t; 297 default: 298 g_assert_not_reached(); 299 } 300 break; 301 case MXL_RV64: 302 case MXL_RV128: 303 break; 304 default: 305 g_assert_not_reached(); 306 } 307 return cpu_gpr[reg_num]; 308 } 309 310 static TCGv get_gprh(DisasContext *ctx, int reg_num) 311 { 312 assert(get_xl(ctx) == MXL_RV128); 313 if (reg_num == 0) { 314 return ctx->zero; 315 } 316 return cpu_gprh[reg_num]; 317 } 318 319 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 320 { 321 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 322 return temp_new(ctx); 323 } 324 return cpu_gpr[reg_num]; 325 } 326 327 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 328 { 329 if (reg_num == 0) { 330 return temp_new(ctx); 331 } 332 return cpu_gprh[reg_num]; 333 } 334 335 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 336 { 337 if (reg_num != 0) { 338 switch (get_ol(ctx)) { 339 case MXL_RV32: 340 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 341 break; 342 case MXL_RV64: 343 case MXL_RV128: 344 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 345 break; 346 default: 347 g_assert_not_reached(); 348 } 349 350 if (get_xl_max(ctx) == MXL_RV128) { 351 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 352 } 353 } 354 } 355 356 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 357 { 358 if (reg_num != 0) { 359 switch (get_ol(ctx)) { 360 case MXL_RV32: 361 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 362 break; 363 case MXL_RV64: 364 case MXL_RV128: 365 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 366 break; 367 default: 368 g_assert_not_reached(); 369 } 370 371 if (get_xl_max(ctx) == MXL_RV128) { 372 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 373 } 374 } 375 } 376 377 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 378 { 379 assert(get_ol(ctx) == MXL_RV128); 380 if (reg_num != 0) { 381 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 382 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 383 } 384 } 385 386 static TCGv_i64 ftemp_new(DisasContext *ctx) 387 { 388 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 389 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 390 } 391 392 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 393 { 394 if (!ctx->cfg_ptr->ext_zfinx) { 395 return cpu_fpr[reg_num]; 396 } 397 398 if (reg_num == 0) { 399 return tcg_constant_i64(0); 400 } 401 switch (get_xl(ctx)) { 402 case MXL_RV32: 403 #ifdef TARGET_RISCV32 404 { 405 TCGv_i64 t = ftemp_new(ctx); 406 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 407 return t; 408 } 409 #else 410 /* fall through */ 411 case MXL_RV64: 412 return cpu_gpr[reg_num]; 413 #endif 414 default: 415 g_assert_not_reached(); 416 } 417 } 418 419 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 420 { 421 if (!ctx->cfg_ptr->ext_zfinx) { 422 return cpu_fpr[reg_num]; 423 } 424 425 if (reg_num == 0) { 426 return ftemp_new(ctx); 427 } 428 429 switch (get_xl(ctx)) { 430 case MXL_RV32: 431 return ftemp_new(ctx); 432 #ifdef TARGET_RISCV64 433 case MXL_RV64: 434 return cpu_gpr[reg_num]; 435 #endif 436 default: 437 g_assert_not_reached(); 438 } 439 } 440 441 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 442 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 443 { 444 if (!ctx->cfg_ptr->ext_zfinx) { 445 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 446 return; 447 } 448 if (reg_num != 0) { 449 switch (get_xl(ctx)) { 450 case MXL_RV32: 451 #ifdef TARGET_RISCV32 452 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 453 break; 454 #else 455 /* fall through */ 456 case MXL_RV64: 457 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 458 break; 459 #endif 460 default: 461 g_assert_not_reached(); 462 } 463 } 464 } 465 466 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 467 { 468 target_ulong next_pc; 469 470 /* check misaligned: */ 471 next_pc = ctx->base.pc_next + imm; 472 if (!has_ext(ctx, RVC)) { 473 if ((next_pc & 0x3) != 0) { 474 gen_exception_inst_addr_mis(ctx); 475 return; 476 } 477 } 478 479 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 480 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 481 ctx->base.is_jmp = DISAS_NORETURN; 482 } 483 484 /* Compute a canonical address from a register plus offset. */ 485 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 486 { 487 TCGv addr = temp_new(ctx); 488 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 489 490 tcg_gen_addi_tl(addr, src1, imm); 491 if (ctx->pm_mask_enabled) { 492 tcg_gen_and_tl(addr, addr, pm_mask); 493 } else if (get_xl(ctx) == MXL_RV32) { 494 tcg_gen_ext32u_tl(addr, addr); 495 } 496 if (ctx->pm_base_enabled) { 497 tcg_gen_or_tl(addr, addr, pm_base); 498 } 499 return addr; 500 } 501 502 #ifndef CONFIG_USER_ONLY 503 /* The states of mstatus_fs are: 504 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 505 * We will have already diagnosed disabled state, 506 * and need to turn initial/clean into dirty. 507 */ 508 static void mark_fs_dirty(DisasContext *ctx) 509 { 510 TCGv tmp; 511 512 if (!has_ext(ctx, RVF)) { 513 return; 514 } 515 516 if (ctx->mstatus_fs != MSTATUS_FS) { 517 /* Remember the state change for the rest of the TB. */ 518 ctx->mstatus_fs = MSTATUS_FS; 519 520 tmp = tcg_temp_new(); 521 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 522 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 523 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 524 tcg_temp_free(tmp); 525 } 526 527 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 528 /* Remember the stage change for the rest of the TB. */ 529 ctx->mstatus_hs_fs = MSTATUS_FS; 530 531 tmp = tcg_temp_new(); 532 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 533 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 534 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 535 tcg_temp_free(tmp); 536 } 537 } 538 #else 539 static inline void mark_fs_dirty(DisasContext *ctx) { } 540 #endif 541 542 #ifndef CONFIG_USER_ONLY 543 /* The states of mstatus_vs are: 544 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 545 * We will have already diagnosed disabled state, 546 * and need to turn initial/clean into dirty. 547 */ 548 static void mark_vs_dirty(DisasContext *ctx) 549 { 550 TCGv tmp; 551 552 if (ctx->mstatus_vs != MSTATUS_VS) { 553 /* Remember the state change for the rest of the TB. */ 554 ctx->mstatus_vs = MSTATUS_VS; 555 556 tmp = tcg_temp_new(); 557 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 558 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 559 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 560 tcg_temp_free(tmp); 561 } 562 563 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 564 /* Remember the stage change for the rest of the TB. */ 565 ctx->mstatus_hs_vs = MSTATUS_VS; 566 567 tmp = tcg_temp_new(); 568 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 569 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 570 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 571 tcg_temp_free(tmp); 572 } 573 } 574 #else 575 static inline void mark_vs_dirty(DisasContext *ctx) { } 576 #endif 577 578 static void gen_set_rm(DisasContext *ctx, int rm) 579 { 580 if (ctx->frm == rm) { 581 return; 582 } 583 ctx->frm = rm; 584 585 if (rm == RISCV_FRM_ROD) { 586 gen_helper_set_rod_rounding_mode(cpu_env); 587 return; 588 } 589 590 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 591 } 592 593 static int ex_plus_1(DisasContext *ctx, int nf) 594 { 595 return nf + 1; 596 } 597 598 #define EX_SH(amount) \ 599 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 600 { \ 601 return imm << amount; \ 602 } 603 EX_SH(1) 604 EX_SH(2) 605 EX_SH(3) 606 EX_SH(4) 607 EX_SH(12) 608 609 #define REQUIRE_EXT(ctx, ext) do { \ 610 if (!has_ext(ctx, ext)) { \ 611 return false; \ 612 } \ 613 } while (0) 614 615 #define REQUIRE_32BIT(ctx) do { \ 616 if (get_xl(ctx) != MXL_RV32) { \ 617 return false; \ 618 } \ 619 } while (0) 620 621 #define REQUIRE_64BIT(ctx) do { \ 622 if (get_xl(ctx) != MXL_RV64) { \ 623 return false; \ 624 } \ 625 } while (0) 626 627 #define REQUIRE_128BIT(ctx) do { \ 628 if (get_xl(ctx) != MXL_RV128) { \ 629 return false; \ 630 } \ 631 } while (0) 632 633 #define REQUIRE_64_OR_128BIT(ctx) do { \ 634 if (get_xl(ctx) == MXL_RV32) { \ 635 return false; \ 636 } \ 637 } while (0) 638 639 static int ex_rvc_register(DisasContext *ctx, int reg) 640 { 641 return 8 + reg; 642 } 643 644 static int ex_rvc_shifti(DisasContext *ctx, int imm) 645 { 646 /* For RV128 a shamt of 0 means a shift by 64. */ 647 return imm ? imm : 64; 648 } 649 650 /* Include the auto-generated decoder for 32 bit insn */ 651 #include "decode-insn32.c.inc" 652 653 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 654 void (*func)(TCGv, TCGv, target_long)) 655 { 656 TCGv dest = dest_gpr(ctx, a->rd); 657 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 658 659 func(dest, src1, a->imm); 660 661 if (get_xl(ctx) == MXL_RV128) { 662 TCGv src1h = get_gprh(ctx, a->rs1); 663 TCGv desth = dest_gprh(ctx, a->rd); 664 665 func(desth, src1h, -(a->imm < 0)); 666 gen_set_gpr128(ctx, a->rd, dest, desth); 667 } else { 668 gen_set_gpr(ctx, a->rd, dest); 669 } 670 671 return true; 672 } 673 674 static bool gen_logic(DisasContext *ctx, arg_r *a, 675 void (*func)(TCGv, TCGv, TCGv)) 676 { 677 TCGv dest = dest_gpr(ctx, a->rd); 678 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 679 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 680 681 func(dest, src1, src2); 682 683 if (get_xl(ctx) == MXL_RV128) { 684 TCGv src1h = get_gprh(ctx, a->rs1); 685 TCGv src2h = get_gprh(ctx, a->rs2); 686 TCGv desth = dest_gprh(ctx, a->rd); 687 688 func(desth, src1h, src2h); 689 gen_set_gpr128(ctx, a->rd, dest, desth); 690 } else { 691 gen_set_gpr(ctx, a->rd, dest); 692 } 693 694 return true; 695 } 696 697 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 698 void (*func)(TCGv, TCGv, target_long), 699 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 700 { 701 TCGv dest = dest_gpr(ctx, a->rd); 702 TCGv src1 = get_gpr(ctx, a->rs1, ext); 703 704 if (get_ol(ctx) < MXL_RV128) { 705 func(dest, src1, a->imm); 706 gen_set_gpr(ctx, a->rd, dest); 707 } else { 708 if (f128 == NULL) { 709 return false; 710 } 711 712 TCGv src1h = get_gprh(ctx, a->rs1); 713 TCGv desth = dest_gprh(ctx, a->rd); 714 715 f128(dest, desth, src1, src1h, a->imm); 716 gen_set_gpr128(ctx, a->rd, dest, desth); 717 } 718 return true; 719 } 720 721 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 722 void (*func)(TCGv, TCGv, TCGv), 723 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 724 { 725 TCGv dest = dest_gpr(ctx, a->rd); 726 TCGv src1 = get_gpr(ctx, a->rs1, ext); 727 TCGv src2 = tcg_constant_tl(a->imm); 728 729 if (get_ol(ctx) < MXL_RV128) { 730 func(dest, src1, src2); 731 gen_set_gpr(ctx, a->rd, dest); 732 } else { 733 if (f128 == NULL) { 734 return false; 735 } 736 737 TCGv src1h = get_gprh(ctx, a->rs1); 738 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 739 TCGv desth = dest_gprh(ctx, a->rd); 740 741 f128(dest, desth, src1, src1h, src2, src2h); 742 gen_set_gpr128(ctx, a->rd, dest, desth); 743 } 744 return true; 745 } 746 747 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 748 void (*func)(TCGv, TCGv, TCGv), 749 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 750 { 751 TCGv dest = dest_gpr(ctx, a->rd); 752 TCGv src1 = get_gpr(ctx, a->rs1, ext); 753 TCGv src2 = get_gpr(ctx, a->rs2, ext); 754 755 if (get_ol(ctx) < MXL_RV128) { 756 func(dest, src1, src2); 757 gen_set_gpr(ctx, a->rd, dest); 758 } else { 759 if (f128 == NULL) { 760 return false; 761 } 762 763 TCGv src1h = get_gprh(ctx, a->rs1); 764 TCGv src2h = get_gprh(ctx, a->rs2); 765 TCGv desth = dest_gprh(ctx, a->rd); 766 767 f128(dest, desth, src1, src1h, src2, src2h); 768 gen_set_gpr128(ctx, a->rd, dest, desth); 769 } 770 return true; 771 } 772 773 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 774 void (*f_tl)(TCGv, TCGv, TCGv), 775 void (*f_32)(TCGv, TCGv, TCGv), 776 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 777 { 778 int olen = get_olen(ctx); 779 780 if (olen != TARGET_LONG_BITS) { 781 if (olen == 32) { 782 f_tl = f_32; 783 } else if (olen != 128) { 784 g_assert_not_reached(); 785 } 786 } 787 return gen_arith(ctx, a, ext, f_tl, f_128); 788 } 789 790 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 791 void (*func)(TCGv, TCGv, target_long), 792 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 793 { 794 TCGv dest, src1; 795 int max_len = get_olen(ctx); 796 797 if (a->shamt >= max_len) { 798 return false; 799 } 800 801 dest = dest_gpr(ctx, a->rd); 802 src1 = get_gpr(ctx, a->rs1, ext); 803 804 if (max_len < 128) { 805 func(dest, src1, a->shamt); 806 gen_set_gpr(ctx, a->rd, dest); 807 } else { 808 TCGv src1h = get_gprh(ctx, a->rs1); 809 TCGv desth = dest_gprh(ctx, a->rd); 810 811 if (f128 == NULL) { 812 return false; 813 } 814 f128(dest, desth, src1, src1h, a->shamt); 815 gen_set_gpr128(ctx, a->rd, dest, desth); 816 } 817 return true; 818 } 819 820 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 821 DisasExtend ext, 822 void (*f_tl)(TCGv, TCGv, target_long), 823 void (*f_32)(TCGv, TCGv, target_long), 824 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 825 target_long)) 826 { 827 int olen = get_olen(ctx); 828 if (olen != TARGET_LONG_BITS) { 829 if (olen == 32) { 830 f_tl = f_32; 831 } else if (olen != 128) { 832 g_assert_not_reached(); 833 } 834 } 835 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 836 } 837 838 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 839 void (*func)(TCGv, TCGv, TCGv)) 840 { 841 TCGv dest, src1, src2; 842 int max_len = get_olen(ctx); 843 844 if (a->shamt >= max_len) { 845 return false; 846 } 847 848 dest = dest_gpr(ctx, a->rd); 849 src1 = get_gpr(ctx, a->rs1, ext); 850 src2 = tcg_constant_tl(a->shamt); 851 852 func(dest, src1, src2); 853 854 gen_set_gpr(ctx, a->rd, dest); 855 return true; 856 } 857 858 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 859 void (*func)(TCGv, TCGv, TCGv), 860 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 861 { 862 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 863 TCGv ext2 = tcg_temp_new(); 864 int max_len = get_olen(ctx); 865 866 tcg_gen_andi_tl(ext2, src2, max_len - 1); 867 868 TCGv dest = dest_gpr(ctx, a->rd); 869 TCGv src1 = get_gpr(ctx, a->rs1, ext); 870 871 if (max_len < 128) { 872 func(dest, src1, ext2); 873 gen_set_gpr(ctx, a->rd, dest); 874 } else { 875 TCGv src1h = get_gprh(ctx, a->rs1); 876 TCGv desth = dest_gprh(ctx, a->rd); 877 878 if (f128 == NULL) { 879 return false; 880 } 881 f128(dest, desth, src1, src1h, ext2); 882 gen_set_gpr128(ctx, a->rd, dest, desth); 883 } 884 tcg_temp_free(ext2); 885 return true; 886 } 887 888 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 889 void (*f_tl)(TCGv, TCGv, TCGv), 890 void (*f_32)(TCGv, TCGv, TCGv), 891 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 892 { 893 int olen = get_olen(ctx); 894 if (olen != TARGET_LONG_BITS) { 895 if (olen == 32) { 896 f_tl = f_32; 897 } else if (olen != 128) { 898 g_assert_not_reached(); 899 } 900 } 901 return gen_shift(ctx, a, ext, f_tl, f_128); 902 } 903 904 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 905 void (*func)(TCGv, TCGv)) 906 { 907 TCGv dest = dest_gpr(ctx, a->rd); 908 TCGv src1 = get_gpr(ctx, a->rs1, ext); 909 910 func(dest, src1); 911 912 gen_set_gpr(ctx, a->rd, dest); 913 return true; 914 } 915 916 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 917 void (*f_tl)(TCGv, TCGv), 918 void (*f_32)(TCGv, TCGv)) 919 { 920 int olen = get_olen(ctx); 921 922 if (olen != TARGET_LONG_BITS) { 923 if (olen == 32) { 924 f_tl = f_32; 925 } else { 926 g_assert_not_reached(); 927 } 928 } 929 return gen_unary(ctx, a, ext, f_tl); 930 } 931 932 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 933 { 934 DisasContext *ctx = container_of(dcbase, DisasContext, base); 935 CPUState *cpu = ctx->cs; 936 CPURISCVState *env = cpu->env_ptr; 937 938 return cpu_ldl_code(env, pc); 939 } 940 941 /* Include insn module translation function */ 942 #include "insn_trans/trans_rvi.c.inc" 943 #include "insn_trans/trans_rvm.c.inc" 944 #include "insn_trans/trans_rva.c.inc" 945 #include "insn_trans/trans_rvf.c.inc" 946 #include "insn_trans/trans_rvd.c.inc" 947 #include "insn_trans/trans_rvh.c.inc" 948 #include "insn_trans/trans_rvv.c.inc" 949 #include "insn_trans/trans_rvb.c.inc" 950 #include "insn_trans/trans_rvzfh.c.inc" 951 #include "insn_trans/trans_privileged.c.inc" 952 #include "insn_trans/trans_svinval.c.inc" 953 #include "insn_trans/trans_xventanacondops.c.inc" 954 955 /* Include the auto-generated decoder for 16 bit insn */ 956 #include "decode-insn16.c.inc" 957 /* Include decoders for factored-out extensions */ 958 #include "decode-XVentanaCondOps.c.inc" 959 960 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 961 { 962 /* 963 * A table with predicate (i.e., guard) functions and decoder functions 964 * that are tested in-order until a decoder matches onto the opcode. 965 */ 966 static const struct { 967 bool (*guard_func)(DisasContext *); 968 bool (*decode_func)(DisasContext *, uint32_t); 969 } decoders[] = { 970 { always_true_p, decode_insn32 }, 971 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 972 }; 973 974 /* Check for compressed insn */ 975 if (extract16(opcode, 0, 2) != 3) { 976 if (!has_ext(ctx, RVC)) { 977 gen_exception_illegal(ctx); 978 } else { 979 ctx->opcode = opcode; 980 ctx->pc_succ_insn = ctx->base.pc_next + 2; 981 if (decode_insn16(ctx, opcode)) { 982 return; 983 } 984 } 985 } else { 986 uint32_t opcode32 = opcode; 987 opcode32 = deposit32(opcode32, 16, 16, 988 translator_lduw(env, &ctx->base, 989 ctx->base.pc_next + 2)); 990 ctx->opcode = opcode32; 991 ctx->pc_succ_insn = ctx->base.pc_next + 4; 992 993 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 994 if (decoders[i].guard_func(ctx) && 995 decoders[i].decode_func(ctx, opcode32)) { 996 return; 997 } 998 } 999 } 1000 1001 gen_exception_illegal(ctx); 1002 } 1003 1004 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1005 { 1006 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1007 CPURISCVState *env = cs->env_ptr; 1008 RISCVCPU *cpu = RISCV_CPU(cs); 1009 uint32_t tb_flags = ctx->base.tb->flags; 1010 1011 ctx->pc_succ_insn = ctx->base.pc_first; 1012 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1013 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1014 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1015 ctx->priv_ver = env->priv_ver; 1016 #if !defined(CONFIG_USER_ONLY) 1017 if (riscv_has_ext(env, RVH)) { 1018 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1019 } else { 1020 ctx->virt_enabled = false; 1021 } 1022 #else 1023 ctx->virt_enabled = false; 1024 #endif 1025 ctx->misa_ext = env->misa_ext; 1026 ctx->frm = -1; /* unknown rounding mode */ 1027 ctx->cfg_ptr = &(cpu->cfg); 1028 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1029 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1030 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1031 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1032 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1033 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1034 ctx->vstart = env->vstart; 1035 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1036 ctx->misa_mxl_max = env->misa_mxl_max; 1037 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1038 ctx->cs = cs; 1039 ctx->ntemp = 0; 1040 memset(ctx->temp, 0, sizeof(ctx->temp)); 1041 ctx->nftemp = 0; 1042 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1043 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1044 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1045 ctx->zero = tcg_constant_tl(0); 1046 } 1047 1048 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1049 { 1050 } 1051 1052 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1053 { 1054 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1055 1056 tcg_gen_insn_start(ctx->base.pc_next); 1057 } 1058 1059 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1060 { 1061 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1062 CPURISCVState *env = cpu->env_ptr; 1063 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1064 int i; 1065 1066 ctx->ol = ctx->xl; 1067 decode_opc(env, ctx, opcode16); 1068 ctx->base.pc_next = ctx->pc_succ_insn; 1069 1070 for (i = ctx->ntemp - 1; i >= 0; --i) { 1071 tcg_temp_free(ctx->temp[i]); 1072 ctx->temp[i] = NULL; 1073 } 1074 ctx->ntemp = 0; 1075 for (i = ctx->nftemp - 1; i >= 0; --i) { 1076 tcg_temp_free_i64(ctx->ftemp[i]); 1077 ctx->ftemp[i] = NULL; 1078 } 1079 ctx->nftemp = 0; 1080 1081 if (ctx->base.is_jmp == DISAS_NEXT) { 1082 target_ulong page_start; 1083 1084 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1085 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 1086 ctx->base.is_jmp = DISAS_TOO_MANY; 1087 } 1088 } 1089 } 1090 1091 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1092 { 1093 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1094 1095 switch (ctx->base.is_jmp) { 1096 case DISAS_TOO_MANY: 1097 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1098 break; 1099 case DISAS_NORETURN: 1100 break; 1101 default: 1102 g_assert_not_reached(); 1103 } 1104 } 1105 1106 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 1107 { 1108 #ifndef CONFIG_USER_ONLY 1109 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1110 CPURISCVState *env = &rvcpu->env; 1111 #endif 1112 1113 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 1114 #ifndef CONFIG_USER_ONLY 1115 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 1116 #endif 1117 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1118 } 1119 1120 static const TranslatorOps riscv_tr_ops = { 1121 .init_disas_context = riscv_tr_init_disas_context, 1122 .tb_start = riscv_tr_tb_start, 1123 .insn_start = riscv_tr_insn_start, 1124 .translate_insn = riscv_tr_translate_insn, 1125 .tb_stop = riscv_tr_tb_stop, 1126 .disas_log = riscv_tr_disas_log, 1127 }; 1128 1129 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1130 { 1131 DisasContext ctx; 1132 1133 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1134 } 1135 1136 void riscv_translate_init(void) 1137 { 1138 int i; 1139 1140 /* 1141 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1142 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1143 * unless you specifically block reads/writes to reg 0. 1144 */ 1145 cpu_gpr[0] = NULL; 1146 cpu_gprh[0] = NULL; 1147 1148 for (i = 1; i < 32; i++) { 1149 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1150 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1151 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1152 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1153 } 1154 1155 for (i = 0; i < 32; i++) { 1156 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1157 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1158 } 1159 1160 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1161 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1162 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1163 "vstart"); 1164 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1165 "load_res"); 1166 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1167 "load_val"); 1168 /* Assign PM CSRs to tcg globals */ 1169 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1170 "pmmask"); 1171 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1172 "pmbase"); 1173 } 1174