1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 uint8_t vta; 98 bool cfg_vta_all_1s; 99 target_ulong vstart; 100 bool vl_eq_vlmax; 101 uint8_t ntemp; 102 CPUState *cs; 103 TCGv zero; 104 /* Space for 3 operands plus 1 extra for address computation. */ 105 TCGv temp[4]; 106 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 107 TCGv_i64 ftemp[4]; 108 uint8_t nftemp; 109 /* PointerMasking extension */ 110 bool pm_mask_enabled; 111 bool pm_base_enabled; 112 /* TCG of the current insn_start */ 113 TCGOp *insn_start; 114 } DisasContext; 115 116 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 117 { 118 return ctx->misa_ext & ext; 119 } 120 121 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 122 { 123 return true; 124 } 125 126 #define MATERIALISE_EXT_PREDICATE(ext) \ 127 static bool has_ ## ext ## _p(DisasContext *ctx) \ 128 { \ 129 return ctx->cfg_ptr->ext_ ## ext ; \ 130 } 131 132 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 133 134 #ifdef TARGET_RISCV32 135 #define get_xl(ctx) MXL_RV32 136 #elif defined(CONFIG_USER_ONLY) 137 #define get_xl(ctx) MXL_RV64 138 #else 139 #define get_xl(ctx) ((ctx)->xl) 140 #endif 141 142 /* The word size for this machine mode. */ 143 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 144 { 145 return 16 << get_xl(ctx); 146 } 147 148 /* The operation length, as opposed to the xlen. */ 149 #ifdef TARGET_RISCV32 150 #define get_ol(ctx) MXL_RV32 151 #else 152 #define get_ol(ctx) ((ctx)->ol) 153 #endif 154 155 static inline int get_olen(DisasContext *ctx) 156 { 157 return 16 << get_ol(ctx); 158 } 159 160 /* The maximum register length */ 161 #ifdef TARGET_RISCV32 162 #define get_xl_max(ctx) MXL_RV32 163 #else 164 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 165 #endif 166 167 /* 168 * RISC-V requires NaN-boxing of narrower width floating point values. 169 * This applies when a 32-bit value is assigned to a 64-bit FP register. 170 * For consistency and simplicity, we nanbox results even when the RVD 171 * extension is not present. 172 */ 173 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 174 { 175 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 176 } 177 178 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 179 { 180 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 181 } 182 183 /* 184 * A narrow n-bit operation, where n < FLEN, checks that input operands 185 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 186 * If so, the least-significant bits of the input are used, otherwise the 187 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 188 * 189 * Here, the result is always nan-boxed, even the canonical nan. 190 */ 191 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 194 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 195 196 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 197 tcg_temp_free_i64(t_max); 198 tcg_temp_free_i64(t_nan); 199 } 200 201 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 202 { 203 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 204 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 205 206 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 207 } 208 209 static void decode_save_opc(DisasContext *ctx) 210 { 211 assert(ctx->insn_start != NULL); 212 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 213 ctx->insn_start = NULL; 214 } 215 216 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 217 { 218 if (get_xl(ctx) == MXL_RV32) { 219 dest = (int32_t)dest; 220 } 221 tcg_gen_movi_tl(cpu_pc, dest); 222 } 223 224 static void gen_set_pc(DisasContext *ctx, TCGv dest) 225 { 226 if (get_xl(ctx) == MXL_RV32) { 227 tcg_gen_ext32s_tl(cpu_pc, dest); 228 } else { 229 tcg_gen_mov_tl(cpu_pc, dest); 230 } 231 } 232 233 static void generate_exception(DisasContext *ctx, int excp) 234 { 235 gen_set_pc_imm(ctx, ctx->base.pc_next); 236 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 237 ctx->base.is_jmp = DISAS_NORETURN; 238 } 239 240 static void gen_exception_illegal(DisasContext *ctx) 241 { 242 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 243 offsetof(CPURISCVState, bins)); 244 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 245 } 246 247 static void gen_exception_inst_addr_mis(DisasContext *ctx) 248 { 249 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 250 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 251 } 252 253 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 254 { 255 if (translator_use_goto_tb(&ctx->base, dest)) { 256 tcg_gen_goto_tb(n); 257 gen_set_pc_imm(ctx, dest); 258 tcg_gen_exit_tb(ctx->base.tb, n); 259 } else { 260 gen_set_pc_imm(ctx, dest); 261 tcg_gen_lookup_and_goto_ptr(); 262 } 263 } 264 265 /* 266 * Wrappers for getting reg values. 267 * 268 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 269 * constant zero as a source, and an uninitialized sink as destination. 270 * 271 * Further, we may provide an extension for word operations. 272 */ 273 static TCGv temp_new(DisasContext *ctx) 274 { 275 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 276 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 277 } 278 279 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 280 { 281 TCGv t; 282 283 if (reg_num == 0) { 284 return ctx->zero; 285 } 286 287 switch (get_ol(ctx)) { 288 case MXL_RV32: 289 switch (ext) { 290 case EXT_NONE: 291 break; 292 case EXT_SIGN: 293 t = temp_new(ctx); 294 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 295 return t; 296 case EXT_ZERO: 297 t = temp_new(ctx); 298 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 299 return t; 300 default: 301 g_assert_not_reached(); 302 } 303 break; 304 case MXL_RV64: 305 case MXL_RV128: 306 break; 307 default: 308 g_assert_not_reached(); 309 } 310 return cpu_gpr[reg_num]; 311 } 312 313 static TCGv get_gprh(DisasContext *ctx, int reg_num) 314 { 315 assert(get_xl(ctx) == MXL_RV128); 316 if (reg_num == 0) { 317 return ctx->zero; 318 } 319 return cpu_gprh[reg_num]; 320 } 321 322 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 323 { 324 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 325 return temp_new(ctx); 326 } 327 return cpu_gpr[reg_num]; 328 } 329 330 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 331 { 332 if (reg_num == 0) { 333 return temp_new(ctx); 334 } 335 return cpu_gprh[reg_num]; 336 } 337 338 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 339 { 340 if (reg_num != 0) { 341 switch (get_ol(ctx)) { 342 case MXL_RV32: 343 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 344 break; 345 case MXL_RV64: 346 case MXL_RV128: 347 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 348 break; 349 default: 350 g_assert_not_reached(); 351 } 352 353 if (get_xl_max(ctx) == MXL_RV128) { 354 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 355 } 356 } 357 } 358 359 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 360 { 361 if (reg_num != 0) { 362 switch (get_ol(ctx)) { 363 case MXL_RV32: 364 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 365 break; 366 case MXL_RV64: 367 case MXL_RV128: 368 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 369 break; 370 default: 371 g_assert_not_reached(); 372 } 373 374 if (get_xl_max(ctx) == MXL_RV128) { 375 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 376 } 377 } 378 } 379 380 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 381 { 382 assert(get_ol(ctx) == MXL_RV128); 383 if (reg_num != 0) { 384 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 385 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 386 } 387 } 388 389 static TCGv_i64 ftemp_new(DisasContext *ctx) 390 { 391 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 392 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 393 } 394 395 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 396 { 397 if (!ctx->cfg_ptr->ext_zfinx) { 398 return cpu_fpr[reg_num]; 399 } 400 401 if (reg_num == 0) { 402 return tcg_constant_i64(0); 403 } 404 switch (get_xl(ctx)) { 405 case MXL_RV32: 406 #ifdef TARGET_RISCV32 407 { 408 TCGv_i64 t = ftemp_new(ctx); 409 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 410 return t; 411 } 412 #else 413 /* fall through */ 414 case MXL_RV64: 415 return cpu_gpr[reg_num]; 416 #endif 417 default: 418 g_assert_not_reached(); 419 } 420 } 421 422 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 423 { 424 if (!ctx->cfg_ptr->ext_zfinx) { 425 return cpu_fpr[reg_num]; 426 } 427 428 if (reg_num == 0) { 429 return tcg_constant_i64(0); 430 } 431 switch (get_xl(ctx)) { 432 case MXL_RV32: 433 { 434 TCGv_i64 t = ftemp_new(ctx); 435 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 436 return t; 437 } 438 #ifdef TARGET_RISCV64 439 case MXL_RV64: 440 return cpu_gpr[reg_num]; 441 #endif 442 default: 443 g_assert_not_reached(); 444 } 445 } 446 447 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 448 { 449 if (!ctx->cfg_ptr->ext_zfinx) { 450 return cpu_fpr[reg_num]; 451 } 452 453 if (reg_num == 0) { 454 return ftemp_new(ctx); 455 } 456 457 switch (get_xl(ctx)) { 458 case MXL_RV32: 459 return ftemp_new(ctx); 460 #ifdef TARGET_RISCV64 461 case MXL_RV64: 462 return cpu_gpr[reg_num]; 463 #endif 464 default: 465 g_assert_not_reached(); 466 } 467 } 468 469 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 470 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 471 { 472 if (!ctx->cfg_ptr->ext_zfinx) { 473 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 474 return; 475 } 476 if (reg_num != 0) { 477 switch (get_xl(ctx)) { 478 case MXL_RV32: 479 #ifdef TARGET_RISCV32 480 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 481 break; 482 #else 483 /* fall through */ 484 case MXL_RV64: 485 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 486 break; 487 #endif 488 default: 489 g_assert_not_reached(); 490 } 491 } 492 } 493 494 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 495 { 496 if (!ctx->cfg_ptr->ext_zfinx) { 497 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 498 return; 499 } 500 501 if (reg_num != 0) { 502 switch (get_xl(ctx)) { 503 case MXL_RV32: 504 #ifdef TARGET_RISCV32 505 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 506 break; 507 #else 508 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 509 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 510 break; 511 case MXL_RV64: 512 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 513 break; 514 #endif 515 default: 516 g_assert_not_reached(); 517 } 518 } 519 } 520 521 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 522 { 523 target_ulong next_pc; 524 525 /* check misaligned: */ 526 next_pc = ctx->base.pc_next + imm; 527 if (!has_ext(ctx, RVC)) { 528 if ((next_pc & 0x3) != 0) { 529 gen_exception_inst_addr_mis(ctx); 530 return; 531 } 532 } 533 534 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 535 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 536 ctx->base.is_jmp = DISAS_NORETURN; 537 } 538 539 /* Compute a canonical address from a register plus offset. */ 540 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 541 { 542 TCGv addr = temp_new(ctx); 543 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 544 545 tcg_gen_addi_tl(addr, src1, imm); 546 if (ctx->pm_mask_enabled) { 547 tcg_gen_andc_tl(addr, addr, pm_mask); 548 } else if (get_xl(ctx) == MXL_RV32) { 549 tcg_gen_ext32u_tl(addr, addr); 550 } 551 if (ctx->pm_base_enabled) { 552 tcg_gen_or_tl(addr, addr, pm_base); 553 } 554 return addr; 555 } 556 557 #ifndef CONFIG_USER_ONLY 558 /* The states of mstatus_fs are: 559 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 560 * We will have already diagnosed disabled state, 561 * and need to turn initial/clean into dirty. 562 */ 563 static void mark_fs_dirty(DisasContext *ctx) 564 { 565 TCGv tmp; 566 567 if (!has_ext(ctx, RVF)) { 568 return; 569 } 570 571 if (ctx->mstatus_fs != MSTATUS_FS) { 572 /* Remember the state change for the rest of the TB. */ 573 ctx->mstatus_fs = MSTATUS_FS; 574 575 tmp = tcg_temp_new(); 576 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 577 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 578 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 579 tcg_temp_free(tmp); 580 } 581 582 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 583 /* Remember the stage change for the rest of the TB. */ 584 ctx->mstatus_hs_fs = MSTATUS_FS; 585 586 tmp = tcg_temp_new(); 587 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 588 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 589 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 590 tcg_temp_free(tmp); 591 } 592 } 593 #else 594 static inline void mark_fs_dirty(DisasContext *ctx) { } 595 #endif 596 597 #ifndef CONFIG_USER_ONLY 598 /* The states of mstatus_vs are: 599 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 600 * We will have already diagnosed disabled state, 601 * and need to turn initial/clean into dirty. 602 */ 603 static void mark_vs_dirty(DisasContext *ctx) 604 { 605 TCGv tmp; 606 607 if (ctx->mstatus_vs != MSTATUS_VS) { 608 /* Remember the state change for the rest of the TB. */ 609 ctx->mstatus_vs = MSTATUS_VS; 610 611 tmp = tcg_temp_new(); 612 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 613 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 614 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 615 tcg_temp_free(tmp); 616 } 617 618 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 619 /* Remember the stage change for the rest of the TB. */ 620 ctx->mstatus_hs_vs = MSTATUS_VS; 621 622 tmp = tcg_temp_new(); 623 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 624 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 625 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 626 tcg_temp_free(tmp); 627 } 628 } 629 #else 630 static inline void mark_vs_dirty(DisasContext *ctx) { } 631 #endif 632 633 static void gen_set_rm(DisasContext *ctx, int rm) 634 { 635 if (ctx->frm == rm) { 636 return; 637 } 638 ctx->frm = rm; 639 640 if (rm == RISCV_FRM_ROD) { 641 gen_helper_set_rod_rounding_mode(cpu_env); 642 return; 643 } 644 645 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 646 decode_save_opc(ctx); 647 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 648 } 649 650 static int ex_plus_1(DisasContext *ctx, int nf) 651 { 652 return nf + 1; 653 } 654 655 #define EX_SH(amount) \ 656 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 657 { \ 658 return imm << amount; \ 659 } 660 EX_SH(1) 661 EX_SH(2) 662 EX_SH(3) 663 EX_SH(4) 664 EX_SH(12) 665 666 #define REQUIRE_EXT(ctx, ext) do { \ 667 if (!has_ext(ctx, ext)) { \ 668 return false; \ 669 } \ 670 } while (0) 671 672 #define REQUIRE_32BIT(ctx) do { \ 673 if (get_xl(ctx) != MXL_RV32) { \ 674 return false; \ 675 } \ 676 } while (0) 677 678 #define REQUIRE_64BIT(ctx) do { \ 679 if (get_xl(ctx) != MXL_RV64) { \ 680 return false; \ 681 } \ 682 } while (0) 683 684 #define REQUIRE_128BIT(ctx) do { \ 685 if (get_xl(ctx) != MXL_RV128) { \ 686 return false; \ 687 } \ 688 } while (0) 689 690 #define REQUIRE_64_OR_128BIT(ctx) do { \ 691 if (get_xl(ctx) == MXL_RV32) { \ 692 return false; \ 693 } \ 694 } while (0) 695 696 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 697 if (!ctx->cfg_ptr->ext_##A && \ 698 !ctx->cfg_ptr->ext_##B) { \ 699 return false; \ 700 } \ 701 } while (0) 702 703 static int ex_rvc_register(DisasContext *ctx, int reg) 704 { 705 return 8 + reg; 706 } 707 708 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 709 { 710 /* For RV128 a shamt of 0 means a shift by 64. */ 711 if (get_ol(ctx) == MXL_RV128) { 712 imm = imm ? imm : 64; 713 } 714 return imm; 715 } 716 717 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 718 { 719 /* 720 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 721 * shifts, the shamt is sign-extended. 722 */ 723 if (get_ol(ctx) == MXL_RV128) { 724 imm = imm | (imm & 32) << 1; 725 imm = imm ? imm : 64; 726 } 727 return imm; 728 } 729 730 /* Include the auto-generated decoder for 32 bit insn */ 731 #include "decode-insn32.c.inc" 732 733 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 734 void (*func)(TCGv, TCGv, target_long)) 735 { 736 TCGv dest = dest_gpr(ctx, a->rd); 737 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 738 739 func(dest, src1, a->imm); 740 741 if (get_xl(ctx) == MXL_RV128) { 742 TCGv src1h = get_gprh(ctx, a->rs1); 743 TCGv desth = dest_gprh(ctx, a->rd); 744 745 func(desth, src1h, -(a->imm < 0)); 746 gen_set_gpr128(ctx, a->rd, dest, desth); 747 } else { 748 gen_set_gpr(ctx, a->rd, dest); 749 } 750 751 return true; 752 } 753 754 static bool gen_logic(DisasContext *ctx, arg_r *a, 755 void (*func)(TCGv, TCGv, TCGv)) 756 { 757 TCGv dest = dest_gpr(ctx, a->rd); 758 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 759 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 760 761 func(dest, src1, src2); 762 763 if (get_xl(ctx) == MXL_RV128) { 764 TCGv src1h = get_gprh(ctx, a->rs1); 765 TCGv src2h = get_gprh(ctx, a->rs2); 766 TCGv desth = dest_gprh(ctx, a->rd); 767 768 func(desth, src1h, src2h); 769 gen_set_gpr128(ctx, a->rd, dest, desth); 770 } else { 771 gen_set_gpr(ctx, a->rd, dest); 772 } 773 774 return true; 775 } 776 777 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 778 void (*func)(TCGv, TCGv, target_long), 779 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 780 { 781 TCGv dest = dest_gpr(ctx, a->rd); 782 TCGv src1 = get_gpr(ctx, a->rs1, ext); 783 784 if (get_ol(ctx) < MXL_RV128) { 785 func(dest, src1, a->imm); 786 gen_set_gpr(ctx, a->rd, dest); 787 } else { 788 if (f128 == NULL) { 789 return false; 790 } 791 792 TCGv src1h = get_gprh(ctx, a->rs1); 793 TCGv desth = dest_gprh(ctx, a->rd); 794 795 f128(dest, desth, src1, src1h, a->imm); 796 gen_set_gpr128(ctx, a->rd, dest, desth); 797 } 798 return true; 799 } 800 801 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 802 void (*func)(TCGv, TCGv, TCGv), 803 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 804 { 805 TCGv dest = dest_gpr(ctx, a->rd); 806 TCGv src1 = get_gpr(ctx, a->rs1, ext); 807 TCGv src2 = tcg_constant_tl(a->imm); 808 809 if (get_ol(ctx) < MXL_RV128) { 810 func(dest, src1, src2); 811 gen_set_gpr(ctx, a->rd, dest); 812 } else { 813 if (f128 == NULL) { 814 return false; 815 } 816 817 TCGv src1h = get_gprh(ctx, a->rs1); 818 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 819 TCGv desth = dest_gprh(ctx, a->rd); 820 821 f128(dest, desth, src1, src1h, src2, src2h); 822 gen_set_gpr128(ctx, a->rd, dest, desth); 823 } 824 return true; 825 } 826 827 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 828 void (*func)(TCGv, TCGv, TCGv), 829 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 830 { 831 TCGv dest = dest_gpr(ctx, a->rd); 832 TCGv src1 = get_gpr(ctx, a->rs1, ext); 833 TCGv src2 = get_gpr(ctx, a->rs2, ext); 834 835 if (get_ol(ctx) < MXL_RV128) { 836 func(dest, src1, src2); 837 gen_set_gpr(ctx, a->rd, dest); 838 } else { 839 if (f128 == NULL) { 840 return false; 841 } 842 843 TCGv src1h = get_gprh(ctx, a->rs1); 844 TCGv src2h = get_gprh(ctx, a->rs2); 845 TCGv desth = dest_gprh(ctx, a->rd); 846 847 f128(dest, desth, src1, src1h, src2, src2h); 848 gen_set_gpr128(ctx, a->rd, dest, desth); 849 } 850 return true; 851 } 852 853 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 854 void (*f_tl)(TCGv, TCGv, TCGv), 855 void (*f_32)(TCGv, TCGv, TCGv), 856 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 857 { 858 int olen = get_olen(ctx); 859 860 if (olen != TARGET_LONG_BITS) { 861 if (olen == 32) { 862 f_tl = f_32; 863 } else if (olen != 128) { 864 g_assert_not_reached(); 865 } 866 } 867 return gen_arith(ctx, a, ext, f_tl, f_128); 868 } 869 870 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 871 void (*func)(TCGv, TCGv, target_long), 872 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 873 { 874 TCGv dest, src1; 875 int max_len = get_olen(ctx); 876 877 if (a->shamt >= max_len) { 878 return false; 879 } 880 881 dest = dest_gpr(ctx, a->rd); 882 src1 = get_gpr(ctx, a->rs1, ext); 883 884 if (max_len < 128) { 885 func(dest, src1, a->shamt); 886 gen_set_gpr(ctx, a->rd, dest); 887 } else { 888 TCGv src1h = get_gprh(ctx, a->rs1); 889 TCGv desth = dest_gprh(ctx, a->rd); 890 891 if (f128 == NULL) { 892 return false; 893 } 894 f128(dest, desth, src1, src1h, a->shamt); 895 gen_set_gpr128(ctx, a->rd, dest, desth); 896 } 897 return true; 898 } 899 900 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 901 DisasExtend ext, 902 void (*f_tl)(TCGv, TCGv, target_long), 903 void (*f_32)(TCGv, TCGv, target_long), 904 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 905 target_long)) 906 { 907 int olen = get_olen(ctx); 908 if (olen != TARGET_LONG_BITS) { 909 if (olen == 32) { 910 f_tl = f_32; 911 } else if (olen != 128) { 912 g_assert_not_reached(); 913 } 914 } 915 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 916 } 917 918 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 919 void (*func)(TCGv, TCGv, TCGv)) 920 { 921 TCGv dest, src1, src2; 922 int max_len = get_olen(ctx); 923 924 if (a->shamt >= max_len) { 925 return false; 926 } 927 928 dest = dest_gpr(ctx, a->rd); 929 src1 = get_gpr(ctx, a->rs1, ext); 930 src2 = tcg_constant_tl(a->shamt); 931 932 func(dest, src1, src2); 933 934 gen_set_gpr(ctx, a->rd, dest); 935 return true; 936 } 937 938 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 939 void (*func)(TCGv, TCGv, TCGv), 940 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 941 { 942 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 943 TCGv ext2 = tcg_temp_new(); 944 int max_len = get_olen(ctx); 945 946 tcg_gen_andi_tl(ext2, src2, max_len - 1); 947 948 TCGv dest = dest_gpr(ctx, a->rd); 949 TCGv src1 = get_gpr(ctx, a->rs1, ext); 950 951 if (max_len < 128) { 952 func(dest, src1, ext2); 953 gen_set_gpr(ctx, a->rd, dest); 954 } else { 955 TCGv src1h = get_gprh(ctx, a->rs1); 956 TCGv desth = dest_gprh(ctx, a->rd); 957 958 if (f128 == NULL) { 959 return false; 960 } 961 f128(dest, desth, src1, src1h, ext2); 962 gen_set_gpr128(ctx, a->rd, dest, desth); 963 } 964 tcg_temp_free(ext2); 965 return true; 966 } 967 968 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 969 void (*f_tl)(TCGv, TCGv, TCGv), 970 void (*f_32)(TCGv, TCGv, TCGv), 971 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 972 { 973 int olen = get_olen(ctx); 974 if (olen != TARGET_LONG_BITS) { 975 if (olen == 32) { 976 f_tl = f_32; 977 } else if (olen != 128) { 978 g_assert_not_reached(); 979 } 980 } 981 return gen_shift(ctx, a, ext, f_tl, f_128); 982 } 983 984 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 985 void (*func)(TCGv, TCGv)) 986 { 987 TCGv dest = dest_gpr(ctx, a->rd); 988 TCGv src1 = get_gpr(ctx, a->rs1, ext); 989 990 func(dest, src1); 991 992 gen_set_gpr(ctx, a->rd, dest); 993 return true; 994 } 995 996 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 997 void (*f_tl)(TCGv, TCGv), 998 void (*f_32)(TCGv, TCGv)) 999 { 1000 int olen = get_olen(ctx); 1001 1002 if (olen != TARGET_LONG_BITS) { 1003 if (olen == 32) { 1004 f_tl = f_32; 1005 } else { 1006 g_assert_not_reached(); 1007 } 1008 } 1009 return gen_unary(ctx, a, ext, f_tl); 1010 } 1011 1012 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1013 { 1014 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1015 CPUState *cpu = ctx->cs; 1016 CPURISCVState *env = cpu->env_ptr; 1017 1018 return cpu_ldl_code(env, pc); 1019 } 1020 1021 /* Include insn module translation function */ 1022 #include "insn_trans/trans_rvi.c.inc" 1023 #include "insn_trans/trans_rvm.c.inc" 1024 #include "insn_trans/trans_rva.c.inc" 1025 #include "insn_trans/trans_rvf.c.inc" 1026 #include "insn_trans/trans_rvd.c.inc" 1027 #include "insn_trans/trans_rvh.c.inc" 1028 #include "insn_trans/trans_rvv.c.inc" 1029 #include "insn_trans/trans_rvb.c.inc" 1030 #include "insn_trans/trans_rvzfh.c.inc" 1031 #include "insn_trans/trans_rvk.c.inc" 1032 #include "insn_trans/trans_privileged.c.inc" 1033 #include "insn_trans/trans_svinval.c.inc" 1034 #include "insn_trans/trans_xventanacondops.c.inc" 1035 1036 /* Include the auto-generated decoder for 16 bit insn */ 1037 #include "decode-insn16.c.inc" 1038 /* Include decoders for factored-out extensions */ 1039 #include "decode-XVentanaCondOps.c.inc" 1040 1041 /* The specification allows for longer insns, but not supported by qemu. */ 1042 #define MAX_INSN_LEN 4 1043 1044 static inline int insn_len(uint16_t first_word) 1045 { 1046 return (first_word & 3) == 3 ? 4 : 2; 1047 } 1048 1049 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1050 { 1051 /* 1052 * A table with predicate (i.e., guard) functions and decoder functions 1053 * that are tested in-order until a decoder matches onto the opcode. 1054 */ 1055 static const struct { 1056 bool (*guard_func)(DisasContext *); 1057 bool (*decode_func)(DisasContext *, uint32_t); 1058 } decoders[] = { 1059 { always_true_p, decode_insn32 }, 1060 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1061 }; 1062 1063 /* Check for compressed insn */ 1064 if (insn_len(opcode) == 2) { 1065 if (!has_ext(ctx, RVC)) { 1066 gen_exception_illegal(ctx); 1067 } else { 1068 ctx->opcode = opcode; 1069 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1070 if (decode_insn16(ctx, opcode)) { 1071 return; 1072 } 1073 } 1074 } else { 1075 uint32_t opcode32 = opcode; 1076 opcode32 = deposit32(opcode32, 16, 16, 1077 translator_lduw(env, &ctx->base, 1078 ctx->base.pc_next + 2)); 1079 ctx->opcode = opcode32; 1080 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1081 1082 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1083 if (decoders[i].guard_func(ctx) && 1084 decoders[i].decode_func(ctx, opcode32)) { 1085 return; 1086 } 1087 } 1088 } 1089 1090 gen_exception_illegal(ctx); 1091 } 1092 1093 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1094 { 1095 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1096 CPURISCVState *env = cs->env_ptr; 1097 RISCVCPU *cpu = RISCV_CPU(cs); 1098 uint32_t tb_flags = ctx->base.tb->flags; 1099 1100 ctx->pc_succ_insn = ctx->base.pc_first; 1101 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1102 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1103 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1104 ctx->priv_ver = env->priv_ver; 1105 #if !defined(CONFIG_USER_ONLY) 1106 if (riscv_has_ext(env, RVH)) { 1107 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1108 } else { 1109 ctx->virt_enabled = false; 1110 } 1111 #else 1112 ctx->virt_enabled = false; 1113 #endif 1114 ctx->misa_ext = env->misa_ext; 1115 ctx->frm = -1; /* unknown rounding mode */ 1116 ctx->cfg_ptr = &(cpu->cfg); 1117 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1118 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1119 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1120 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1121 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1122 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1123 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1124 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1125 ctx->vstart = env->vstart; 1126 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1127 ctx->misa_mxl_max = env->misa_mxl_max; 1128 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1129 ctx->cs = cs; 1130 ctx->ntemp = 0; 1131 memset(ctx->temp, 0, sizeof(ctx->temp)); 1132 ctx->nftemp = 0; 1133 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1134 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1135 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1136 ctx->zero = tcg_constant_tl(0); 1137 } 1138 1139 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1140 { 1141 } 1142 1143 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1144 { 1145 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1146 1147 tcg_gen_insn_start(ctx->base.pc_next, 0); 1148 ctx->insn_start = tcg_last_op(); 1149 } 1150 1151 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1152 { 1153 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1154 CPURISCVState *env = cpu->env_ptr; 1155 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1156 int i; 1157 1158 ctx->ol = ctx->xl; 1159 decode_opc(env, ctx, opcode16); 1160 ctx->base.pc_next = ctx->pc_succ_insn; 1161 1162 for (i = ctx->ntemp - 1; i >= 0; --i) { 1163 tcg_temp_free(ctx->temp[i]); 1164 ctx->temp[i] = NULL; 1165 } 1166 ctx->ntemp = 0; 1167 for (i = ctx->nftemp - 1; i >= 0; --i) { 1168 tcg_temp_free_i64(ctx->ftemp[i]); 1169 ctx->ftemp[i] = NULL; 1170 } 1171 ctx->nftemp = 0; 1172 1173 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1174 if (ctx->base.is_jmp == DISAS_NEXT) { 1175 if (!is_same_page(&ctx->base, ctx->base.pc_next)) { 1176 ctx->base.is_jmp = DISAS_TOO_MANY; 1177 } else { 1178 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1179 1180 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1181 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1182 int len = insn_len(next_insn); 1183 1184 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1185 ctx->base.is_jmp = DISAS_TOO_MANY; 1186 } 1187 } 1188 } 1189 } 1190 } 1191 1192 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1193 { 1194 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1195 1196 switch (ctx->base.is_jmp) { 1197 case DISAS_TOO_MANY: 1198 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1199 break; 1200 case DISAS_NORETURN: 1201 break; 1202 default: 1203 g_assert_not_reached(); 1204 } 1205 } 1206 1207 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1208 CPUState *cpu, FILE *logfile) 1209 { 1210 #ifndef CONFIG_USER_ONLY 1211 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1212 CPURISCVState *env = &rvcpu->env; 1213 #endif 1214 1215 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1216 #ifndef CONFIG_USER_ONLY 1217 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1218 env->priv, env->virt); 1219 #endif 1220 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1221 } 1222 1223 static const TranslatorOps riscv_tr_ops = { 1224 .init_disas_context = riscv_tr_init_disas_context, 1225 .tb_start = riscv_tr_tb_start, 1226 .insn_start = riscv_tr_insn_start, 1227 .translate_insn = riscv_tr_translate_insn, 1228 .tb_stop = riscv_tr_tb_stop, 1229 .disas_log = riscv_tr_disas_log, 1230 }; 1231 1232 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1233 target_ulong pc, void *host_pc) 1234 { 1235 DisasContext ctx; 1236 1237 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1238 } 1239 1240 void riscv_translate_init(void) 1241 { 1242 int i; 1243 1244 /* 1245 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1246 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1247 * unless you specifically block reads/writes to reg 0. 1248 */ 1249 cpu_gpr[0] = NULL; 1250 cpu_gprh[0] = NULL; 1251 1252 for (i = 1; i < 32; i++) { 1253 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1254 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1255 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1256 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1257 } 1258 1259 for (i = 0; i < 32; i++) { 1260 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1261 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1262 } 1263 1264 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1265 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1266 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1267 "vstart"); 1268 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1269 "load_res"); 1270 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1271 "load_val"); 1272 /* Assign PM CSRs to tcg globals */ 1273 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1274 "pmmask"); 1275 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1276 "pmbase"); 1277 } 1278