1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 34 /* global register indices */ 35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl; 36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 37 static TCGv load_res; 38 static TCGv load_val; 39 40 #include "exec/gen-icount.h" 41 42 typedef struct DisasContext { 43 DisasContextBase base; 44 /* pc_succ_insn points to the instruction following base.pc_next */ 45 target_ulong pc_succ_insn; 46 target_ulong priv_ver; 47 bool virt_enabled; 48 uint32_t opcode; 49 uint32_t mstatus_fs; 50 uint32_t misa; 51 uint32_t mem_idx; 52 /* Remember the rounding mode encoded in the previous fp instruction, 53 which we have already installed into env->fp_status. Or -1 for 54 no previous fp instruction. Note that we exit the TB when writing 55 to any system register, which includes CSR_FRM, so we do not have 56 to reset this known value. */ 57 int frm; 58 bool ext_ifencei; 59 /* vector extension */ 60 bool vill; 61 uint8_t lmul; 62 uint8_t sew; 63 uint16_t vlen; 64 uint16_t mlen; 65 bool vl_eq_vlmax; 66 } DisasContext; 67 68 #ifdef TARGET_RISCV64 69 /* convert riscv funct3 to qemu memop for load/store */ 70 static const int tcg_memop_lookup[8] = { 71 [0 ... 7] = -1, 72 [0] = MO_SB, 73 [1] = MO_TESW, 74 [2] = MO_TESL, 75 [3] = MO_TEQ, 76 [4] = MO_UB, 77 [5] = MO_TEUW, 78 [6] = MO_TEUL, 79 }; 80 #endif 81 82 #ifdef TARGET_RISCV64 83 #define CASE_OP_32_64(X) case X: case glue(X, W) 84 #else 85 #define CASE_OP_32_64(X) case X 86 #endif 87 88 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 89 { 90 return ctx->misa & ext; 91 } 92 93 /* 94 * RISC-V requires NaN-boxing of narrower width floating point values. 95 * This applies when a 32-bit value is assigned to a 64-bit FP register. 96 * For consistency and simplicity, we nanbox results even when the RVD 97 * extension is not present. 98 */ 99 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 100 { 101 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 102 } 103 104 static void generate_exception(DisasContext *ctx, int excp) 105 { 106 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 107 TCGv_i32 helper_tmp = tcg_const_i32(excp); 108 gen_helper_raise_exception(cpu_env, helper_tmp); 109 tcg_temp_free_i32(helper_tmp); 110 ctx->base.is_jmp = DISAS_NORETURN; 111 } 112 113 static void generate_exception_mbadaddr(DisasContext *ctx, int excp) 114 { 115 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 116 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 117 TCGv_i32 helper_tmp = tcg_const_i32(excp); 118 gen_helper_raise_exception(cpu_env, helper_tmp); 119 tcg_temp_free_i32(helper_tmp); 120 ctx->base.is_jmp = DISAS_NORETURN; 121 } 122 123 static void gen_exception_debug(void) 124 { 125 TCGv_i32 helper_tmp = tcg_const_i32(EXCP_DEBUG); 126 gen_helper_raise_exception(cpu_env, helper_tmp); 127 tcg_temp_free_i32(helper_tmp); 128 } 129 130 /* Wrapper around tcg_gen_exit_tb that handles single stepping */ 131 static void exit_tb(DisasContext *ctx) 132 { 133 if (ctx->base.singlestep_enabled) { 134 gen_exception_debug(); 135 } else { 136 tcg_gen_exit_tb(NULL, 0); 137 } 138 } 139 140 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ 141 static void lookup_and_goto_ptr(DisasContext *ctx) 142 { 143 if (ctx->base.singlestep_enabled) { 144 gen_exception_debug(); 145 } else { 146 tcg_gen_lookup_and_goto_ptr(); 147 } 148 } 149 150 static void gen_exception_illegal(DisasContext *ctx) 151 { 152 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 153 } 154 155 static void gen_exception_inst_addr_mis(DisasContext *ctx) 156 { 157 generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); 158 } 159 160 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) 161 { 162 if (unlikely(ctx->base.singlestep_enabled)) { 163 return false; 164 } 165 166 #ifndef CONFIG_USER_ONLY 167 return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 168 #else 169 return true; 170 #endif 171 } 172 173 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 174 { 175 if (use_goto_tb(ctx, dest)) { 176 /* chaining is only allowed when the jump is to the same page */ 177 tcg_gen_goto_tb(n); 178 tcg_gen_movi_tl(cpu_pc, dest); 179 180 /* No need to check for single stepping here as use_goto_tb() will 181 * return false in case of single stepping. 182 */ 183 tcg_gen_exit_tb(ctx->base.tb, n); 184 } else { 185 tcg_gen_movi_tl(cpu_pc, dest); 186 lookup_and_goto_ptr(ctx); 187 } 188 } 189 190 /* Wrapper for getting reg values - need to check of reg is zero since 191 * cpu_gpr[0] is not actually allocated 192 */ 193 static inline void gen_get_gpr(TCGv t, int reg_num) 194 { 195 if (reg_num == 0) { 196 tcg_gen_movi_tl(t, 0); 197 } else { 198 tcg_gen_mov_tl(t, cpu_gpr[reg_num]); 199 } 200 } 201 202 /* Wrapper for setting reg values - need to check of reg is zero since 203 * cpu_gpr[0] is not actually allocated. this is more for safety purposes, 204 * since we usually avoid calling the OP_TYPE_gen function if we see a write to 205 * $zero 206 */ 207 static inline void gen_set_gpr(int reg_num_dst, TCGv t) 208 { 209 if (reg_num_dst != 0) { 210 tcg_gen_mov_tl(cpu_gpr[reg_num_dst], t); 211 } 212 } 213 214 static void gen_mulhsu(TCGv ret, TCGv arg1, TCGv arg2) 215 { 216 TCGv rl = tcg_temp_new(); 217 TCGv rh = tcg_temp_new(); 218 219 tcg_gen_mulu2_tl(rl, rh, arg1, arg2); 220 /* fix up for one negative */ 221 tcg_gen_sari_tl(rl, arg1, TARGET_LONG_BITS - 1); 222 tcg_gen_and_tl(rl, rl, arg2); 223 tcg_gen_sub_tl(ret, rh, rl); 224 225 tcg_temp_free(rl); 226 tcg_temp_free(rh); 227 } 228 229 static void gen_div(TCGv ret, TCGv source1, TCGv source2) 230 { 231 TCGv cond1, cond2, zeroreg, resultopt1; 232 /* 233 * Handle by altering args to tcg_gen_div to produce req'd results: 234 * For overflow: want source1 in source1 and 1 in source2 235 * For div by zero: want -1 in source1 and 1 in source2 -> -1 result 236 */ 237 cond1 = tcg_temp_new(); 238 cond2 = tcg_temp_new(); 239 zeroreg = tcg_const_tl(0); 240 resultopt1 = tcg_temp_new(); 241 242 tcg_gen_movi_tl(resultopt1, (target_ulong)-1); 243 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); 244 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, 245 ((target_ulong)1) << (TARGET_LONG_BITS - 1)); 246 tcg_gen_and_tl(cond1, cond1, cond2); /* cond1 = overflow */ 247 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ 248 /* if div by zero, set source1 to -1, otherwise don't change */ 249 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond2, zeroreg, source1, 250 resultopt1); 251 /* if overflow or div by zero, set source2 to 1, else don't change */ 252 tcg_gen_or_tl(cond1, cond1, cond2); 253 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 254 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 255 resultopt1); 256 tcg_gen_div_tl(ret, source1, source2); 257 258 tcg_temp_free(cond1); 259 tcg_temp_free(cond2); 260 tcg_temp_free(zeroreg); 261 tcg_temp_free(resultopt1); 262 } 263 264 static void gen_divu(TCGv ret, TCGv source1, TCGv source2) 265 { 266 TCGv cond1, zeroreg, resultopt1; 267 cond1 = tcg_temp_new(); 268 269 zeroreg = tcg_const_tl(0); 270 resultopt1 = tcg_temp_new(); 271 272 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); 273 tcg_gen_movi_tl(resultopt1, (target_ulong)-1); 274 tcg_gen_movcond_tl(TCG_COND_EQ, source1, cond1, zeroreg, source1, 275 resultopt1); 276 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 277 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 278 resultopt1); 279 tcg_gen_divu_tl(ret, source1, source2); 280 281 tcg_temp_free(cond1); 282 tcg_temp_free(zeroreg); 283 tcg_temp_free(resultopt1); 284 } 285 286 static void gen_rem(TCGv ret, TCGv source1, TCGv source2) 287 { 288 TCGv cond1, cond2, zeroreg, resultopt1; 289 290 cond1 = tcg_temp_new(); 291 cond2 = tcg_temp_new(); 292 zeroreg = tcg_const_tl(0); 293 resultopt1 = tcg_temp_new(); 294 295 tcg_gen_movi_tl(resultopt1, 1L); 296 tcg_gen_setcondi_tl(TCG_COND_EQ, cond2, source2, (target_ulong)-1); 297 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source1, 298 (target_ulong)1 << (TARGET_LONG_BITS - 1)); 299 tcg_gen_and_tl(cond2, cond1, cond2); /* cond1 = overflow */ 300 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ 301 /* if overflow or div by zero, set source2 to 1, else don't change */ 302 tcg_gen_or_tl(cond2, cond1, cond2); 303 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond2, zeroreg, source2, 304 resultopt1); 305 tcg_gen_rem_tl(resultopt1, source1, source2); 306 /* if div by zero, just return the original dividend */ 307 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, 308 source1); 309 310 tcg_temp_free(cond1); 311 tcg_temp_free(cond2); 312 tcg_temp_free(zeroreg); 313 tcg_temp_free(resultopt1); 314 } 315 316 static void gen_remu(TCGv ret, TCGv source1, TCGv source2) 317 { 318 TCGv cond1, zeroreg, resultopt1; 319 cond1 = tcg_temp_new(); 320 zeroreg = tcg_const_tl(0); 321 resultopt1 = tcg_temp_new(); 322 323 tcg_gen_movi_tl(resultopt1, (target_ulong)1); 324 tcg_gen_setcondi_tl(TCG_COND_EQ, cond1, source2, 0); 325 tcg_gen_movcond_tl(TCG_COND_EQ, source2, cond1, zeroreg, source2, 326 resultopt1); 327 tcg_gen_remu_tl(resultopt1, source1, source2); 328 /* if div by zero, just return the original dividend */ 329 tcg_gen_movcond_tl(TCG_COND_EQ, ret, cond1, zeroreg, resultopt1, 330 source1); 331 332 tcg_temp_free(cond1); 333 tcg_temp_free(zeroreg); 334 tcg_temp_free(resultopt1); 335 } 336 337 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 338 { 339 target_ulong next_pc; 340 341 /* check misaligned: */ 342 next_pc = ctx->base.pc_next + imm; 343 if (!has_ext(ctx, RVC)) { 344 if ((next_pc & 0x3) != 0) { 345 gen_exception_inst_addr_mis(ctx); 346 return; 347 } 348 } 349 if (rd != 0) { 350 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 351 } 352 353 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 354 ctx->base.is_jmp = DISAS_NORETURN; 355 } 356 357 #ifdef TARGET_RISCV64 358 static void gen_load_c(DisasContext *ctx, uint32_t opc, int rd, int rs1, 359 target_long imm) 360 { 361 TCGv t0 = tcg_temp_new(); 362 TCGv t1 = tcg_temp_new(); 363 gen_get_gpr(t0, rs1); 364 tcg_gen_addi_tl(t0, t0, imm); 365 int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; 366 367 if (memop < 0) { 368 gen_exception_illegal(ctx); 369 return; 370 } 371 372 tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, memop); 373 gen_set_gpr(rd, t1); 374 tcg_temp_free(t0); 375 tcg_temp_free(t1); 376 } 377 378 static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2, 379 target_long imm) 380 { 381 TCGv t0 = tcg_temp_new(); 382 TCGv dat = tcg_temp_new(); 383 gen_get_gpr(t0, rs1); 384 tcg_gen_addi_tl(t0, t0, imm); 385 gen_get_gpr(dat, rs2); 386 int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; 387 388 if (memop < 0) { 389 gen_exception_illegal(ctx); 390 return; 391 } 392 393 tcg_gen_qemu_st_tl(dat, t0, ctx->mem_idx, memop); 394 tcg_temp_free(t0); 395 tcg_temp_free(dat); 396 } 397 #endif 398 399 #ifndef CONFIG_USER_ONLY 400 /* The states of mstatus_fs are: 401 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 402 * We will have already diagnosed disabled state, 403 * and need to turn initial/clean into dirty. 404 */ 405 static void mark_fs_dirty(DisasContext *ctx) 406 { 407 TCGv tmp; 408 if (ctx->mstatus_fs == MSTATUS_FS) { 409 return; 410 } 411 /* Remember the state change for the rest of the TB. */ 412 ctx->mstatus_fs = MSTATUS_FS; 413 414 tmp = tcg_temp_new(); 415 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 416 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); 417 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 418 419 if (ctx->virt_enabled) { 420 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 421 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD); 422 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 423 } 424 tcg_temp_free(tmp); 425 } 426 #else 427 static inline void mark_fs_dirty(DisasContext *ctx) { } 428 #endif 429 430 #if !defined(TARGET_RISCV64) 431 static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, 432 int rs1, target_long imm) 433 { 434 TCGv t0; 435 436 if (ctx->mstatus_fs == 0) { 437 gen_exception_illegal(ctx); 438 return; 439 } 440 441 t0 = tcg_temp_new(); 442 gen_get_gpr(t0, rs1); 443 tcg_gen_addi_tl(t0, t0, imm); 444 445 switch (opc) { 446 case OPC_RISC_FLW: 447 if (!has_ext(ctx, RVF)) { 448 goto do_illegal; 449 } 450 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); 451 /* RISC-V requires NaN-boxing of narrower width floating point values */ 452 tcg_gen_ori_i64(cpu_fpr[rd], cpu_fpr[rd], 0xffffffff00000000ULL); 453 break; 454 case OPC_RISC_FLD: 455 if (!has_ext(ctx, RVD)) { 456 goto do_illegal; 457 } 458 tcg_gen_qemu_ld_i64(cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); 459 break; 460 do_illegal: 461 default: 462 gen_exception_illegal(ctx); 463 break; 464 } 465 tcg_temp_free(t0); 466 467 mark_fs_dirty(ctx); 468 } 469 470 static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, 471 int rs2, target_long imm) 472 { 473 TCGv t0; 474 475 if (ctx->mstatus_fs == 0) { 476 gen_exception_illegal(ctx); 477 return; 478 } 479 480 t0 = tcg_temp_new(); 481 gen_get_gpr(t0, rs1); 482 tcg_gen_addi_tl(t0, t0, imm); 483 484 switch (opc) { 485 case OPC_RISC_FSW: 486 if (!has_ext(ctx, RVF)) { 487 goto do_illegal; 488 } 489 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); 490 break; 491 case OPC_RISC_FSD: 492 if (!has_ext(ctx, RVD)) { 493 goto do_illegal; 494 } 495 tcg_gen_qemu_st_i64(cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); 496 break; 497 do_illegal: 498 default: 499 gen_exception_illegal(ctx); 500 break; 501 } 502 503 tcg_temp_free(t0); 504 } 505 #endif 506 507 static void gen_set_rm(DisasContext *ctx, int rm) 508 { 509 TCGv_i32 t0; 510 511 if (ctx->frm == rm) { 512 return; 513 } 514 ctx->frm = rm; 515 t0 = tcg_const_i32(rm); 516 gen_helper_set_rounding_mode(cpu_env, t0); 517 tcg_temp_free_i32(t0); 518 } 519 520 static void decode_RV32_64C0(DisasContext *ctx, uint16_t opcode) 521 { 522 uint8_t funct3 = extract16(opcode, 13, 3); 523 uint8_t rd_rs2 = GET_C_RS2S(opcode); 524 uint8_t rs1s = GET_C_RS1S(opcode); 525 526 switch (funct3) { 527 case 3: 528 #if defined(TARGET_RISCV64) 529 /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ 530 gen_load_c(ctx, OPC_RISC_LD, rd_rs2, rs1s, 531 GET_C_LD_IMM(opcode)); 532 #else 533 /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ 534 gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, 535 GET_C_LW_IMM(opcode)); 536 #endif 537 break; 538 case 7: 539 #if defined(TARGET_RISCV64) 540 /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ 541 gen_store_c(ctx, OPC_RISC_SD, rs1s, rd_rs2, 542 GET_C_LD_IMM(opcode)); 543 #else 544 /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ 545 gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, 546 GET_C_LW_IMM(opcode)); 547 #endif 548 break; 549 } 550 } 551 552 static void decode_RV32_64C(DisasContext *ctx, uint16_t opcode) 553 { 554 uint8_t op = extract16(opcode, 0, 2); 555 556 switch (op) { 557 case 0: 558 decode_RV32_64C0(ctx, opcode); 559 break; 560 } 561 } 562 563 static int ex_plus_1(DisasContext *ctx, int nf) 564 { 565 return nf + 1; 566 } 567 568 #define EX_SH(amount) \ 569 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 570 { \ 571 return imm << amount; \ 572 } 573 EX_SH(1) 574 EX_SH(2) 575 EX_SH(3) 576 EX_SH(4) 577 EX_SH(12) 578 579 #define REQUIRE_EXT(ctx, ext) do { \ 580 if (!has_ext(ctx, ext)) { \ 581 return false; \ 582 } \ 583 } while (0) 584 585 static int ex_rvc_register(DisasContext *ctx, int reg) 586 { 587 return 8 + reg; 588 } 589 590 static int ex_rvc_shifti(DisasContext *ctx, int imm) 591 { 592 /* For RV128 a shamt of 0 means a shift by 64. */ 593 return imm ? imm : 64; 594 } 595 596 /* Include the auto-generated decoder for 32 bit insn */ 597 #include "decode-insn32.c.inc" 598 599 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, 600 void (*func)(TCGv, TCGv, target_long)) 601 { 602 TCGv source1; 603 source1 = tcg_temp_new(); 604 605 gen_get_gpr(source1, a->rs1); 606 607 (*func)(source1, source1, a->imm); 608 609 gen_set_gpr(a->rd, source1); 610 tcg_temp_free(source1); 611 return true; 612 } 613 614 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, 615 void (*func)(TCGv, TCGv, TCGv)) 616 { 617 TCGv source1, source2; 618 source1 = tcg_temp_new(); 619 source2 = tcg_temp_new(); 620 621 gen_get_gpr(source1, a->rs1); 622 tcg_gen_movi_tl(source2, a->imm); 623 624 (*func)(source1, source1, source2); 625 626 gen_set_gpr(a->rd, source1); 627 tcg_temp_free(source1); 628 tcg_temp_free(source2); 629 return true; 630 } 631 632 #ifdef TARGET_RISCV64 633 static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) 634 { 635 tcg_gen_add_tl(ret, arg1, arg2); 636 tcg_gen_ext32s_tl(ret, ret); 637 } 638 639 static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) 640 { 641 tcg_gen_sub_tl(ret, arg1, arg2); 642 tcg_gen_ext32s_tl(ret, ret); 643 } 644 645 static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) 646 { 647 tcg_gen_mul_tl(ret, arg1, arg2); 648 tcg_gen_ext32s_tl(ret, ret); 649 } 650 651 static bool gen_arith_div_w(DisasContext *ctx, arg_r *a, 652 void(*func)(TCGv, TCGv, TCGv)) 653 { 654 TCGv source1, source2; 655 source1 = tcg_temp_new(); 656 source2 = tcg_temp_new(); 657 658 gen_get_gpr(source1, a->rs1); 659 gen_get_gpr(source2, a->rs2); 660 tcg_gen_ext32s_tl(source1, source1); 661 tcg_gen_ext32s_tl(source2, source2); 662 663 (*func)(source1, source1, source2); 664 665 tcg_gen_ext32s_tl(source1, source1); 666 gen_set_gpr(a->rd, source1); 667 tcg_temp_free(source1); 668 tcg_temp_free(source2); 669 return true; 670 } 671 672 static bool gen_arith_div_uw(DisasContext *ctx, arg_r *a, 673 void(*func)(TCGv, TCGv, TCGv)) 674 { 675 TCGv source1, source2; 676 source1 = tcg_temp_new(); 677 source2 = tcg_temp_new(); 678 679 gen_get_gpr(source1, a->rs1); 680 gen_get_gpr(source2, a->rs2); 681 tcg_gen_ext32u_tl(source1, source1); 682 tcg_gen_ext32u_tl(source2, source2); 683 684 (*func)(source1, source1, source2); 685 686 tcg_gen_ext32s_tl(source1, source1); 687 gen_set_gpr(a->rd, source1); 688 tcg_temp_free(source1); 689 tcg_temp_free(source2); 690 return true; 691 } 692 693 #endif 694 695 static bool gen_arith(DisasContext *ctx, arg_r *a, 696 void(*func)(TCGv, TCGv, TCGv)) 697 { 698 TCGv source1, source2; 699 source1 = tcg_temp_new(); 700 source2 = tcg_temp_new(); 701 702 gen_get_gpr(source1, a->rs1); 703 gen_get_gpr(source2, a->rs2); 704 705 (*func)(source1, source1, source2); 706 707 gen_set_gpr(a->rd, source1); 708 tcg_temp_free(source1); 709 tcg_temp_free(source2); 710 return true; 711 } 712 713 static bool gen_shift(DisasContext *ctx, arg_r *a, 714 void(*func)(TCGv, TCGv, TCGv)) 715 { 716 TCGv source1 = tcg_temp_new(); 717 TCGv source2 = tcg_temp_new(); 718 719 gen_get_gpr(source1, a->rs1); 720 gen_get_gpr(source2, a->rs2); 721 722 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); 723 (*func)(source1, source1, source2); 724 725 gen_set_gpr(a->rd, source1); 726 tcg_temp_free(source1); 727 tcg_temp_free(source2); 728 return true; 729 } 730 731 /* Include insn module translation function */ 732 #include "insn_trans/trans_rvi.c.inc" 733 #include "insn_trans/trans_rvm.c.inc" 734 #include "insn_trans/trans_rva.c.inc" 735 #include "insn_trans/trans_rvf.c.inc" 736 #include "insn_trans/trans_rvd.c.inc" 737 #include "insn_trans/trans_rvh.c.inc" 738 #include "insn_trans/trans_rvv.c.inc" 739 #include "insn_trans/trans_privileged.c.inc" 740 741 /* Include the auto-generated decoder for 16 bit insn */ 742 #include "decode-insn16.c.inc" 743 744 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 745 { 746 /* check for compressed insn */ 747 if (extract16(opcode, 0, 2) != 3) { 748 if (!has_ext(ctx, RVC)) { 749 gen_exception_illegal(ctx); 750 } else { 751 ctx->pc_succ_insn = ctx->base.pc_next + 2; 752 if (!decode_insn16(ctx, opcode)) { 753 /* fall back to old decoder */ 754 decode_RV32_64C(ctx, opcode); 755 } 756 } 757 } else { 758 uint32_t opcode32 = opcode; 759 opcode32 = deposit32(opcode32, 16, 16, 760 translator_lduw(env, ctx->base.pc_next + 2)); 761 ctx->pc_succ_insn = ctx->base.pc_next + 4; 762 if (!decode_insn32(ctx, opcode32)) { 763 gen_exception_illegal(ctx); 764 } 765 } 766 } 767 768 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 769 { 770 DisasContext *ctx = container_of(dcbase, DisasContext, base); 771 CPURISCVState *env = cs->env_ptr; 772 RISCVCPU *cpu = RISCV_CPU(cs); 773 uint32_t tb_flags = ctx->base.tb->flags; 774 775 ctx->pc_succ_insn = ctx->base.pc_first; 776 ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; 777 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 778 ctx->priv_ver = env->priv_ver; 779 #if !defined(CONFIG_USER_ONLY) 780 if (riscv_has_ext(env, RVH)) { 781 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 782 if (env->priv_ver == PRV_M && 783 get_field(env->mstatus, MSTATUS_MPRV) && 784 MSTATUS_MPV_ISSET(env)) { 785 ctx->virt_enabled = true; 786 } else if (env->priv == PRV_S && 787 !riscv_cpu_virt_enabled(env) && 788 get_field(env->hstatus, HSTATUS_SPRV) && 789 get_field(env->hstatus, HSTATUS_SPV)) { 790 ctx->virt_enabled = true; 791 } 792 } else { 793 ctx->virt_enabled = false; 794 } 795 #else 796 ctx->virt_enabled = false; 797 #endif 798 ctx->misa = env->misa; 799 ctx->frm = -1; /* unknown rounding mode */ 800 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 801 ctx->vlen = cpu->cfg.vlen; 802 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 803 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 804 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); 805 ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); 806 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 807 } 808 809 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 810 { 811 } 812 813 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 814 { 815 DisasContext *ctx = container_of(dcbase, DisasContext, base); 816 817 tcg_gen_insn_start(ctx->base.pc_next); 818 } 819 820 static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, 821 const CPUBreakpoint *bp) 822 { 823 DisasContext *ctx = container_of(dcbase, DisasContext, base); 824 825 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 826 ctx->base.is_jmp = DISAS_NORETURN; 827 gen_exception_debug(); 828 /* The address covered by the breakpoint must be included in 829 [tb->pc, tb->pc + tb->size) in order to for it to be 830 properly cleared -- thus we increment the PC here so that 831 the logic setting tb->size below does the right thing. */ 832 ctx->base.pc_next += 4; 833 return true; 834 } 835 836 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 837 { 838 DisasContext *ctx = container_of(dcbase, DisasContext, base); 839 CPURISCVState *env = cpu->env_ptr; 840 uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); 841 842 decode_opc(env, ctx, opcode16); 843 ctx->base.pc_next = ctx->pc_succ_insn; 844 845 if (ctx->base.is_jmp == DISAS_NEXT) { 846 target_ulong page_start; 847 848 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 849 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 850 ctx->base.is_jmp = DISAS_TOO_MANY; 851 } 852 } 853 } 854 855 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 856 { 857 DisasContext *ctx = container_of(dcbase, DisasContext, base); 858 859 switch (ctx->base.is_jmp) { 860 case DISAS_TOO_MANY: 861 gen_goto_tb(ctx, 0, ctx->base.pc_next); 862 break; 863 case DISAS_NORETURN: 864 break; 865 default: 866 g_assert_not_reached(); 867 } 868 } 869 870 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 871 { 872 #ifndef CONFIG_USER_ONLY 873 RISCVCPU *rvcpu = RISCV_CPU(cpu); 874 CPURISCVState *env = &rvcpu->env; 875 #endif 876 877 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 878 #ifndef CONFIG_USER_ONLY 879 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 880 #endif 881 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 882 } 883 884 static const TranslatorOps riscv_tr_ops = { 885 .init_disas_context = riscv_tr_init_disas_context, 886 .tb_start = riscv_tr_tb_start, 887 .insn_start = riscv_tr_insn_start, 888 .breakpoint_check = riscv_tr_breakpoint_check, 889 .translate_insn = riscv_tr_translate_insn, 890 .tb_stop = riscv_tr_tb_stop, 891 .disas_log = riscv_tr_disas_log, 892 }; 893 894 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 895 { 896 DisasContext ctx; 897 898 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 899 } 900 901 void riscv_translate_init(void) 902 { 903 int i; 904 905 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ 906 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ 907 /* registers, unless you specifically block reads/writes to reg 0 */ 908 cpu_gpr[0] = NULL; 909 910 for (i = 1; i < 32; i++) { 911 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 912 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 913 } 914 915 for (i = 0; i < 32; i++) { 916 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 917 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 918 } 919 920 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 921 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 922 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 923 "load_res"); 924 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 925 "load_val"); 926 } 927