1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 105 TCGv_i64 ftemp[4]; 106 uint8_t nftemp; 107 /* PointerMasking extension */ 108 bool pm_mask_enabled; 109 bool pm_base_enabled; 110 /* TCG of the current insn_start */ 111 TCGOp *insn_start; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 120 { 121 return true; 122 } 123 124 #define MATERIALISE_EXT_PREDICATE(ext) \ 125 static bool has_ ## ext ## _p(DisasContext *ctx) \ 126 { \ 127 return ctx->cfg_ptr->ext_ ## ext ; \ 128 } 129 130 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 131 132 #ifdef TARGET_RISCV32 133 #define get_xl(ctx) MXL_RV32 134 #elif defined(CONFIG_USER_ONLY) 135 #define get_xl(ctx) MXL_RV64 136 #else 137 #define get_xl(ctx) ((ctx)->xl) 138 #endif 139 140 /* The word size for this machine mode. */ 141 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 142 { 143 return 16 << get_xl(ctx); 144 } 145 146 /* The operation length, as opposed to the xlen. */ 147 #ifdef TARGET_RISCV32 148 #define get_ol(ctx) MXL_RV32 149 #else 150 #define get_ol(ctx) ((ctx)->ol) 151 #endif 152 153 static inline int get_olen(DisasContext *ctx) 154 { 155 return 16 << get_ol(ctx); 156 } 157 158 /* The maximum register length */ 159 #ifdef TARGET_RISCV32 160 #define get_xl_max(ctx) MXL_RV32 161 #else 162 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 163 #endif 164 165 /* 166 * RISC-V requires NaN-boxing of narrower width floating point values. 167 * This applies when a 32-bit value is assigned to a 64-bit FP register. 168 * For consistency and simplicity, we nanbox results even when the RVD 169 * extension is not present. 170 */ 171 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 172 { 173 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 174 } 175 176 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 179 } 180 181 /* 182 * A narrow n-bit operation, where n < FLEN, checks that input operands 183 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 184 * If so, the least-significant bits of the input are used, otherwise the 185 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 186 * 187 * Here, the result is always nan-boxed, even the canonical nan. 188 */ 189 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 190 { 191 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 192 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 193 194 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 195 tcg_temp_free_i64(t_max); 196 tcg_temp_free_i64(t_nan); 197 } 198 199 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 200 { 201 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 202 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 203 204 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 205 } 206 207 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 208 { 209 if (get_xl(ctx) == MXL_RV32) { 210 dest = (int32_t)dest; 211 } 212 tcg_gen_movi_tl(cpu_pc, dest); 213 } 214 215 static void gen_set_pc(DisasContext *ctx, TCGv dest) 216 { 217 if (get_xl(ctx) == MXL_RV32) { 218 tcg_gen_ext32s_tl(cpu_pc, dest); 219 } else { 220 tcg_gen_mov_tl(cpu_pc, dest); 221 } 222 } 223 224 static void generate_exception(DisasContext *ctx, int excp) 225 { 226 gen_set_pc_imm(ctx, ctx->base.pc_next); 227 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 228 ctx->base.is_jmp = DISAS_NORETURN; 229 } 230 231 static void generate_exception_mtval(DisasContext *ctx, int excp) 232 { 233 gen_set_pc_imm(ctx, ctx->base.pc_next); 234 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 235 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 236 ctx->base.is_jmp = DISAS_NORETURN; 237 } 238 239 static void gen_exception_illegal(DisasContext *ctx) 240 { 241 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 242 } 243 244 static void gen_exception_inst_addr_mis(DisasContext *ctx) 245 { 246 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 247 } 248 249 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 250 { 251 if (translator_use_goto_tb(&ctx->base, dest)) { 252 tcg_gen_goto_tb(n); 253 gen_set_pc_imm(ctx, dest); 254 tcg_gen_exit_tb(ctx->base.tb, n); 255 } else { 256 gen_set_pc_imm(ctx, dest); 257 tcg_gen_lookup_and_goto_ptr(); 258 } 259 } 260 261 /* 262 * Wrappers for getting reg values. 263 * 264 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 265 * constant zero as a source, and an uninitialized sink as destination. 266 * 267 * Further, we may provide an extension for word operations. 268 */ 269 static TCGv temp_new(DisasContext *ctx) 270 { 271 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 272 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 273 } 274 275 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 276 { 277 TCGv t; 278 279 if (reg_num == 0) { 280 return ctx->zero; 281 } 282 283 switch (get_ol(ctx)) { 284 case MXL_RV32: 285 switch (ext) { 286 case EXT_NONE: 287 break; 288 case EXT_SIGN: 289 t = temp_new(ctx); 290 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 291 return t; 292 case EXT_ZERO: 293 t = temp_new(ctx); 294 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 295 return t; 296 default: 297 g_assert_not_reached(); 298 } 299 break; 300 case MXL_RV64: 301 case MXL_RV128: 302 break; 303 default: 304 g_assert_not_reached(); 305 } 306 return cpu_gpr[reg_num]; 307 } 308 309 static TCGv get_gprh(DisasContext *ctx, int reg_num) 310 { 311 assert(get_xl(ctx) == MXL_RV128); 312 if (reg_num == 0) { 313 return ctx->zero; 314 } 315 return cpu_gprh[reg_num]; 316 } 317 318 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 319 { 320 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 321 return temp_new(ctx); 322 } 323 return cpu_gpr[reg_num]; 324 } 325 326 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 327 { 328 if (reg_num == 0) { 329 return temp_new(ctx); 330 } 331 return cpu_gprh[reg_num]; 332 } 333 334 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 335 { 336 if (reg_num != 0) { 337 switch (get_ol(ctx)) { 338 case MXL_RV32: 339 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 340 break; 341 case MXL_RV64: 342 case MXL_RV128: 343 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 344 break; 345 default: 346 g_assert_not_reached(); 347 } 348 349 if (get_xl_max(ctx) == MXL_RV128) { 350 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 351 } 352 } 353 } 354 355 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 356 { 357 if (reg_num != 0) { 358 switch (get_ol(ctx)) { 359 case MXL_RV32: 360 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 361 break; 362 case MXL_RV64: 363 case MXL_RV128: 364 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 365 break; 366 default: 367 g_assert_not_reached(); 368 } 369 370 if (get_xl_max(ctx) == MXL_RV128) { 371 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 372 } 373 } 374 } 375 376 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 377 { 378 assert(get_ol(ctx) == MXL_RV128); 379 if (reg_num != 0) { 380 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 381 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 382 } 383 } 384 385 static TCGv_i64 ftemp_new(DisasContext *ctx) 386 { 387 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 388 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 389 } 390 391 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 392 { 393 if (!ctx->cfg_ptr->ext_zfinx) { 394 return cpu_fpr[reg_num]; 395 } 396 397 if (reg_num == 0) { 398 return tcg_constant_i64(0); 399 } 400 switch (get_xl(ctx)) { 401 case MXL_RV32: 402 #ifdef TARGET_RISCV32 403 { 404 TCGv_i64 t = ftemp_new(ctx); 405 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 406 return t; 407 } 408 #else 409 /* fall through */ 410 case MXL_RV64: 411 return cpu_gpr[reg_num]; 412 #endif 413 default: 414 g_assert_not_reached(); 415 } 416 } 417 418 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 419 { 420 if (!ctx->cfg_ptr->ext_zfinx) { 421 return cpu_fpr[reg_num]; 422 } 423 424 if (reg_num == 0) { 425 return tcg_constant_i64(0); 426 } 427 switch (get_xl(ctx)) { 428 case MXL_RV32: 429 { 430 TCGv_i64 t = ftemp_new(ctx); 431 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 432 return t; 433 } 434 #ifdef TARGET_RISCV64 435 case MXL_RV64: 436 return cpu_gpr[reg_num]; 437 #endif 438 default: 439 g_assert_not_reached(); 440 } 441 } 442 443 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 444 { 445 if (!ctx->cfg_ptr->ext_zfinx) { 446 return cpu_fpr[reg_num]; 447 } 448 449 if (reg_num == 0) { 450 return ftemp_new(ctx); 451 } 452 453 switch (get_xl(ctx)) { 454 case MXL_RV32: 455 return ftemp_new(ctx); 456 #ifdef TARGET_RISCV64 457 case MXL_RV64: 458 return cpu_gpr[reg_num]; 459 #endif 460 default: 461 g_assert_not_reached(); 462 } 463 } 464 465 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 466 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 467 { 468 if (!ctx->cfg_ptr->ext_zfinx) { 469 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 470 return; 471 } 472 if (reg_num != 0) { 473 switch (get_xl(ctx)) { 474 case MXL_RV32: 475 #ifdef TARGET_RISCV32 476 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 477 break; 478 #else 479 /* fall through */ 480 case MXL_RV64: 481 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 482 break; 483 #endif 484 default: 485 g_assert_not_reached(); 486 } 487 } 488 } 489 490 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 491 { 492 if (!ctx->cfg_ptr->ext_zfinx) { 493 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 494 return; 495 } 496 497 if (reg_num != 0) { 498 switch (get_xl(ctx)) { 499 case MXL_RV32: 500 #ifdef TARGET_RISCV32 501 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 502 break; 503 #else 504 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 505 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 506 break; 507 case MXL_RV64: 508 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 509 break; 510 #endif 511 default: 512 g_assert_not_reached(); 513 } 514 } 515 } 516 517 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 518 { 519 target_ulong next_pc; 520 521 /* check misaligned: */ 522 next_pc = ctx->base.pc_next + imm; 523 if (!has_ext(ctx, RVC)) { 524 if ((next_pc & 0x3) != 0) { 525 gen_exception_inst_addr_mis(ctx); 526 return; 527 } 528 } 529 530 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 531 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 532 ctx->base.is_jmp = DISAS_NORETURN; 533 } 534 535 /* Compute a canonical address from a register plus offset. */ 536 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 537 { 538 TCGv addr = temp_new(ctx); 539 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 540 541 tcg_gen_addi_tl(addr, src1, imm); 542 if (ctx->pm_mask_enabled) { 543 tcg_gen_and_tl(addr, addr, pm_mask); 544 } else if (get_xl(ctx) == MXL_RV32) { 545 tcg_gen_ext32u_tl(addr, addr); 546 } 547 if (ctx->pm_base_enabled) { 548 tcg_gen_or_tl(addr, addr, pm_base); 549 } 550 return addr; 551 } 552 553 #ifndef CONFIG_USER_ONLY 554 /* The states of mstatus_fs are: 555 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 556 * We will have already diagnosed disabled state, 557 * and need to turn initial/clean into dirty. 558 */ 559 static void mark_fs_dirty(DisasContext *ctx) 560 { 561 TCGv tmp; 562 563 if (!has_ext(ctx, RVF)) { 564 return; 565 } 566 567 if (ctx->mstatus_fs != MSTATUS_FS) { 568 /* Remember the state change for the rest of the TB. */ 569 ctx->mstatus_fs = MSTATUS_FS; 570 571 tmp = tcg_temp_new(); 572 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 573 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 574 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 575 tcg_temp_free(tmp); 576 } 577 578 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 579 /* Remember the stage change for the rest of the TB. */ 580 ctx->mstatus_hs_fs = MSTATUS_FS; 581 582 tmp = tcg_temp_new(); 583 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 584 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 585 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 586 tcg_temp_free(tmp); 587 } 588 } 589 #else 590 static inline void mark_fs_dirty(DisasContext *ctx) { } 591 #endif 592 593 #ifndef CONFIG_USER_ONLY 594 /* The states of mstatus_vs are: 595 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 596 * We will have already diagnosed disabled state, 597 * and need to turn initial/clean into dirty. 598 */ 599 static void mark_vs_dirty(DisasContext *ctx) 600 { 601 TCGv tmp; 602 603 if (ctx->mstatus_vs != MSTATUS_VS) { 604 /* Remember the state change for the rest of the TB. */ 605 ctx->mstatus_vs = MSTATUS_VS; 606 607 tmp = tcg_temp_new(); 608 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 609 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 610 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 611 tcg_temp_free(tmp); 612 } 613 614 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 615 /* Remember the stage change for the rest of the TB. */ 616 ctx->mstatus_hs_vs = MSTATUS_VS; 617 618 tmp = tcg_temp_new(); 619 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 620 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 621 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 622 tcg_temp_free(tmp); 623 } 624 } 625 #else 626 static inline void mark_vs_dirty(DisasContext *ctx) { } 627 #endif 628 629 static void gen_set_rm(DisasContext *ctx, int rm) 630 { 631 if (ctx->frm == rm) { 632 return; 633 } 634 ctx->frm = rm; 635 636 if (rm == RISCV_FRM_ROD) { 637 gen_helper_set_rod_rounding_mode(cpu_env); 638 return; 639 } 640 641 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 642 } 643 644 static int ex_plus_1(DisasContext *ctx, int nf) 645 { 646 return nf + 1; 647 } 648 649 #define EX_SH(amount) \ 650 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 651 { \ 652 return imm << amount; \ 653 } 654 EX_SH(1) 655 EX_SH(2) 656 EX_SH(3) 657 EX_SH(4) 658 EX_SH(12) 659 660 #define REQUIRE_EXT(ctx, ext) do { \ 661 if (!has_ext(ctx, ext)) { \ 662 return false; \ 663 } \ 664 } while (0) 665 666 #define REQUIRE_32BIT(ctx) do { \ 667 if (get_xl(ctx) != MXL_RV32) { \ 668 return false; \ 669 } \ 670 } while (0) 671 672 #define REQUIRE_64BIT(ctx) do { \ 673 if (get_xl(ctx) != MXL_RV64) { \ 674 return false; \ 675 } \ 676 } while (0) 677 678 #define REQUIRE_128BIT(ctx) do { \ 679 if (get_xl(ctx) != MXL_RV128) { \ 680 return false; \ 681 } \ 682 } while (0) 683 684 #define REQUIRE_64_OR_128BIT(ctx) do { \ 685 if (get_xl(ctx) == MXL_RV32) { \ 686 return false; \ 687 } \ 688 } while (0) 689 690 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 691 if (!ctx->cfg_ptr->ext_##A && \ 692 !ctx->cfg_ptr->ext_##B) { \ 693 return false; \ 694 } \ 695 } while (0) 696 697 static int ex_rvc_register(DisasContext *ctx, int reg) 698 { 699 return 8 + reg; 700 } 701 702 static int ex_rvc_shifti(DisasContext *ctx, int imm) 703 { 704 /* For RV128 a shamt of 0 means a shift by 64. */ 705 return imm ? imm : 64; 706 } 707 708 /* Include the auto-generated decoder for 32 bit insn */ 709 #include "decode-insn32.c.inc" 710 711 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 712 void (*func)(TCGv, TCGv, target_long)) 713 { 714 TCGv dest = dest_gpr(ctx, a->rd); 715 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 716 717 func(dest, src1, a->imm); 718 719 if (get_xl(ctx) == MXL_RV128) { 720 TCGv src1h = get_gprh(ctx, a->rs1); 721 TCGv desth = dest_gprh(ctx, a->rd); 722 723 func(desth, src1h, -(a->imm < 0)); 724 gen_set_gpr128(ctx, a->rd, dest, desth); 725 } else { 726 gen_set_gpr(ctx, a->rd, dest); 727 } 728 729 return true; 730 } 731 732 static bool gen_logic(DisasContext *ctx, arg_r *a, 733 void (*func)(TCGv, TCGv, TCGv)) 734 { 735 TCGv dest = dest_gpr(ctx, a->rd); 736 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 737 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 738 739 func(dest, src1, src2); 740 741 if (get_xl(ctx) == MXL_RV128) { 742 TCGv src1h = get_gprh(ctx, a->rs1); 743 TCGv src2h = get_gprh(ctx, a->rs2); 744 TCGv desth = dest_gprh(ctx, a->rd); 745 746 func(desth, src1h, src2h); 747 gen_set_gpr128(ctx, a->rd, dest, desth); 748 } else { 749 gen_set_gpr(ctx, a->rd, dest); 750 } 751 752 return true; 753 } 754 755 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 756 void (*func)(TCGv, TCGv, target_long), 757 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 758 { 759 TCGv dest = dest_gpr(ctx, a->rd); 760 TCGv src1 = get_gpr(ctx, a->rs1, ext); 761 762 if (get_ol(ctx) < MXL_RV128) { 763 func(dest, src1, a->imm); 764 gen_set_gpr(ctx, a->rd, dest); 765 } else { 766 if (f128 == NULL) { 767 return false; 768 } 769 770 TCGv src1h = get_gprh(ctx, a->rs1); 771 TCGv desth = dest_gprh(ctx, a->rd); 772 773 f128(dest, desth, src1, src1h, a->imm); 774 gen_set_gpr128(ctx, a->rd, dest, desth); 775 } 776 return true; 777 } 778 779 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 780 void (*func)(TCGv, TCGv, TCGv), 781 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 782 { 783 TCGv dest = dest_gpr(ctx, a->rd); 784 TCGv src1 = get_gpr(ctx, a->rs1, ext); 785 TCGv src2 = tcg_constant_tl(a->imm); 786 787 if (get_ol(ctx) < MXL_RV128) { 788 func(dest, src1, src2); 789 gen_set_gpr(ctx, a->rd, dest); 790 } else { 791 if (f128 == NULL) { 792 return false; 793 } 794 795 TCGv src1h = get_gprh(ctx, a->rs1); 796 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 797 TCGv desth = dest_gprh(ctx, a->rd); 798 799 f128(dest, desth, src1, src1h, src2, src2h); 800 gen_set_gpr128(ctx, a->rd, dest, desth); 801 } 802 return true; 803 } 804 805 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 806 void (*func)(TCGv, TCGv, TCGv), 807 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 808 { 809 TCGv dest = dest_gpr(ctx, a->rd); 810 TCGv src1 = get_gpr(ctx, a->rs1, ext); 811 TCGv src2 = get_gpr(ctx, a->rs2, ext); 812 813 if (get_ol(ctx) < MXL_RV128) { 814 func(dest, src1, src2); 815 gen_set_gpr(ctx, a->rd, dest); 816 } else { 817 if (f128 == NULL) { 818 return false; 819 } 820 821 TCGv src1h = get_gprh(ctx, a->rs1); 822 TCGv src2h = get_gprh(ctx, a->rs2); 823 TCGv desth = dest_gprh(ctx, a->rd); 824 825 f128(dest, desth, src1, src1h, src2, src2h); 826 gen_set_gpr128(ctx, a->rd, dest, desth); 827 } 828 return true; 829 } 830 831 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 832 void (*f_tl)(TCGv, TCGv, TCGv), 833 void (*f_32)(TCGv, TCGv, TCGv), 834 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 835 { 836 int olen = get_olen(ctx); 837 838 if (olen != TARGET_LONG_BITS) { 839 if (olen == 32) { 840 f_tl = f_32; 841 } else if (olen != 128) { 842 g_assert_not_reached(); 843 } 844 } 845 return gen_arith(ctx, a, ext, f_tl, f_128); 846 } 847 848 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 849 void (*func)(TCGv, TCGv, target_long), 850 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 851 { 852 TCGv dest, src1; 853 int max_len = get_olen(ctx); 854 855 if (a->shamt >= max_len) { 856 return false; 857 } 858 859 dest = dest_gpr(ctx, a->rd); 860 src1 = get_gpr(ctx, a->rs1, ext); 861 862 if (max_len < 128) { 863 func(dest, src1, a->shamt); 864 gen_set_gpr(ctx, a->rd, dest); 865 } else { 866 TCGv src1h = get_gprh(ctx, a->rs1); 867 TCGv desth = dest_gprh(ctx, a->rd); 868 869 if (f128 == NULL) { 870 return false; 871 } 872 f128(dest, desth, src1, src1h, a->shamt); 873 gen_set_gpr128(ctx, a->rd, dest, desth); 874 } 875 return true; 876 } 877 878 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 879 DisasExtend ext, 880 void (*f_tl)(TCGv, TCGv, target_long), 881 void (*f_32)(TCGv, TCGv, target_long), 882 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 883 target_long)) 884 { 885 int olen = get_olen(ctx); 886 if (olen != TARGET_LONG_BITS) { 887 if (olen == 32) { 888 f_tl = f_32; 889 } else if (olen != 128) { 890 g_assert_not_reached(); 891 } 892 } 893 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 894 } 895 896 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 897 void (*func)(TCGv, TCGv, TCGv)) 898 { 899 TCGv dest, src1, src2; 900 int max_len = get_olen(ctx); 901 902 if (a->shamt >= max_len) { 903 return false; 904 } 905 906 dest = dest_gpr(ctx, a->rd); 907 src1 = get_gpr(ctx, a->rs1, ext); 908 src2 = tcg_constant_tl(a->shamt); 909 910 func(dest, src1, src2); 911 912 gen_set_gpr(ctx, a->rd, dest); 913 return true; 914 } 915 916 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 917 void (*func)(TCGv, TCGv, TCGv), 918 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 919 { 920 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 921 TCGv ext2 = tcg_temp_new(); 922 int max_len = get_olen(ctx); 923 924 tcg_gen_andi_tl(ext2, src2, max_len - 1); 925 926 TCGv dest = dest_gpr(ctx, a->rd); 927 TCGv src1 = get_gpr(ctx, a->rs1, ext); 928 929 if (max_len < 128) { 930 func(dest, src1, ext2); 931 gen_set_gpr(ctx, a->rd, dest); 932 } else { 933 TCGv src1h = get_gprh(ctx, a->rs1); 934 TCGv desth = dest_gprh(ctx, a->rd); 935 936 if (f128 == NULL) { 937 return false; 938 } 939 f128(dest, desth, src1, src1h, ext2); 940 gen_set_gpr128(ctx, a->rd, dest, desth); 941 } 942 tcg_temp_free(ext2); 943 return true; 944 } 945 946 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 947 void (*f_tl)(TCGv, TCGv, TCGv), 948 void (*f_32)(TCGv, TCGv, TCGv), 949 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 950 { 951 int olen = get_olen(ctx); 952 if (olen != TARGET_LONG_BITS) { 953 if (olen == 32) { 954 f_tl = f_32; 955 } else if (olen != 128) { 956 g_assert_not_reached(); 957 } 958 } 959 return gen_shift(ctx, a, ext, f_tl, f_128); 960 } 961 962 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 963 void (*func)(TCGv, TCGv)) 964 { 965 TCGv dest = dest_gpr(ctx, a->rd); 966 TCGv src1 = get_gpr(ctx, a->rs1, ext); 967 968 func(dest, src1); 969 970 gen_set_gpr(ctx, a->rd, dest); 971 return true; 972 } 973 974 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 975 void (*f_tl)(TCGv, TCGv), 976 void (*f_32)(TCGv, TCGv)) 977 { 978 int olen = get_olen(ctx); 979 980 if (olen != TARGET_LONG_BITS) { 981 if (olen == 32) { 982 f_tl = f_32; 983 } else { 984 g_assert_not_reached(); 985 } 986 } 987 return gen_unary(ctx, a, ext, f_tl); 988 } 989 990 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 991 { 992 DisasContext *ctx = container_of(dcbase, DisasContext, base); 993 CPUState *cpu = ctx->cs; 994 CPURISCVState *env = cpu->env_ptr; 995 996 return cpu_ldl_code(env, pc); 997 } 998 999 /* Include insn module translation function */ 1000 #include "insn_trans/trans_rvi.c.inc" 1001 #include "insn_trans/trans_rvm.c.inc" 1002 #include "insn_trans/trans_rva.c.inc" 1003 #include "insn_trans/trans_rvf.c.inc" 1004 #include "insn_trans/trans_rvd.c.inc" 1005 #include "insn_trans/trans_rvh.c.inc" 1006 #include "insn_trans/trans_rvv.c.inc" 1007 #include "insn_trans/trans_rvb.c.inc" 1008 #include "insn_trans/trans_rvzfh.c.inc" 1009 #include "insn_trans/trans_rvk.c.inc" 1010 #include "insn_trans/trans_privileged.c.inc" 1011 #include "insn_trans/trans_svinval.c.inc" 1012 #include "insn_trans/trans_xventanacondops.c.inc" 1013 1014 /* Include the auto-generated decoder for 16 bit insn */ 1015 #include "decode-insn16.c.inc" 1016 /* Include decoders for factored-out extensions */ 1017 #include "decode-XVentanaCondOps.c.inc" 1018 1019 static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) 1020 { 1021 assert(ctx->insn_start != NULL); 1022 tcg_set_insn_start_param(ctx->insn_start, 1, opc); 1023 ctx->insn_start = NULL; 1024 } 1025 1026 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1027 { 1028 /* 1029 * A table with predicate (i.e., guard) functions and decoder functions 1030 * that are tested in-order until a decoder matches onto the opcode. 1031 */ 1032 static const struct { 1033 bool (*guard_func)(DisasContext *); 1034 bool (*decode_func)(DisasContext *, uint32_t); 1035 } decoders[] = { 1036 { always_true_p, decode_insn32 }, 1037 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1038 }; 1039 1040 /* Check for compressed insn */ 1041 if (extract16(opcode, 0, 2) != 3) { 1042 decode_save_opc(ctx, opcode); 1043 if (!has_ext(ctx, RVC)) { 1044 gen_exception_illegal(ctx); 1045 } else { 1046 ctx->opcode = opcode; 1047 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1048 if (decode_insn16(ctx, opcode)) { 1049 return; 1050 } 1051 } 1052 } else { 1053 uint32_t opcode32 = opcode; 1054 opcode32 = deposit32(opcode32, 16, 16, 1055 translator_lduw(env, &ctx->base, 1056 ctx->base.pc_next + 2)); 1057 decode_save_opc(ctx, opcode32); 1058 ctx->opcode = opcode32; 1059 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1060 1061 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1062 if (decoders[i].guard_func(ctx) && 1063 decoders[i].decode_func(ctx, opcode32)) { 1064 return; 1065 } 1066 } 1067 } 1068 1069 gen_exception_illegal(ctx); 1070 } 1071 1072 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1073 { 1074 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1075 CPURISCVState *env = cs->env_ptr; 1076 RISCVCPU *cpu = RISCV_CPU(cs); 1077 uint32_t tb_flags = ctx->base.tb->flags; 1078 1079 ctx->pc_succ_insn = ctx->base.pc_first; 1080 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1081 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1082 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1083 ctx->priv_ver = env->priv_ver; 1084 #if !defined(CONFIG_USER_ONLY) 1085 if (riscv_has_ext(env, RVH)) { 1086 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1087 } else { 1088 ctx->virt_enabled = false; 1089 } 1090 #else 1091 ctx->virt_enabled = false; 1092 #endif 1093 ctx->misa_ext = env->misa_ext; 1094 ctx->frm = -1; /* unknown rounding mode */ 1095 ctx->cfg_ptr = &(cpu->cfg); 1096 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1097 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1098 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1099 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1100 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1101 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1102 ctx->vstart = env->vstart; 1103 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1104 ctx->misa_mxl_max = env->misa_mxl_max; 1105 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1106 ctx->cs = cs; 1107 ctx->ntemp = 0; 1108 memset(ctx->temp, 0, sizeof(ctx->temp)); 1109 ctx->nftemp = 0; 1110 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1111 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1112 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1113 ctx->zero = tcg_constant_tl(0); 1114 } 1115 1116 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1117 { 1118 } 1119 1120 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1121 { 1122 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1123 1124 tcg_gen_insn_start(ctx->base.pc_next, 0); 1125 ctx->insn_start = tcg_last_op(); 1126 } 1127 1128 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1129 { 1130 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1131 CPURISCVState *env = cpu->env_ptr; 1132 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1133 int i; 1134 1135 ctx->ol = ctx->xl; 1136 decode_opc(env, ctx, opcode16); 1137 ctx->base.pc_next = ctx->pc_succ_insn; 1138 1139 for (i = ctx->ntemp - 1; i >= 0; --i) { 1140 tcg_temp_free(ctx->temp[i]); 1141 ctx->temp[i] = NULL; 1142 } 1143 ctx->ntemp = 0; 1144 for (i = ctx->nftemp - 1; i >= 0; --i) { 1145 tcg_temp_free_i64(ctx->ftemp[i]); 1146 ctx->ftemp[i] = NULL; 1147 } 1148 ctx->nftemp = 0; 1149 1150 if (ctx->base.is_jmp == DISAS_NEXT) { 1151 target_ulong page_start; 1152 1153 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1154 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 1155 ctx->base.is_jmp = DISAS_TOO_MANY; 1156 } 1157 } 1158 } 1159 1160 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1161 { 1162 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1163 1164 switch (ctx->base.is_jmp) { 1165 case DISAS_TOO_MANY: 1166 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1167 break; 1168 case DISAS_NORETURN: 1169 break; 1170 default: 1171 g_assert_not_reached(); 1172 } 1173 } 1174 1175 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1176 CPUState *cpu, FILE *logfile) 1177 { 1178 #ifndef CONFIG_USER_ONLY 1179 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1180 CPURISCVState *env = &rvcpu->env; 1181 #endif 1182 1183 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1184 #ifndef CONFIG_USER_ONLY 1185 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1186 env->priv, env->virt); 1187 #endif 1188 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1189 } 1190 1191 static const TranslatorOps riscv_tr_ops = { 1192 .init_disas_context = riscv_tr_init_disas_context, 1193 .tb_start = riscv_tr_tb_start, 1194 .insn_start = riscv_tr_insn_start, 1195 .translate_insn = riscv_tr_translate_insn, 1196 .tb_stop = riscv_tr_tb_stop, 1197 .disas_log = riscv_tr_disas_log, 1198 }; 1199 1200 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1201 { 1202 DisasContext ctx; 1203 1204 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1205 } 1206 1207 void riscv_translate_init(void) 1208 { 1209 int i; 1210 1211 /* 1212 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1213 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1214 * unless you specifically block reads/writes to reg 0. 1215 */ 1216 cpu_gpr[0] = NULL; 1217 cpu_gprh[0] = NULL; 1218 1219 for (i = 1; i < 32; i++) { 1220 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1221 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1222 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1223 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1224 } 1225 1226 for (i = 0; i < 32; i++) { 1227 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1228 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1229 } 1230 1231 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1232 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1233 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1234 "vstart"); 1235 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1236 "load_res"); 1237 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1238 "load_val"); 1239 /* Assign PM CSRs to tcg globals */ 1240 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1241 "pmmask"); 1242 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1243 "pmbase"); 1244 } 1245