1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* PointerMasking extension */ 105 bool pm_mask_enabled; 106 bool pm_base_enabled; 107 } DisasContext; 108 109 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 110 { 111 return ctx->misa_ext & ext; 112 } 113 114 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 115 { 116 return true; 117 } 118 119 #define MATERIALISE_EXT_PREDICATE(ext) \ 120 static bool has_ ## ext ## _p(DisasContext *ctx) \ 121 { \ 122 return ctx->cfg_ptr->ext_ ## ext ; \ 123 } 124 125 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 126 127 #ifdef TARGET_RISCV32 128 #define get_xl(ctx) MXL_RV32 129 #elif defined(CONFIG_USER_ONLY) 130 #define get_xl(ctx) MXL_RV64 131 #else 132 #define get_xl(ctx) ((ctx)->xl) 133 #endif 134 135 /* The word size for this machine mode. */ 136 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 137 { 138 return 16 << get_xl(ctx); 139 } 140 141 /* The operation length, as opposed to the xlen. */ 142 #ifdef TARGET_RISCV32 143 #define get_ol(ctx) MXL_RV32 144 #else 145 #define get_ol(ctx) ((ctx)->ol) 146 #endif 147 148 static inline int get_olen(DisasContext *ctx) 149 { 150 return 16 << get_ol(ctx); 151 } 152 153 /* The maximum register length */ 154 #ifdef TARGET_RISCV32 155 #define get_xl_max(ctx) MXL_RV32 156 #else 157 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 158 #endif 159 160 /* 161 * RISC-V requires NaN-boxing of narrower width floating point values. 162 * This applies when a 32-bit value is assigned to a 64-bit FP register. 163 * For consistency and simplicity, we nanbox results even when the RVD 164 * extension is not present. 165 */ 166 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 167 { 168 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 169 } 170 171 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 172 { 173 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 174 } 175 176 /* 177 * A narrow n-bit operation, where n < FLEN, checks that input operands 178 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 179 * If so, the least-significant bits of the input are used, otherwise the 180 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 181 * 182 * Here, the result is always nan-boxed, even the canonical nan. 183 */ 184 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 185 { 186 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 187 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 188 189 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 190 tcg_temp_free_i64(t_max); 191 tcg_temp_free_i64(t_nan); 192 } 193 194 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 195 { 196 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 197 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 198 199 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 200 } 201 202 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 203 { 204 if (get_xl(ctx) == MXL_RV32) { 205 dest = (int32_t)dest; 206 } 207 tcg_gen_movi_tl(cpu_pc, dest); 208 } 209 210 static void gen_set_pc(DisasContext *ctx, TCGv dest) 211 { 212 if (get_xl(ctx) == MXL_RV32) { 213 tcg_gen_ext32s_tl(cpu_pc, dest); 214 } else { 215 tcg_gen_mov_tl(cpu_pc, dest); 216 } 217 } 218 219 static void generate_exception(DisasContext *ctx, int excp) 220 { 221 gen_set_pc_imm(ctx, ctx->base.pc_next); 222 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 223 ctx->base.is_jmp = DISAS_NORETURN; 224 } 225 226 static void generate_exception_mtval(DisasContext *ctx, int excp) 227 { 228 gen_set_pc_imm(ctx, ctx->base.pc_next); 229 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 230 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 231 ctx->base.is_jmp = DISAS_NORETURN; 232 } 233 234 static void gen_exception_illegal(DisasContext *ctx) 235 { 236 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 237 offsetof(CPURISCVState, bins)); 238 239 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 240 } 241 242 static void gen_exception_inst_addr_mis(DisasContext *ctx) 243 { 244 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 245 } 246 247 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 248 { 249 if (translator_use_goto_tb(&ctx->base, dest)) { 250 tcg_gen_goto_tb(n); 251 gen_set_pc_imm(ctx, dest); 252 tcg_gen_exit_tb(ctx->base.tb, n); 253 } else { 254 gen_set_pc_imm(ctx, dest); 255 tcg_gen_lookup_and_goto_ptr(); 256 } 257 } 258 259 /* 260 * Wrappers for getting reg values. 261 * 262 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 263 * constant zero as a source, and an uninitialized sink as destination. 264 * 265 * Further, we may provide an extension for word operations. 266 */ 267 static TCGv temp_new(DisasContext *ctx) 268 { 269 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 270 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 271 } 272 273 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 274 { 275 TCGv t; 276 277 if (reg_num == 0) { 278 return ctx->zero; 279 } 280 281 switch (get_ol(ctx)) { 282 case MXL_RV32: 283 switch (ext) { 284 case EXT_NONE: 285 break; 286 case EXT_SIGN: 287 t = temp_new(ctx); 288 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 289 return t; 290 case EXT_ZERO: 291 t = temp_new(ctx); 292 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 293 return t; 294 default: 295 g_assert_not_reached(); 296 } 297 break; 298 case MXL_RV64: 299 case MXL_RV128: 300 break; 301 default: 302 g_assert_not_reached(); 303 } 304 return cpu_gpr[reg_num]; 305 } 306 307 static TCGv get_gprh(DisasContext *ctx, int reg_num) 308 { 309 assert(get_xl(ctx) == MXL_RV128); 310 if (reg_num == 0) { 311 return ctx->zero; 312 } 313 return cpu_gprh[reg_num]; 314 } 315 316 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 317 { 318 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 319 return temp_new(ctx); 320 } 321 return cpu_gpr[reg_num]; 322 } 323 324 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 325 { 326 if (reg_num == 0) { 327 return temp_new(ctx); 328 } 329 return cpu_gprh[reg_num]; 330 } 331 332 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 333 { 334 if (reg_num != 0) { 335 switch (get_ol(ctx)) { 336 case MXL_RV32: 337 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 338 break; 339 case MXL_RV64: 340 case MXL_RV128: 341 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 347 if (get_xl_max(ctx) == MXL_RV128) { 348 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 349 } 350 } 351 } 352 353 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 354 { 355 if (reg_num != 0) { 356 switch (get_ol(ctx)) { 357 case MXL_RV32: 358 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 359 break; 360 case MXL_RV64: 361 case MXL_RV128: 362 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 363 break; 364 default: 365 g_assert_not_reached(); 366 } 367 368 if (get_xl_max(ctx) == MXL_RV128) { 369 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 370 } 371 } 372 } 373 374 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 375 { 376 assert(get_ol(ctx) == MXL_RV128); 377 if (reg_num != 0) { 378 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 379 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 380 } 381 } 382 383 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 384 { 385 target_ulong next_pc; 386 387 /* check misaligned: */ 388 next_pc = ctx->base.pc_next + imm; 389 if (!has_ext(ctx, RVC)) { 390 if ((next_pc & 0x3) != 0) { 391 gen_exception_inst_addr_mis(ctx); 392 return; 393 } 394 } 395 396 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 397 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 398 ctx->base.is_jmp = DISAS_NORETURN; 399 } 400 401 /* Compute a canonical address from a register plus offset. */ 402 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 403 { 404 TCGv addr = temp_new(ctx); 405 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 406 407 tcg_gen_addi_tl(addr, src1, imm); 408 if (ctx->pm_mask_enabled) { 409 tcg_gen_and_tl(addr, addr, pm_mask); 410 } else if (get_xl(ctx) == MXL_RV32) { 411 tcg_gen_ext32u_tl(addr, addr); 412 } 413 if (ctx->pm_base_enabled) { 414 tcg_gen_or_tl(addr, addr, pm_base); 415 } 416 return addr; 417 } 418 419 #ifndef CONFIG_USER_ONLY 420 /* The states of mstatus_fs are: 421 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 422 * We will have already diagnosed disabled state, 423 * and need to turn initial/clean into dirty. 424 */ 425 static void mark_fs_dirty(DisasContext *ctx) 426 { 427 TCGv tmp; 428 429 if (!has_ext(ctx, RVF)) { 430 return; 431 } 432 433 if (ctx->mstatus_fs != MSTATUS_FS) { 434 /* Remember the state change for the rest of the TB. */ 435 ctx->mstatus_fs = MSTATUS_FS; 436 437 tmp = tcg_temp_new(); 438 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 439 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 440 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 441 tcg_temp_free(tmp); 442 } 443 444 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 445 /* Remember the stage change for the rest of the TB. */ 446 ctx->mstatus_hs_fs = MSTATUS_FS; 447 448 tmp = tcg_temp_new(); 449 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 450 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 451 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 452 tcg_temp_free(tmp); 453 } 454 } 455 #else 456 static inline void mark_fs_dirty(DisasContext *ctx) { } 457 #endif 458 459 #ifndef CONFIG_USER_ONLY 460 /* The states of mstatus_vs are: 461 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 462 * We will have already diagnosed disabled state, 463 * and need to turn initial/clean into dirty. 464 */ 465 static void mark_vs_dirty(DisasContext *ctx) 466 { 467 TCGv tmp; 468 469 if (ctx->mstatus_vs != MSTATUS_VS) { 470 /* Remember the state change for the rest of the TB. */ 471 ctx->mstatus_vs = MSTATUS_VS; 472 473 tmp = tcg_temp_new(); 474 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 475 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 476 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 477 tcg_temp_free(tmp); 478 } 479 480 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 481 /* Remember the stage change for the rest of the TB. */ 482 ctx->mstatus_hs_vs = MSTATUS_VS; 483 484 tmp = tcg_temp_new(); 485 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 486 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 487 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 488 tcg_temp_free(tmp); 489 } 490 } 491 #else 492 static inline void mark_vs_dirty(DisasContext *ctx) { } 493 #endif 494 495 static void gen_set_rm(DisasContext *ctx, int rm) 496 { 497 if (ctx->frm == rm) { 498 return; 499 } 500 ctx->frm = rm; 501 502 if (rm == RISCV_FRM_ROD) { 503 gen_helper_set_rod_rounding_mode(cpu_env); 504 return; 505 } 506 507 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 508 } 509 510 static int ex_plus_1(DisasContext *ctx, int nf) 511 { 512 return nf + 1; 513 } 514 515 #define EX_SH(amount) \ 516 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 517 { \ 518 return imm << amount; \ 519 } 520 EX_SH(1) 521 EX_SH(2) 522 EX_SH(3) 523 EX_SH(4) 524 EX_SH(12) 525 526 #define REQUIRE_EXT(ctx, ext) do { \ 527 if (!has_ext(ctx, ext)) { \ 528 return false; \ 529 } \ 530 } while (0) 531 532 #define REQUIRE_32BIT(ctx) do { \ 533 if (get_xl(ctx) != MXL_RV32) { \ 534 return false; \ 535 } \ 536 } while (0) 537 538 #define REQUIRE_64BIT(ctx) do { \ 539 if (get_xl(ctx) != MXL_RV64) { \ 540 return false; \ 541 } \ 542 } while (0) 543 544 #define REQUIRE_128BIT(ctx) do { \ 545 if (get_xl(ctx) != MXL_RV128) { \ 546 return false; \ 547 } \ 548 } while (0) 549 550 #define REQUIRE_64_OR_128BIT(ctx) do { \ 551 if (get_xl(ctx) == MXL_RV32) { \ 552 return false; \ 553 } \ 554 } while (0) 555 556 static int ex_rvc_register(DisasContext *ctx, int reg) 557 { 558 return 8 + reg; 559 } 560 561 static int ex_rvc_shifti(DisasContext *ctx, int imm) 562 { 563 /* For RV128 a shamt of 0 means a shift by 64. */ 564 return imm ? imm : 64; 565 } 566 567 /* Include the auto-generated decoder for 32 bit insn */ 568 #include "decode-insn32.c.inc" 569 570 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 571 void (*func)(TCGv, TCGv, target_long)) 572 { 573 TCGv dest = dest_gpr(ctx, a->rd); 574 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 575 576 func(dest, src1, a->imm); 577 578 if (get_xl(ctx) == MXL_RV128) { 579 TCGv src1h = get_gprh(ctx, a->rs1); 580 TCGv desth = dest_gprh(ctx, a->rd); 581 582 func(desth, src1h, -(a->imm < 0)); 583 gen_set_gpr128(ctx, a->rd, dest, desth); 584 } else { 585 gen_set_gpr(ctx, a->rd, dest); 586 } 587 588 return true; 589 } 590 591 static bool gen_logic(DisasContext *ctx, arg_r *a, 592 void (*func)(TCGv, TCGv, TCGv)) 593 { 594 TCGv dest = dest_gpr(ctx, a->rd); 595 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 596 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 597 598 func(dest, src1, src2); 599 600 if (get_xl(ctx) == MXL_RV128) { 601 TCGv src1h = get_gprh(ctx, a->rs1); 602 TCGv src2h = get_gprh(ctx, a->rs2); 603 TCGv desth = dest_gprh(ctx, a->rd); 604 605 func(desth, src1h, src2h); 606 gen_set_gpr128(ctx, a->rd, dest, desth); 607 } else { 608 gen_set_gpr(ctx, a->rd, dest); 609 } 610 611 return true; 612 } 613 614 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 615 void (*func)(TCGv, TCGv, target_long), 616 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 617 { 618 TCGv dest = dest_gpr(ctx, a->rd); 619 TCGv src1 = get_gpr(ctx, a->rs1, ext); 620 621 if (get_ol(ctx) < MXL_RV128) { 622 func(dest, src1, a->imm); 623 gen_set_gpr(ctx, a->rd, dest); 624 } else { 625 if (f128 == NULL) { 626 return false; 627 } 628 629 TCGv src1h = get_gprh(ctx, a->rs1); 630 TCGv desth = dest_gprh(ctx, a->rd); 631 632 f128(dest, desth, src1, src1h, a->imm); 633 gen_set_gpr128(ctx, a->rd, dest, desth); 634 } 635 return true; 636 } 637 638 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 639 void (*func)(TCGv, TCGv, TCGv), 640 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 641 { 642 TCGv dest = dest_gpr(ctx, a->rd); 643 TCGv src1 = get_gpr(ctx, a->rs1, ext); 644 TCGv src2 = tcg_constant_tl(a->imm); 645 646 if (get_ol(ctx) < MXL_RV128) { 647 func(dest, src1, src2); 648 gen_set_gpr(ctx, a->rd, dest); 649 } else { 650 if (f128 == NULL) { 651 return false; 652 } 653 654 TCGv src1h = get_gprh(ctx, a->rs1); 655 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 656 TCGv desth = dest_gprh(ctx, a->rd); 657 658 f128(dest, desth, src1, src1h, src2, src2h); 659 gen_set_gpr128(ctx, a->rd, dest, desth); 660 } 661 return true; 662 } 663 664 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 665 void (*func)(TCGv, TCGv, TCGv), 666 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 667 { 668 TCGv dest = dest_gpr(ctx, a->rd); 669 TCGv src1 = get_gpr(ctx, a->rs1, ext); 670 TCGv src2 = get_gpr(ctx, a->rs2, ext); 671 672 if (get_ol(ctx) < MXL_RV128) { 673 func(dest, src1, src2); 674 gen_set_gpr(ctx, a->rd, dest); 675 } else { 676 if (f128 == NULL) { 677 return false; 678 } 679 680 TCGv src1h = get_gprh(ctx, a->rs1); 681 TCGv src2h = get_gprh(ctx, a->rs2); 682 TCGv desth = dest_gprh(ctx, a->rd); 683 684 f128(dest, desth, src1, src1h, src2, src2h); 685 gen_set_gpr128(ctx, a->rd, dest, desth); 686 } 687 return true; 688 } 689 690 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 691 void (*f_tl)(TCGv, TCGv, TCGv), 692 void (*f_32)(TCGv, TCGv, TCGv), 693 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 694 { 695 int olen = get_olen(ctx); 696 697 if (olen != TARGET_LONG_BITS) { 698 if (olen == 32) { 699 f_tl = f_32; 700 } else if (olen != 128) { 701 g_assert_not_reached(); 702 } 703 } 704 return gen_arith(ctx, a, ext, f_tl, f_128); 705 } 706 707 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 708 void (*func)(TCGv, TCGv, target_long), 709 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 710 { 711 TCGv dest, src1; 712 int max_len = get_olen(ctx); 713 714 if (a->shamt >= max_len) { 715 return false; 716 } 717 718 dest = dest_gpr(ctx, a->rd); 719 src1 = get_gpr(ctx, a->rs1, ext); 720 721 if (max_len < 128) { 722 func(dest, src1, a->shamt); 723 gen_set_gpr(ctx, a->rd, dest); 724 } else { 725 TCGv src1h = get_gprh(ctx, a->rs1); 726 TCGv desth = dest_gprh(ctx, a->rd); 727 728 if (f128 == NULL) { 729 return false; 730 } 731 f128(dest, desth, src1, src1h, a->shamt); 732 gen_set_gpr128(ctx, a->rd, dest, desth); 733 } 734 return true; 735 } 736 737 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 738 DisasExtend ext, 739 void (*f_tl)(TCGv, TCGv, target_long), 740 void (*f_32)(TCGv, TCGv, target_long), 741 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 742 target_long)) 743 { 744 int olen = get_olen(ctx); 745 if (olen != TARGET_LONG_BITS) { 746 if (olen == 32) { 747 f_tl = f_32; 748 } else if (olen != 128) { 749 g_assert_not_reached(); 750 } 751 } 752 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 753 } 754 755 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 756 void (*func)(TCGv, TCGv, TCGv)) 757 { 758 TCGv dest, src1, src2; 759 int max_len = get_olen(ctx); 760 761 if (a->shamt >= max_len) { 762 return false; 763 } 764 765 dest = dest_gpr(ctx, a->rd); 766 src1 = get_gpr(ctx, a->rs1, ext); 767 src2 = tcg_constant_tl(a->shamt); 768 769 func(dest, src1, src2); 770 771 gen_set_gpr(ctx, a->rd, dest); 772 return true; 773 } 774 775 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 776 void (*func)(TCGv, TCGv, TCGv), 777 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 778 { 779 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 780 TCGv ext2 = tcg_temp_new(); 781 int max_len = get_olen(ctx); 782 783 tcg_gen_andi_tl(ext2, src2, max_len - 1); 784 785 TCGv dest = dest_gpr(ctx, a->rd); 786 TCGv src1 = get_gpr(ctx, a->rs1, ext); 787 788 if (max_len < 128) { 789 func(dest, src1, ext2); 790 gen_set_gpr(ctx, a->rd, dest); 791 } else { 792 TCGv src1h = get_gprh(ctx, a->rs1); 793 TCGv desth = dest_gprh(ctx, a->rd); 794 795 if (f128 == NULL) { 796 return false; 797 } 798 f128(dest, desth, src1, src1h, ext2); 799 gen_set_gpr128(ctx, a->rd, dest, desth); 800 } 801 tcg_temp_free(ext2); 802 return true; 803 } 804 805 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 806 void (*f_tl)(TCGv, TCGv, TCGv), 807 void (*f_32)(TCGv, TCGv, TCGv), 808 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 809 { 810 int olen = get_olen(ctx); 811 if (olen != TARGET_LONG_BITS) { 812 if (olen == 32) { 813 f_tl = f_32; 814 } else if (olen != 128) { 815 g_assert_not_reached(); 816 } 817 } 818 return gen_shift(ctx, a, ext, f_tl, f_128); 819 } 820 821 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 822 void (*func)(TCGv, TCGv)) 823 { 824 TCGv dest = dest_gpr(ctx, a->rd); 825 TCGv src1 = get_gpr(ctx, a->rs1, ext); 826 827 func(dest, src1); 828 829 gen_set_gpr(ctx, a->rd, dest); 830 return true; 831 } 832 833 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 834 void (*f_tl)(TCGv, TCGv), 835 void (*f_32)(TCGv, TCGv)) 836 { 837 int olen = get_olen(ctx); 838 839 if (olen != TARGET_LONG_BITS) { 840 if (olen == 32) { 841 f_tl = f_32; 842 } else { 843 g_assert_not_reached(); 844 } 845 } 846 return gen_unary(ctx, a, ext, f_tl); 847 } 848 849 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 850 { 851 DisasContext *ctx = container_of(dcbase, DisasContext, base); 852 CPUState *cpu = ctx->cs; 853 CPURISCVState *env = cpu->env_ptr; 854 855 return cpu_ldl_code(env, pc); 856 } 857 858 /* Include insn module translation function */ 859 #include "insn_trans/trans_rvi.c.inc" 860 #include "insn_trans/trans_rvm.c.inc" 861 #include "insn_trans/trans_rva.c.inc" 862 #include "insn_trans/trans_rvf.c.inc" 863 #include "insn_trans/trans_rvd.c.inc" 864 #include "insn_trans/trans_rvh.c.inc" 865 #include "insn_trans/trans_rvv.c.inc" 866 #include "insn_trans/trans_rvb.c.inc" 867 #include "insn_trans/trans_rvzfh.c.inc" 868 #include "insn_trans/trans_privileged.c.inc" 869 #include "insn_trans/trans_svinval.c.inc" 870 #include "insn_trans/trans_xventanacondops.c.inc" 871 872 /* Include the auto-generated decoder for 16 bit insn */ 873 #include "decode-insn16.c.inc" 874 /* Include decoders for factored-out extensions */ 875 #include "decode-XVentanaCondOps.c.inc" 876 877 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 878 { 879 /* 880 * A table with predicate (i.e., guard) functions and decoder functions 881 * that are tested in-order until a decoder matches onto the opcode. 882 */ 883 static const struct { 884 bool (*guard_func)(DisasContext *); 885 bool (*decode_func)(DisasContext *, uint32_t); 886 } decoders[] = { 887 { always_true_p, decode_insn32 }, 888 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 889 }; 890 891 /* Check for compressed insn */ 892 if (extract16(opcode, 0, 2) != 3) { 893 if (!has_ext(ctx, RVC)) { 894 gen_exception_illegal(ctx); 895 } else { 896 ctx->opcode = opcode; 897 ctx->pc_succ_insn = ctx->base.pc_next + 2; 898 if (decode_insn16(ctx, opcode)) { 899 return; 900 } 901 } 902 } else { 903 uint32_t opcode32 = opcode; 904 opcode32 = deposit32(opcode32, 16, 16, 905 translator_lduw(env, &ctx->base, 906 ctx->base.pc_next + 2)); 907 ctx->opcode = opcode32; 908 ctx->pc_succ_insn = ctx->base.pc_next + 4; 909 910 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 911 if (decoders[i].guard_func(ctx) && 912 decoders[i].decode_func(ctx, opcode32)) { 913 return; 914 } 915 } 916 } 917 918 gen_exception_illegal(ctx); 919 } 920 921 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 922 { 923 DisasContext *ctx = container_of(dcbase, DisasContext, base); 924 CPURISCVState *env = cs->env_ptr; 925 RISCVCPU *cpu = RISCV_CPU(cs); 926 uint32_t tb_flags = ctx->base.tb->flags; 927 928 ctx->pc_succ_insn = ctx->base.pc_first; 929 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 930 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 931 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 932 ctx->priv_ver = env->priv_ver; 933 #if !defined(CONFIG_USER_ONLY) 934 if (riscv_has_ext(env, RVH)) { 935 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 936 } else { 937 ctx->virt_enabled = false; 938 } 939 #else 940 ctx->virt_enabled = false; 941 #endif 942 ctx->misa_ext = env->misa_ext; 943 ctx->frm = -1; /* unknown rounding mode */ 944 ctx->cfg_ptr = &(cpu->cfg); 945 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 946 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 947 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 948 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 949 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 950 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 951 ctx->vstart = env->vstart; 952 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 953 ctx->misa_mxl_max = env->misa_mxl_max; 954 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 955 ctx->cs = cs; 956 ctx->ntemp = 0; 957 memset(ctx->temp, 0, sizeof(ctx->temp)); 958 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 959 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 960 ctx->zero = tcg_constant_tl(0); 961 } 962 963 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 964 { 965 } 966 967 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 968 { 969 DisasContext *ctx = container_of(dcbase, DisasContext, base); 970 971 tcg_gen_insn_start(ctx->base.pc_next); 972 } 973 974 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 975 { 976 DisasContext *ctx = container_of(dcbase, DisasContext, base); 977 CPURISCVState *env = cpu->env_ptr; 978 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 979 980 ctx->ol = ctx->xl; 981 decode_opc(env, ctx, opcode16); 982 ctx->base.pc_next = ctx->pc_succ_insn; 983 984 for (int i = ctx->ntemp - 1; i >= 0; --i) { 985 tcg_temp_free(ctx->temp[i]); 986 ctx->temp[i] = NULL; 987 } 988 ctx->ntemp = 0; 989 990 if (ctx->base.is_jmp == DISAS_NEXT) { 991 target_ulong page_start; 992 993 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 994 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 995 ctx->base.is_jmp = DISAS_TOO_MANY; 996 } 997 } 998 } 999 1000 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1001 { 1002 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1003 1004 switch (ctx->base.is_jmp) { 1005 case DISAS_TOO_MANY: 1006 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1007 break; 1008 case DISAS_NORETURN: 1009 break; 1010 default: 1011 g_assert_not_reached(); 1012 } 1013 } 1014 1015 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 1016 { 1017 #ifndef CONFIG_USER_ONLY 1018 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1019 CPURISCVState *env = &rvcpu->env; 1020 #endif 1021 1022 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 1023 #ifndef CONFIG_USER_ONLY 1024 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 1025 #endif 1026 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1027 } 1028 1029 static const TranslatorOps riscv_tr_ops = { 1030 .init_disas_context = riscv_tr_init_disas_context, 1031 .tb_start = riscv_tr_tb_start, 1032 .insn_start = riscv_tr_insn_start, 1033 .translate_insn = riscv_tr_translate_insn, 1034 .tb_stop = riscv_tr_tb_stop, 1035 .disas_log = riscv_tr_disas_log, 1036 }; 1037 1038 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1039 { 1040 DisasContext ctx; 1041 1042 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1043 } 1044 1045 void riscv_translate_init(void) 1046 { 1047 int i; 1048 1049 /* 1050 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1051 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1052 * unless you specifically block reads/writes to reg 0. 1053 */ 1054 cpu_gpr[0] = NULL; 1055 cpu_gprh[0] = NULL; 1056 1057 for (i = 1; i < 32; i++) { 1058 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1059 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1060 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1061 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1062 } 1063 1064 for (i = 0; i < 32; i++) { 1065 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1066 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1067 } 1068 1069 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1070 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1071 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1072 "vstart"); 1073 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1074 "load_res"); 1075 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1076 "load_val"); 1077 /* Assign PM CSRs to tcg globals */ 1078 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1079 "pmmask"); 1080 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1081 "pmbase"); 1082 } 1083