1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 uint8_t ntemp; 105 CPUState *cs; 106 TCGv zero; 107 /* Space for 3 operands plus 1 extra for address computation. */ 108 TCGv temp[4]; 109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 110 TCGv_i64 ftemp[4]; 111 uint8_t nftemp; 112 /* PointerMasking extension */ 113 bool pm_mask_enabled; 114 bool pm_base_enabled; 115 /* Use icount trigger for native debug */ 116 bool itrigger; 117 /* FRM is known to contain a valid value. */ 118 bool frm_valid; 119 /* TCG of the current insn_start */ 120 TCGOp *insn_start; 121 } DisasContext; 122 123 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 124 { 125 return ctx->misa_ext & ext; 126 } 127 128 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 129 { 130 return true; 131 } 132 133 #define MATERIALISE_EXT_PREDICATE(ext) \ 134 static bool has_ ## ext ## _p(DisasContext *ctx) \ 135 { \ 136 return ctx->cfg_ptr->ext_ ## ext ; \ 137 } 138 139 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 140 141 #ifdef TARGET_RISCV32 142 #define get_xl(ctx) MXL_RV32 143 #elif defined(CONFIG_USER_ONLY) 144 #define get_xl(ctx) MXL_RV64 145 #else 146 #define get_xl(ctx) ((ctx)->xl) 147 #endif 148 149 /* The word size for this machine mode. */ 150 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 151 { 152 return 16 << get_xl(ctx); 153 } 154 155 /* The operation length, as opposed to the xlen. */ 156 #ifdef TARGET_RISCV32 157 #define get_ol(ctx) MXL_RV32 158 #else 159 #define get_ol(ctx) ((ctx)->ol) 160 #endif 161 162 static inline int get_olen(DisasContext *ctx) 163 { 164 return 16 << get_ol(ctx); 165 } 166 167 /* The maximum register length */ 168 #ifdef TARGET_RISCV32 169 #define get_xl_max(ctx) MXL_RV32 170 #else 171 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 172 #endif 173 174 /* 175 * RISC-V requires NaN-boxing of narrower width floating point values. 176 * This applies when a 32-bit value is assigned to a 64-bit FP register. 177 * For consistency and simplicity, we nanbox results even when the RVD 178 * extension is not present. 179 */ 180 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 181 { 182 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 183 } 184 185 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 186 { 187 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 188 } 189 190 /* 191 * A narrow n-bit operation, where n < FLEN, checks that input operands 192 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 193 * If so, the least-significant bits of the input are used, otherwise the 194 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 195 * 196 * Here, the result is always nan-boxed, even the canonical nan. 197 */ 198 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 199 { 200 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 201 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 202 203 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 204 tcg_temp_free_i64(t_max); 205 tcg_temp_free_i64(t_nan); 206 } 207 208 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 209 { 210 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 211 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 212 213 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 214 } 215 216 static void decode_save_opc(DisasContext *ctx) 217 { 218 assert(ctx->insn_start != NULL); 219 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 220 ctx->insn_start = NULL; 221 } 222 223 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 224 { 225 if (get_xl(ctx) == MXL_RV32) { 226 dest = (int32_t)dest; 227 } 228 tcg_gen_movi_tl(cpu_pc, dest); 229 } 230 231 static void gen_set_pc(DisasContext *ctx, TCGv dest) 232 { 233 if (get_xl(ctx) == MXL_RV32) { 234 tcg_gen_ext32s_tl(cpu_pc, dest); 235 } else { 236 tcg_gen_mov_tl(cpu_pc, dest); 237 } 238 } 239 240 static void generate_exception(DisasContext *ctx, int excp) 241 { 242 gen_set_pc_imm(ctx, ctx->base.pc_next); 243 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 244 ctx->base.is_jmp = DISAS_NORETURN; 245 } 246 247 static void gen_exception_illegal(DisasContext *ctx) 248 { 249 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 250 offsetof(CPURISCVState, bins)); 251 if (ctx->virt_inst_excp) { 252 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 253 } else { 254 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 255 } 256 } 257 258 static void gen_exception_inst_addr_mis(DisasContext *ctx) 259 { 260 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 261 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 262 } 263 264 static void lookup_and_goto_ptr(DisasContext *ctx) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (ctx->itrigger) { 268 gen_helper_itrigger_match(cpu_env); 269 } 270 #endif 271 tcg_gen_lookup_and_goto_ptr(); 272 } 273 274 static void exit_tb(DisasContext *ctx) 275 { 276 #ifndef CONFIG_USER_ONLY 277 if (ctx->itrigger) { 278 gen_helper_itrigger_match(cpu_env); 279 } 280 #endif 281 tcg_gen_exit_tb(NULL, 0); 282 } 283 284 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 285 { 286 /* 287 * Under itrigger, instruction executes one by one like singlestep, 288 * direct block chain benefits will be small. 289 */ 290 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 291 tcg_gen_goto_tb(n); 292 gen_set_pc_imm(ctx, dest); 293 tcg_gen_exit_tb(ctx->base.tb, n); 294 } else { 295 gen_set_pc_imm(ctx, dest); 296 lookup_and_goto_ptr(ctx); 297 } 298 } 299 300 /* 301 * Wrappers for getting reg values. 302 * 303 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 304 * constant zero as a source, and an uninitialized sink as destination. 305 * 306 * Further, we may provide an extension for word operations. 307 */ 308 static TCGv temp_new(DisasContext *ctx) 309 { 310 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 311 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 312 } 313 314 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 315 { 316 TCGv t; 317 318 if (reg_num == 0) { 319 return ctx->zero; 320 } 321 322 switch (get_ol(ctx)) { 323 case MXL_RV32: 324 switch (ext) { 325 case EXT_NONE: 326 break; 327 case EXT_SIGN: 328 t = temp_new(ctx); 329 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 330 return t; 331 case EXT_ZERO: 332 t = temp_new(ctx); 333 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 334 return t; 335 default: 336 g_assert_not_reached(); 337 } 338 break; 339 case MXL_RV64: 340 case MXL_RV128: 341 break; 342 default: 343 g_assert_not_reached(); 344 } 345 return cpu_gpr[reg_num]; 346 } 347 348 static TCGv get_gprh(DisasContext *ctx, int reg_num) 349 { 350 assert(get_xl(ctx) == MXL_RV128); 351 if (reg_num == 0) { 352 return ctx->zero; 353 } 354 return cpu_gprh[reg_num]; 355 } 356 357 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 358 { 359 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 360 return temp_new(ctx); 361 } 362 return cpu_gpr[reg_num]; 363 } 364 365 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 366 { 367 if (reg_num == 0) { 368 return temp_new(ctx); 369 } 370 return cpu_gprh[reg_num]; 371 } 372 373 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 374 { 375 if (reg_num != 0) { 376 switch (get_ol(ctx)) { 377 case MXL_RV32: 378 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 379 break; 380 case MXL_RV64: 381 case MXL_RV128: 382 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 383 break; 384 default: 385 g_assert_not_reached(); 386 } 387 388 if (get_xl_max(ctx) == MXL_RV128) { 389 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 390 } 391 } 392 } 393 394 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 395 { 396 if (reg_num != 0) { 397 switch (get_ol(ctx)) { 398 case MXL_RV32: 399 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 400 break; 401 case MXL_RV64: 402 case MXL_RV128: 403 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 404 break; 405 default: 406 g_assert_not_reached(); 407 } 408 409 if (get_xl_max(ctx) == MXL_RV128) { 410 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 411 } 412 } 413 } 414 415 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 416 { 417 assert(get_ol(ctx) == MXL_RV128); 418 if (reg_num != 0) { 419 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 420 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 421 } 422 } 423 424 static TCGv_i64 ftemp_new(DisasContext *ctx) 425 { 426 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 427 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 428 } 429 430 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 431 { 432 if (!ctx->cfg_ptr->ext_zfinx) { 433 return cpu_fpr[reg_num]; 434 } 435 436 if (reg_num == 0) { 437 return tcg_constant_i64(0); 438 } 439 switch (get_xl(ctx)) { 440 case MXL_RV32: 441 #ifdef TARGET_RISCV32 442 { 443 TCGv_i64 t = ftemp_new(ctx); 444 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 445 return t; 446 } 447 #else 448 /* fall through */ 449 case MXL_RV64: 450 return cpu_gpr[reg_num]; 451 #endif 452 default: 453 g_assert_not_reached(); 454 } 455 } 456 457 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 458 { 459 if (!ctx->cfg_ptr->ext_zfinx) { 460 return cpu_fpr[reg_num]; 461 } 462 463 if (reg_num == 0) { 464 return tcg_constant_i64(0); 465 } 466 switch (get_xl(ctx)) { 467 case MXL_RV32: 468 { 469 TCGv_i64 t = ftemp_new(ctx); 470 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 471 return t; 472 } 473 #ifdef TARGET_RISCV64 474 case MXL_RV64: 475 return cpu_gpr[reg_num]; 476 #endif 477 default: 478 g_assert_not_reached(); 479 } 480 } 481 482 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 483 { 484 if (!ctx->cfg_ptr->ext_zfinx) { 485 return cpu_fpr[reg_num]; 486 } 487 488 if (reg_num == 0) { 489 return ftemp_new(ctx); 490 } 491 492 switch (get_xl(ctx)) { 493 case MXL_RV32: 494 return ftemp_new(ctx); 495 #ifdef TARGET_RISCV64 496 case MXL_RV64: 497 return cpu_gpr[reg_num]; 498 #endif 499 default: 500 g_assert_not_reached(); 501 } 502 } 503 504 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 505 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 506 { 507 if (!ctx->cfg_ptr->ext_zfinx) { 508 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 509 return; 510 } 511 if (reg_num != 0) { 512 switch (get_xl(ctx)) { 513 case MXL_RV32: 514 #ifdef TARGET_RISCV32 515 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 516 break; 517 #else 518 /* fall through */ 519 case MXL_RV64: 520 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 521 break; 522 #endif 523 default: 524 g_assert_not_reached(); 525 } 526 } 527 } 528 529 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 530 { 531 if (!ctx->cfg_ptr->ext_zfinx) { 532 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 533 return; 534 } 535 536 if (reg_num != 0) { 537 switch (get_xl(ctx)) { 538 case MXL_RV32: 539 #ifdef TARGET_RISCV32 540 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 541 break; 542 #else 543 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 544 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 545 break; 546 case MXL_RV64: 547 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 548 break; 549 #endif 550 default: 551 g_assert_not_reached(); 552 } 553 } 554 } 555 556 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 557 { 558 target_ulong next_pc; 559 560 /* check misaligned: */ 561 next_pc = ctx->base.pc_next + imm; 562 if (!has_ext(ctx, RVC)) { 563 if ((next_pc & 0x3) != 0) { 564 gen_exception_inst_addr_mis(ctx); 565 return; 566 } 567 } 568 569 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 570 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 571 ctx->base.is_jmp = DISAS_NORETURN; 572 } 573 574 /* Compute a canonical address from a register plus offset. */ 575 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 576 { 577 TCGv addr = temp_new(ctx); 578 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 579 580 tcg_gen_addi_tl(addr, src1, imm); 581 if (ctx->pm_mask_enabled) { 582 tcg_gen_andc_tl(addr, addr, pm_mask); 583 } else if (get_xl(ctx) == MXL_RV32) { 584 tcg_gen_ext32u_tl(addr, addr); 585 } 586 if (ctx->pm_base_enabled) { 587 tcg_gen_or_tl(addr, addr, pm_base); 588 } 589 return addr; 590 } 591 592 #ifndef CONFIG_USER_ONLY 593 /* The states of mstatus_fs are: 594 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 595 * We will have already diagnosed disabled state, 596 * and need to turn initial/clean into dirty. 597 */ 598 static void mark_fs_dirty(DisasContext *ctx) 599 { 600 TCGv tmp; 601 602 if (!has_ext(ctx, RVF)) { 603 return; 604 } 605 606 if (ctx->mstatus_fs != MSTATUS_FS) { 607 /* Remember the state change for the rest of the TB. */ 608 ctx->mstatus_fs = MSTATUS_FS; 609 610 tmp = tcg_temp_new(); 611 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 612 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 613 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 614 tcg_temp_free(tmp); 615 } 616 617 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 618 /* Remember the stage change for the rest of the TB. */ 619 ctx->mstatus_hs_fs = MSTATUS_FS; 620 621 tmp = tcg_temp_new(); 622 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 623 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 624 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 625 tcg_temp_free(tmp); 626 } 627 } 628 #else 629 static inline void mark_fs_dirty(DisasContext *ctx) { } 630 #endif 631 632 #ifndef CONFIG_USER_ONLY 633 /* The states of mstatus_vs are: 634 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 635 * We will have already diagnosed disabled state, 636 * and need to turn initial/clean into dirty. 637 */ 638 static void mark_vs_dirty(DisasContext *ctx) 639 { 640 TCGv tmp; 641 642 if (ctx->mstatus_vs != MSTATUS_VS) { 643 /* Remember the state change for the rest of the TB. */ 644 ctx->mstatus_vs = MSTATUS_VS; 645 646 tmp = tcg_temp_new(); 647 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 648 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 649 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 650 tcg_temp_free(tmp); 651 } 652 653 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 654 /* Remember the stage change for the rest of the TB. */ 655 ctx->mstatus_hs_vs = MSTATUS_VS; 656 657 tmp = tcg_temp_new(); 658 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 659 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 660 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 661 tcg_temp_free(tmp); 662 } 663 } 664 #else 665 static inline void mark_vs_dirty(DisasContext *ctx) { } 666 #endif 667 668 static void gen_set_rm(DisasContext *ctx, int rm) 669 { 670 if (ctx->frm == rm) { 671 return; 672 } 673 ctx->frm = rm; 674 675 if (rm == RISCV_FRM_DYN) { 676 /* The helper will return only if frm valid. */ 677 ctx->frm_valid = true; 678 } 679 680 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 681 decode_save_opc(ctx); 682 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 683 } 684 685 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 686 { 687 if (ctx->frm == rm && ctx->frm_valid) { 688 return; 689 } 690 ctx->frm = rm; 691 ctx->frm_valid = true; 692 693 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 694 decode_save_opc(ctx); 695 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 696 } 697 698 static int ex_plus_1(DisasContext *ctx, int nf) 699 { 700 return nf + 1; 701 } 702 703 #define EX_SH(amount) \ 704 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 705 { \ 706 return imm << amount; \ 707 } 708 EX_SH(1) 709 EX_SH(2) 710 EX_SH(3) 711 EX_SH(4) 712 EX_SH(12) 713 714 #define REQUIRE_EXT(ctx, ext) do { \ 715 if (!has_ext(ctx, ext)) { \ 716 return false; \ 717 } \ 718 } while (0) 719 720 #define REQUIRE_32BIT(ctx) do { \ 721 if (get_xl(ctx) != MXL_RV32) { \ 722 return false; \ 723 } \ 724 } while (0) 725 726 #define REQUIRE_64BIT(ctx) do { \ 727 if (get_xl(ctx) != MXL_RV64) { \ 728 return false; \ 729 } \ 730 } while (0) 731 732 #define REQUIRE_128BIT(ctx) do { \ 733 if (get_xl(ctx) != MXL_RV128) { \ 734 return false; \ 735 } \ 736 } while (0) 737 738 #define REQUIRE_64_OR_128BIT(ctx) do { \ 739 if (get_xl(ctx) == MXL_RV32) { \ 740 return false; \ 741 } \ 742 } while (0) 743 744 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 745 if (!ctx->cfg_ptr->ext_##A && \ 746 !ctx->cfg_ptr->ext_##B) { \ 747 return false; \ 748 } \ 749 } while (0) 750 751 static int ex_rvc_register(DisasContext *ctx, int reg) 752 { 753 return 8 + reg; 754 } 755 756 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 757 { 758 /* For RV128 a shamt of 0 means a shift by 64. */ 759 if (get_ol(ctx) == MXL_RV128) { 760 imm = imm ? imm : 64; 761 } 762 return imm; 763 } 764 765 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 766 { 767 /* 768 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 769 * shifts, the shamt is sign-extended. 770 */ 771 if (get_ol(ctx) == MXL_RV128) { 772 imm = imm | (imm & 32) << 1; 773 imm = imm ? imm : 64; 774 } 775 return imm; 776 } 777 778 /* Include the auto-generated decoder for 32 bit insn */ 779 #include "decode-insn32.c.inc" 780 781 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 782 void (*func)(TCGv, TCGv, target_long)) 783 { 784 TCGv dest = dest_gpr(ctx, a->rd); 785 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 786 787 func(dest, src1, a->imm); 788 789 if (get_xl(ctx) == MXL_RV128) { 790 TCGv src1h = get_gprh(ctx, a->rs1); 791 TCGv desth = dest_gprh(ctx, a->rd); 792 793 func(desth, src1h, -(a->imm < 0)); 794 gen_set_gpr128(ctx, a->rd, dest, desth); 795 } else { 796 gen_set_gpr(ctx, a->rd, dest); 797 } 798 799 return true; 800 } 801 802 static bool gen_logic(DisasContext *ctx, arg_r *a, 803 void (*func)(TCGv, TCGv, TCGv)) 804 { 805 TCGv dest = dest_gpr(ctx, a->rd); 806 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 807 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 808 809 func(dest, src1, src2); 810 811 if (get_xl(ctx) == MXL_RV128) { 812 TCGv src1h = get_gprh(ctx, a->rs1); 813 TCGv src2h = get_gprh(ctx, a->rs2); 814 TCGv desth = dest_gprh(ctx, a->rd); 815 816 func(desth, src1h, src2h); 817 gen_set_gpr128(ctx, a->rd, dest, desth); 818 } else { 819 gen_set_gpr(ctx, a->rd, dest); 820 } 821 822 return true; 823 } 824 825 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 826 void (*func)(TCGv, TCGv, target_long), 827 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 828 { 829 TCGv dest = dest_gpr(ctx, a->rd); 830 TCGv src1 = get_gpr(ctx, a->rs1, ext); 831 832 if (get_ol(ctx) < MXL_RV128) { 833 func(dest, src1, a->imm); 834 gen_set_gpr(ctx, a->rd, dest); 835 } else { 836 if (f128 == NULL) { 837 return false; 838 } 839 840 TCGv src1h = get_gprh(ctx, a->rs1); 841 TCGv desth = dest_gprh(ctx, a->rd); 842 843 f128(dest, desth, src1, src1h, a->imm); 844 gen_set_gpr128(ctx, a->rd, dest, desth); 845 } 846 return true; 847 } 848 849 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 850 void (*func)(TCGv, TCGv, TCGv), 851 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 852 { 853 TCGv dest = dest_gpr(ctx, a->rd); 854 TCGv src1 = get_gpr(ctx, a->rs1, ext); 855 TCGv src2 = tcg_constant_tl(a->imm); 856 857 if (get_ol(ctx) < MXL_RV128) { 858 func(dest, src1, src2); 859 gen_set_gpr(ctx, a->rd, dest); 860 } else { 861 if (f128 == NULL) { 862 return false; 863 } 864 865 TCGv src1h = get_gprh(ctx, a->rs1); 866 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 867 TCGv desth = dest_gprh(ctx, a->rd); 868 869 f128(dest, desth, src1, src1h, src2, src2h); 870 gen_set_gpr128(ctx, a->rd, dest, desth); 871 } 872 return true; 873 } 874 875 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 876 void (*func)(TCGv, TCGv, TCGv), 877 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 878 { 879 TCGv dest = dest_gpr(ctx, a->rd); 880 TCGv src1 = get_gpr(ctx, a->rs1, ext); 881 TCGv src2 = get_gpr(ctx, a->rs2, ext); 882 883 if (get_ol(ctx) < MXL_RV128) { 884 func(dest, src1, src2); 885 gen_set_gpr(ctx, a->rd, dest); 886 } else { 887 if (f128 == NULL) { 888 return false; 889 } 890 891 TCGv src1h = get_gprh(ctx, a->rs1); 892 TCGv src2h = get_gprh(ctx, a->rs2); 893 TCGv desth = dest_gprh(ctx, a->rd); 894 895 f128(dest, desth, src1, src1h, src2, src2h); 896 gen_set_gpr128(ctx, a->rd, dest, desth); 897 } 898 return true; 899 } 900 901 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 902 void (*f_tl)(TCGv, TCGv, TCGv), 903 void (*f_32)(TCGv, TCGv, TCGv), 904 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 905 { 906 int olen = get_olen(ctx); 907 908 if (olen != TARGET_LONG_BITS) { 909 if (olen == 32) { 910 f_tl = f_32; 911 } else if (olen != 128) { 912 g_assert_not_reached(); 913 } 914 } 915 return gen_arith(ctx, a, ext, f_tl, f_128); 916 } 917 918 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 919 void (*func)(TCGv, TCGv, target_long), 920 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 921 { 922 TCGv dest, src1; 923 int max_len = get_olen(ctx); 924 925 if (a->shamt >= max_len) { 926 return false; 927 } 928 929 dest = dest_gpr(ctx, a->rd); 930 src1 = get_gpr(ctx, a->rs1, ext); 931 932 if (max_len < 128) { 933 func(dest, src1, a->shamt); 934 gen_set_gpr(ctx, a->rd, dest); 935 } else { 936 TCGv src1h = get_gprh(ctx, a->rs1); 937 TCGv desth = dest_gprh(ctx, a->rd); 938 939 if (f128 == NULL) { 940 return false; 941 } 942 f128(dest, desth, src1, src1h, a->shamt); 943 gen_set_gpr128(ctx, a->rd, dest, desth); 944 } 945 return true; 946 } 947 948 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 949 DisasExtend ext, 950 void (*f_tl)(TCGv, TCGv, target_long), 951 void (*f_32)(TCGv, TCGv, target_long), 952 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 953 target_long)) 954 { 955 int olen = get_olen(ctx); 956 if (olen != TARGET_LONG_BITS) { 957 if (olen == 32) { 958 f_tl = f_32; 959 } else if (olen != 128) { 960 g_assert_not_reached(); 961 } 962 } 963 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 964 } 965 966 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 967 void (*func)(TCGv, TCGv, TCGv)) 968 { 969 TCGv dest, src1, src2; 970 int max_len = get_olen(ctx); 971 972 if (a->shamt >= max_len) { 973 return false; 974 } 975 976 dest = dest_gpr(ctx, a->rd); 977 src1 = get_gpr(ctx, a->rs1, ext); 978 src2 = tcg_constant_tl(a->shamt); 979 980 func(dest, src1, src2); 981 982 gen_set_gpr(ctx, a->rd, dest); 983 return true; 984 } 985 986 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 987 void (*func)(TCGv, TCGv, TCGv), 988 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 989 { 990 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 991 TCGv ext2 = tcg_temp_new(); 992 int max_len = get_olen(ctx); 993 994 tcg_gen_andi_tl(ext2, src2, max_len - 1); 995 996 TCGv dest = dest_gpr(ctx, a->rd); 997 TCGv src1 = get_gpr(ctx, a->rs1, ext); 998 999 if (max_len < 128) { 1000 func(dest, src1, ext2); 1001 gen_set_gpr(ctx, a->rd, dest); 1002 } else { 1003 TCGv src1h = get_gprh(ctx, a->rs1); 1004 TCGv desth = dest_gprh(ctx, a->rd); 1005 1006 if (f128 == NULL) { 1007 return false; 1008 } 1009 f128(dest, desth, src1, src1h, ext2); 1010 gen_set_gpr128(ctx, a->rd, dest, desth); 1011 } 1012 tcg_temp_free(ext2); 1013 return true; 1014 } 1015 1016 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1017 void (*f_tl)(TCGv, TCGv, TCGv), 1018 void (*f_32)(TCGv, TCGv, TCGv), 1019 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1020 { 1021 int olen = get_olen(ctx); 1022 if (olen != TARGET_LONG_BITS) { 1023 if (olen == 32) { 1024 f_tl = f_32; 1025 } else if (olen != 128) { 1026 g_assert_not_reached(); 1027 } 1028 } 1029 return gen_shift(ctx, a, ext, f_tl, f_128); 1030 } 1031 1032 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1033 void (*func)(TCGv, TCGv)) 1034 { 1035 TCGv dest = dest_gpr(ctx, a->rd); 1036 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1037 1038 func(dest, src1); 1039 1040 gen_set_gpr(ctx, a->rd, dest); 1041 return true; 1042 } 1043 1044 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1045 void (*f_tl)(TCGv, TCGv), 1046 void (*f_32)(TCGv, TCGv)) 1047 { 1048 int olen = get_olen(ctx); 1049 1050 if (olen != TARGET_LONG_BITS) { 1051 if (olen == 32) { 1052 f_tl = f_32; 1053 } else { 1054 g_assert_not_reached(); 1055 } 1056 } 1057 return gen_unary(ctx, a, ext, f_tl); 1058 } 1059 1060 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1061 { 1062 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1063 CPUState *cpu = ctx->cs; 1064 CPURISCVState *env = cpu->env_ptr; 1065 1066 return cpu_ldl_code(env, pc); 1067 } 1068 1069 /* Include insn module translation function */ 1070 #include "insn_trans/trans_rvi.c.inc" 1071 #include "insn_trans/trans_rvm.c.inc" 1072 #include "insn_trans/trans_rva.c.inc" 1073 #include "insn_trans/trans_rvf.c.inc" 1074 #include "insn_trans/trans_rvd.c.inc" 1075 #include "insn_trans/trans_rvh.c.inc" 1076 #include "insn_trans/trans_rvv.c.inc" 1077 #include "insn_trans/trans_rvb.c.inc" 1078 #include "insn_trans/trans_rvzawrs.c.inc" 1079 #include "insn_trans/trans_rvzfh.c.inc" 1080 #include "insn_trans/trans_rvk.c.inc" 1081 #include "insn_trans/trans_privileged.c.inc" 1082 #include "insn_trans/trans_svinval.c.inc" 1083 #include "insn_trans/trans_xventanacondops.c.inc" 1084 1085 /* Include the auto-generated decoder for 16 bit insn */ 1086 #include "decode-insn16.c.inc" 1087 /* Include decoders for factored-out extensions */ 1088 #include "decode-XVentanaCondOps.c.inc" 1089 1090 /* The specification allows for longer insns, but not supported by qemu. */ 1091 #define MAX_INSN_LEN 4 1092 1093 static inline int insn_len(uint16_t first_word) 1094 { 1095 return (first_word & 3) == 3 ? 4 : 2; 1096 } 1097 1098 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1099 { 1100 /* 1101 * A table with predicate (i.e., guard) functions and decoder functions 1102 * that are tested in-order until a decoder matches onto the opcode. 1103 */ 1104 static const struct { 1105 bool (*guard_func)(DisasContext *); 1106 bool (*decode_func)(DisasContext *, uint32_t); 1107 } decoders[] = { 1108 { always_true_p, decode_insn32 }, 1109 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1110 }; 1111 1112 ctx->virt_inst_excp = false; 1113 /* Check for compressed insn */ 1114 if (insn_len(opcode) == 2) { 1115 ctx->opcode = opcode; 1116 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1117 if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { 1118 return; 1119 } 1120 } else { 1121 uint32_t opcode32 = opcode; 1122 opcode32 = deposit32(opcode32, 16, 16, 1123 translator_lduw(env, &ctx->base, 1124 ctx->base.pc_next + 2)); 1125 ctx->opcode = opcode32; 1126 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1127 1128 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1129 if (decoders[i].guard_func(ctx) && 1130 decoders[i].decode_func(ctx, opcode32)) { 1131 return; 1132 } 1133 } 1134 } 1135 1136 gen_exception_illegal(ctx); 1137 } 1138 1139 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1140 { 1141 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1142 CPURISCVState *env = cs->env_ptr; 1143 RISCVCPU *cpu = RISCV_CPU(cs); 1144 uint32_t tb_flags = ctx->base.tb->flags; 1145 1146 ctx->pc_succ_insn = ctx->base.pc_first; 1147 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1148 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1149 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1150 ctx->priv_ver = env->priv_ver; 1151 #if !defined(CONFIG_USER_ONLY) 1152 if (riscv_has_ext(env, RVH)) { 1153 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1154 } else { 1155 ctx->virt_enabled = false; 1156 } 1157 #else 1158 ctx->virt_enabled = false; 1159 #endif 1160 ctx->misa_ext = env->misa_ext; 1161 ctx->frm = -1; /* unknown rounding mode */ 1162 ctx->cfg_ptr = &(cpu->cfg); 1163 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1164 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1165 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1166 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1167 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1168 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1169 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1170 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1171 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1172 ctx->vstart = env->vstart; 1173 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1174 ctx->misa_mxl_max = env->misa_mxl_max; 1175 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1176 ctx->cs = cs; 1177 ctx->ntemp = 0; 1178 memset(ctx->temp, 0, sizeof(ctx->temp)); 1179 ctx->nftemp = 0; 1180 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1181 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1182 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1183 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1184 ctx->zero = tcg_constant_tl(0); 1185 } 1186 1187 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1188 { 1189 } 1190 1191 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1192 { 1193 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1194 1195 tcg_gen_insn_start(ctx->base.pc_next, 0); 1196 ctx->insn_start = tcg_last_op(); 1197 } 1198 1199 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1200 { 1201 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1202 CPURISCVState *env = cpu->env_ptr; 1203 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1204 int i; 1205 1206 ctx->ol = ctx->xl; 1207 decode_opc(env, ctx, opcode16); 1208 ctx->base.pc_next = ctx->pc_succ_insn; 1209 1210 for (i = ctx->ntemp - 1; i >= 0; --i) { 1211 tcg_temp_free(ctx->temp[i]); 1212 ctx->temp[i] = NULL; 1213 } 1214 ctx->ntemp = 0; 1215 for (i = ctx->nftemp - 1; i >= 0; --i) { 1216 tcg_temp_free_i64(ctx->ftemp[i]); 1217 ctx->ftemp[i] = NULL; 1218 } 1219 ctx->nftemp = 0; 1220 1221 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1222 if (ctx->base.is_jmp == DISAS_NEXT) { 1223 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1224 ctx->base.is_jmp = DISAS_TOO_MANY; 1225 } else { 1226 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1227 1228 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1229 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1230 int len = insn_len(next_insn); 1231 1232 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1233 ctx->base.is_jmp = DISAS_TOO_MANY; 1234 } 1235 } 1236 } 1237 } 1238 } 1239 1240 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1241 { 1242 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1243 1244 switch (ctx->base.is_jmp) { 1245 case DISAS_TOO_MANY: 1246 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1247 break; 1248 case DISAS_NORETURN: 1249 break; 1250 default: 1251 g_assert_not_reached(); 1252 } 1253 } 1254 1255 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1256 CPUState *cpu, FILE *logfile) 1257 { 1258 #ifndef CONFIG_USER_ONLY 1259 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1260 CPURISCVState *env = &rvcpu->env; 1261 #endif 1262 1263 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1264 #ifndef CONFIG_USER_ONLY 1265 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1266 env->priv, env->virt); 1267 #endif 1268 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1269 } 1270 1271 static const TranslatorOps riscv_tr_ops = { 1272 .init_disas_context = riscv_tr_init_disas_context, 1273 .tb_start = riscv_tr_tb_start, 1274 .insn_start = riscv_tr_insn_start, 1275 .translate_insn = riscv_tr_translate_insn, 1276 .tb_stop = riscv_tr_tb_stop, 1277 .disas_log = riscv_tr_disas_log, 1278 }; 1279 1280 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1281 target_ulong pc, void *host_pc) 1282 { 1283 DisasContext ctx; 1284 1285 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1286 } 1287 1288 void riscv_translate_init(void) 1289 { 1290 int i; 1291 1292 /* 1293 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1294 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1295 * unless you specifically block reads/writes to reg 0. 1296 */ 1297 cpu_gpr[0] = NULL; 1298 cpu_gprh[0] = NULL; 1299 1300 for (i = 1; i < 32; i++) { 1301 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1302 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1303 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1304 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1305 } 1306 1307 for (i = 0; i < 32; i++) { 1308 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1309 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1310 } 1311 1312 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1313 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1314 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1315 "vstart"); 1316 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1317 "load_res"); 1318 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1319 "load_val"); 1320 /* Assign PM CSRs to tcg globals */ 1321 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1322 "pmmask"); 1323 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1324 "pmbase"); 1325 } 1326