1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 34 /* global register indices */ 35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl; 36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 37 static TCGv load_res; 38 static TCGv load_val; 39 40 #include "exec/gen-icount.h" 41 42 /* 43 * If an operation is being performed on less than TARGET_LONG_BITS, 44 * it may require the inputs to be sign- or zero-extended; which will 45 * depend on the exact operation being performed. 46 */ 47 typedef enum { 48 EXT_NONE, 49 EXT_SIGN, 50 EXT_ZERO, 51 } DisasExtend; 52 53 typedef struct DisasContext { 54 DisasContextBase base; 55 /* pc_succ_insn points to the instruction following base.pc_next */ 56 target_ulong pc_succ_insn; 57 target_ulong priv_ver; 58 target_ulong misa; 59 uint32_t opcode; 60 uint32_t mstatus_fs; 61 uint32_t mem_idx; 62 /* Remember the rounding mode encoded in the previous fp instruction, 63 which we have already installed into env->fp_status. Or -1 for 64 no previous fp instruction. Note that we exit the TB when writing 65 to any system register, which includes CSR_FRM, so we do not have 66 to reset this known value. */ 67 int frm; 68 bool w; 69 bool virt_enabled; 70 bool ext_ifencei; 71 bool hlsx; 72 /* vector extension */ 73 bool vill; 74 uint8_t lmul; 75 uint8_t sew; 76 uint16_t vlen; 77 uint16_t mlen; 78 bool vl_eq_vlmax; 79 uint8_t ntemp; 80 CPUState *cs; 81 TCGv zero; 82 /* Space for 3 operands plus 1 extra for address computation. */ 83 TCGv temp[4]; 84 } DisasContext; 85 86 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 87 { 88 return ctx->misa & ext; 89 } 90 91 #ifdef TARGET_RISCV32 92 # define is_32bit(ctx) true 93 #elif defined(CONFIG_USER_ONLY) 94 # define is_32bit(ctx) false 95 #else 96 static inline bool is_32bit(DisasContext *ctx) 97 { 98 return (ctx->misa & RV32) == RV32; 99 } 100 #endif 101 102 /* 103 * RISC-V requires NaN-boxing of narrower width floating point values. 104 * This applies when a 32-bit value is assigned to a 64-bit FP register. 105 * For consistency and simplicity, we nanbox results even when the RVD 106 * extension is not present. 107 */ 108 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 109 { 110 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 111 } 112 113 /* 114 * A narrow n-bit operation, where n < FLEN, checks that input operands 115 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 116 * If so, the least-significant bits of the input are used, otherwise the 117 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 118 * 119 * Here, the result is always nan-boxed, even the canonical nan. 120 */ 121 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 122 { 123 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 124 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 125 126 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 127 } 128 129 static void generate_exception(DisasContext *ctx, int excp) 130 { 131 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 132 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 133 ctx->base.is_jmp = DISAS_NORETURN; 134 } 135 136 static void generate_exception_mtval(DisasContext *ctx, int excp) 137 { 138 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 139 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 140 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 141 ctx->base.is_jmp = DISAS_NORETURN; 142 } 143 144 static void gen_exception_debug(void) 145 { 146 gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG)); 147 } 148 149 /* Wrapper around tcg_gen_exit_tb that handles single stepping */ 150 static void exit_tb(DisasContext *ctx) 151 { 152 if (ctx->base.singlestep_enabled) { 153 gen_exception_debug(); 154 } else { 155 tcg_gen_exit_tb(NULL, 0); 156 } 157 } 158 159 /* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */ 160 static void lookup_and_goto_ptr(DisasContext *ctx) 161 { 162 if (ctx->base.singlestep_enabled) { 163 gen_exception_debug(); 164 } else { 165 tcg_gen_lookup_and_goto_ptr(); 166 } 167 } 168 169 static void gen_exception_illegal(DisasContext *ctx) 170 { 171 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 172 } 173 174 static void gen_exception_inst_addr_mis(DisasContext *ctx) 175 { 176 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 177 } 178 179 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 180 { 181 if (translator_use_goto_tb(&ctx->base, dest)) { 182 tcg_gen_goto_tb(n); 183 tcg_gen_movi_tl(cpu_pc, dest); 184 tcg_gen_exit_tb(ctx->base.tb, n); 185 } else { 186 tcg_gen_movi_tl(cpu_pc, dest); 187 lookup_and_goto_ptr(ctx); 188 } 189 } 190 191 /* 192 * Wrappers for getting reg values. 193 * 194 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 195 * constant zero as a source, and an uninitialized sink as destination. 196 * 197 * Further, we may provide an extension for word operations. 198 */ 199 static TCGv temp_new(DisasContext *ctx) 200 { 201 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 202 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 203 } 204 205 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 206 { 207 TCGv t; 208 209 if (reg_num == 0) { 210 return ctx->zero; 211 } 212 213 switch (ctx->w ? ext : EXT_NONE) { 214 case EXT_NONE: 215 return cpu_gpr[reg_num]; 216 case EXT_SIGN: 217 t = temp_new(ctx); 218 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 219 return t; 220 case EXT_ZERO: 221 t = temp_new(ctx); 222 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 223 return t; 224 } 225 g_assert_not_reached(); 226 } 227 228 static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) 229 { 230 tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE)); 231 } 232 233 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 234 { 235 if (reg_num == 0 || ctx->w) { 236 return temp_new(ctx); 237 } 238 return cpu_gpr[reg_num]; 239 } 240 241 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 242 { 243 if (reg_num != 0) { 244 if (ctx->w) { 245 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 246 } else { 247 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 248 } 249 } 250 } 251 252 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 253 { 254 target_ulong next_pc; 255 256 /* check misaligned: */ 257 next_pc = ctx->base.pc_next + imm; 258 if (!has_ext(ctx, RVC)) { 259 if ((next_pc & 0x3) != 0) { 260 gen_exception_inst_addr_mis(ctx); 261 return; 262 } 263 } 264 if (rd != 0) { 265 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 266 } 267 268 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 269 ctx->base.is_jmp = DISAS_NORETURN; 270 } 271 272 #ifndef CONFIG_USER_ONLY 273 /* The states of mstatus_fs are: 274 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 275 * We will have already diagnosed disabled state, 276 * and need to turn initial/clean into dirty. 277 */ 278 static void mark_fs_dirty(DisasContext *ctx) 279 { 280 TCGv tmp; 281 target_ulong sd; 282 283 if (ctx->mstatus_fs == MSTATUS_FS) { 284 return; 285 } 286 /* Remember the state change for the rest of the TB. */ 287 ctx->mstatus_fs = MSTATUS_FS; 288 289 tmp = tcg_temp_new(); 290 sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD; 291 292 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 293 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); 294 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 295 296 if (ctx->virt_enabled) { 297 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 298 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd); 299 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 300 } 301 tcg_temp_free(tmp); 302 } 303 #else 304 static inline void mark_fs_dirty(DisasContext *ctx) { } 305 #endif 306 307 static void gen_set_rm(DisasContext *ctx, int rm) 308 { 309 if (ctx->frm == rm) { 310 return; 311 } 312 ctx->frm = rm; 313 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 314 } 315 316 static int ex_plus_1(DisasContext *ctx, int nf) 317 { 318 return nf + 1; 319 } 320 321 #define EX_SH(amount) \ 322 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 323 { \ 324 return imm << amount; \ 325 } 326 EX_SH(1) 327 EX_SH(2) 328 EX_SH(3) 329 EX_SH(4) 330 EX_SH(12) 331 332 #define REQUIRE_EXT(ctx, ext) do { \ 333 if (!has_ext(ctx, ext)) { \ 334 return false; \ 335 } \ 336 } while (0) 337 338 #define REQUIRE_64BIT(ctx) do { \ 339 if (is_32bit(ctx)) { \ 340 return false; \ 341 } \ 342 } while (0) 343 344 static int ex_rvc_register(DisasContext *ctx, int reg) 345 { 346 return 8 + reg; 347 } 348 349 static int ex_rvc_shifti(DisasContext *ctx, int imm) 350 { 351 /* For RV128 a shamt of 0 means a shift by 64. */ 352 return imm ? imm : 64; 353 } 354 355 /* Include the auto-generated decoder for 32 bit insn */ 356 #include "decode-insn32.c.inc" 357 358 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 359 void (*func)(TCGv, TCGv, target_long)) 360 { 361 TCGv dest = dest_gpr(ctx, a->rd); 362 TCGv src1 = get_gpr(ctx, a->rs1, ext); 363 364 func(dest, src1, a->imm); 365 366 gen_set_gpr(ctx, a->rd, dest); 367 return true; 368 } 369 370 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 371 void (*func)(TCGv, TCGv, TCGv)) 372 { 373 TCGv dest = dest_gpr(ctx, a->rd); 374 TCGv src1 = get_gpr(ctx, a->rs1, ext); 375 TCGv src2 = tcg_constant_tl(a->imm); 376 377 func(dest, src1, src2); 378 379 gen_set_gpr(ctx, a->rd, dest); 380 return true; 381 } 382 383 static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2) 384 { 385 tcg_gen_deposit_tl(ret, arg1, arg2, 386 TARGET_LONG_BITS / 2, 387 TARGET_LONG_BITS / 2); 388 } 389 390 static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2) 391 { 392 TCGv t = tcg_temp_new(); 393 tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2); 394 tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2); 395 tcg_temp_free(t); 396 } 397 398 static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2) 399 { 400 TCGv t = tcg_temp_new(); 401 tcg_gen_ext8u_tl(t, arg2); 402 tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8); 403 tcg_temp_free(t); 404 } 405 406 static void gen_sbop_mask(TCGv ret, TCGv shamt) 407 { 408 tcg_gen_movi_tl(ret, 1); 409 tcg_gen_shl_tl(ret, ret, shamt); 410 } 411 412 static void gen_bset(TCGv ret, TCGv arg1, TCGv shamt) 413 { 414 TCGv t = tcg_temp_new(); 415 416 gen_sbop_mask(t, shamt); 417 tcg_gen_or_tl(ret, arg1, t); 418 419 tcg_temp_free(t); 420 } 421 422 static void gen_bclr(TCGv ret, TCGv arg1, TCGv shamt) 423 { 424 TCGv t = tcg_temp_new(); 425 426 gen_sbop_mask(t, shamt); 427 tcg_gen_andc_tl(ret, arg1, t); 428 429 tcg_temp_free(t); 430 } 431 432 static void gen_binv(TCGv ret, TCGv arg1, TCGv shamt) 433 { 434 TCGv t = tcg_temp_new(); 435 436 gen_sbop_mask(t, shamt); 437 tcg_gen_xor_tl(ret, arg1, t); 438 439 tcg_temp_free(t); 440 } 441 442 static void gen_bext(TCGv ret, TCGv arg1, TCGv shamt) 443 { 444 tcg_gen_shr_tl(ret, arg1, shamt); 445 tcg_gen_andi_tl(ret, ret, 1); 446 } 447 448 static void gen_slo(TCGv ret, TCGv arg1, TCGv arg2) 449 { 450 tcg_gen_not_tl(ret, arg1); 451 tcg_gen_shl_tl(ret, ret, arg2); 452 tcg_gen_not_tl(ret, ret); 453 } 454 455 static void gen_sro(TCGv ret, TCGv arg1, TCGv arg2) 456 { 457 tcg_gen_not_tl(ret, arg1); 458 tcg_gen_shr_tl(ret, ret, arg2); 459 tcg_gen_not_tl(ret, ret); 460 } 461 462 static bool gen_grevi(DisasContext *ctx, arg_grevi *a) 463 { 464 TCGv source1 = tcg_temp_new(); 465 TCGv source2; 466 467 gen_get_gpr(ctx, source1, a->rs1); 468 469 if (a->shamt == (TARGET_LONG_BITS - 8)) { 470 /* rev8, byte swaps */ 471 tcg_gen_bswap_tl(source1, source1); 472 } else { 473 source2 = tcg_temp_new(); 474 tcg_gen_movi_tl(source2, a->shamt); 475 gen_helper_grev(source1, source1, source2); 476 tcg_temp_free(source2); 477 } 478 479 gen_set_gpr(ctx, a->rd, source1); 480 tcg_temp_free(source1); 481 return true; 482 } 483 484 #define GEN_SHADD(SHAMT) \ 485 static void gen_sh##SHAMT##add(TCGv ret, TCGv arg1, TCGv arg2) \ 486 { \ 487 TCGv t = tcg_temp_new(); \ 488 \ 489 tcg_gen_shli_tl(t, arg1, SHAMT); \ 490 tcg_gen_add_tl(ret, t, arg2); \ 491 \ 492 tcg_temp_free(t); \ 493 } 494 495 GEN_SHADD(1) 496 GEN_SHADD(2) 497 GEN_SHADD(3) 498 499 static void gen_ctzw(TCGv ret, TCGv arg1) 500 { 501 tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32)); 502 tcg_gen_ctzi_tl(ret, ret, 64); 503 } 504 505 static void gen_clzw(TCGv ret, TCGv arg1) 506 { 507 tcg_gen_ext32u_tl(ret, arg1); 508 tcg_gen_clzi_tl(ret, ret, 64); 509 tcg_gen_subi_tl(ret, ret, 32); 510 } 511 512 static void gen_cpopw(TCGv ret, TCGv arg1) 513 { 514 tcg_gen_ext32u_tl(arg1, arg1); 515 tcg_gen_ctpop_tl(ret, arg1); 516 } 517 518 static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2) 519 { 520 TCGv t = tcg_temp_new(); 521 tcg_gen_ext16s_tl(t, arg2); 522 tcg_gen_deposit_tl(ret, arg1, t, 16, 48); 523 tcg_temp_free(t); 524 } 525 526 static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2) 527 { 528 TCGv t = tcg_temp_new(); 529 tcg_gen_shri_tl(t, arg1, 16); 530 tcg_gen_deposit_tl(ret, arg2, t, 0, 16); 531 tcg_gen_ext32s_tl(ret, ret); 532 tcg_temp_free(t); 533 } 534 535 static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2) 536 { 537 TCGv_i32 t1 = tcg_temp_new_i32(); 538 TCGv_i32 t2 = tcg_temp_new_i32(); 539 540 /* truncate to 32-bits */ 541 tcg_gen_trunc_tl_i32(t1, arg1); 542 tcg_gen_trunc_tl_i32(t2, arg2); 543 544 tcg_gen_rotr_i32(t1, t1, t2); 545 546 /* sign-extend 64-bits */ 547 tcg_gen_ext_i32_tl(ret, t1); 548 549 tcg_temp_free_i32(t1); 550 tcg_temp_free_i32(t2); 551 } 552 553 static void gen_rolw(TCGv ret, TCGv arg1, TCGv arg2) 554 { 555 TCGv_i32 t1 = tcg_temp_new_i32(); 556 TCGv_i32 t2 = tcg_temp_new_i32(); 557 558 /* truncate to 32-bits */ 559 tcg_gen_trunc_tl_i32(t1, arg1); 560 tcg_gen_trunc_tl_i32(t2, arg2); 561 562 tcg_gen_rotl_i32(t1, t1, t2); 563 564 /* sign-extend 64-bits */ 565 tcg_gen_ext_i32_tl(ret, t1); 566 567 tcg_temp_free_i32(t1); 568 tcg_temp_free_i32(t2); 569 } 570 571 static void gen_grevw(TCGv ret, TCGv arg1, TCGv arg2) 572 { 573 tcg_gen_ext32u_tl(arg1, arg1); 574 gen_helper_grev(ret, arg1, arg2); 575 } 576 577 static void gen_gorcw(TCGv ret, TCGv arg1, TCGv arg2) 578 { 579 tcg_gen_ext32u_tl(arg1, arg1); 580 gen_helper_gorcw(ret, arg1, arg2); 581 } 582 583 #define GEN_SHADD_UW(SHAMT) \ 584 static void gen_sh##SHAMT##add_uw(TCGv ret, TCGv arg1, TCGv arg2) \ 585 { \ 586 TCGv t = tcg_temp_new(); \ 587 \ 588 tcg_gen_ext32u_tl(t, arg1); \ 589 \ 590 tcg_gen_shli_tl(t, t, SHAMT); \ 591 tcg_gen_add_tl(ret, t, arg2); \ 592 \ 593 tcg_temp_free(t); \ 594 } 595 596 GEN_SHADD_UW(1) 597 GEN_SHADD_UW(2) 598 GEN_SHADD_UW(3) 599 600 static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) 601 { 602 tcg_gen_ext32u_tl(arg1, arg1); 603 tcg_gen_add_tl(ret, arg1, arg2); 604 } 605 606 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 607 void (*func)(TCGv, TCGv, TCGv)) 608 { 609 TCGv dest = dest_gpr(ctx, a->rd); 610 TCGv src1 = get_gpr(ctx, a->rs1, ext); 611 TCGv src2 = get_gpr(ctx, a->rs2, ext); 612 613 func(dest, src1, src2); 614 615 gen_set_gpr(ctx, a->rd, dest); 616 return true; 617 } 618 619 static bool gen_shift(DisasContext *ctx, arg_r *a, 620 void(*func)(TCGv, TCGv, TCGv)) 621 { 622 TCGv source1 = tcg_temp_new(); 623 TCGv source2 = tcg_temp_new(); 624 625 gen_get_gpr(ctx, source1, a->rs1); 626 gen_get_gpr(ctx, source2, a->rs2); 627 628 tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); 629 (*func)(source1, source1, source2); 630 631 gen_set_gpr(ctx, a->rd, source1); 632 tcg_temp_free(source1); 633 tcg_temp_free(source2); 634 return true; 635 } 636 637 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 638 { 639 DisasContext *ctx = container_of(dcbase, DisasContext, base); 640 CPUState *cpu = ctx->cs; 641 CPURISCVState *env = cpu->env_ptr; 642 643 return cpu_ldl_code(env, pc); 644 } 645 646 static bool gen_shifti(DisasContext *ctx, arg_shift *a, 647 void(*func)(TCGv, TCGv, TCGv)) 648 { 649 if (a->shamt >= TARGET_LONG_BITS) { 650 return false; 651 } 652 653 TCGv source1 = tcg_temp_new(); 654 TCGv source2 = tcg_temp_new(); 655 656 gen_get_gpr(ctx, source1, a->rs1); 657 658 tcg_gen_movi_tl(source2, a->shamt); 659 (*func)(source1, source1, source2); 660 661 gen_set_gpr(ctx, a->rd, source1); 662 tcg_temp_free(source1); 663 tcg_temp_free(source2); 664 return true; 665 } 666 667 static bool gen_shiftw(DisasContext *ctx, arg_r *a, 668 void(*func)(TCGv, TCGv, TCGv)) 669 { 670 TCGv source1 = tcg_temp_new(); 671 TCGv source2 = tcg_temp_new(); 672 673 gen_get_gpr(ctx, source1, a->rs1); 674 gen_get_gpr(ctx, source2, a->rs2); 675 676 tcg_gen_andi_tl(source2, source2, 31); 677 (*func)(source1, source1, source2); 678 tcg_gen_ext32s_tl(source1, source1); 679 680 gen_set_gpr(ctx, a->rd, source1); 681 tcg_temp_free(source1); 682 tcg_temp_free(source2); 683 return true; 684 } 685 686 static bool gen_shiftiw(DisasContext *ctx, arg_shift *a, 687 void(*func)(TCGv, TCGv, TCGv)) 688 { 689 TCGv source1 = tcg_temp_new(); 690 TCGv source2 = tcg_temp_new(); 691 692 gen_get_gpr(ctx, source1, a->rs1); 693 tcg_gen_movi_tl(source2, a->shamt); 694 695 (*func)(source1, source1, source2); 696 tcg_gen_ext32s_tl(source1, source1); 697 698 gen_set_gpr(ctx, a->rd, source1); 699 tcg_temp_free(source1); 700 tcg_temp_free(source2); 701 return true; 702 } 703 704 static void gen_ctz(TCGv ret, TCGv arg1) 705 { 706 tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS); 707 } 708 709 static void gen_clz(TCGv ret, TCGv arg1) 710 { 711 tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS); 712 } 713 714 static bool gen_unary(DisasContext *ctx, arg_r2 *a, 715 void(*func)(TCGv, TCGv)) 716 { 717 TCGv source = tcg_temp_new(); 718 719 gen_get_gpr(ctx, source, a->rs1); 720 721 (*func)(source, source); 722 723 gen_set_gpr(ctx, a->rd, source); 724 tcg_temp_free(source); 725 return true; 726 } 727 728 /* Include insn module translation function */ 729 #include "insn_trans/trans_rvi.c.inc" 730 #include "insn_trans/trans_rvm.c.inc" 731 #include "insn_trans/trans_rva.c.inc" 732 #include "insn_trans/trans_rvf.c.inc" 733 #include "insn_trans/trans_rvd.c.inc" 734 #include "insn_trans/trans_rvh.c.inc" 735 #include "insn_trans/trans_rvv.c.inc" 736 #include "insn_trans/trans_rvb.c.inc" 737 #include "insn_trans/trans_privileged.c.inc" 738 739 /* Include the auto-generated decoder for 16 bit insn */ 740 #include "decode-insn16.c.inc" 741 742 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 743 { 744 /* check for compressed insn */ 745 if (extract16(opcode, 0, 2) != 3) { 746 if (!has_ext(ctx, RVC)) { 747 gen_exception_illegal(ctx); 748 } else { 749 ctx->pc_succ_insn = ctx->base.pc_next + 2; 750 if (!decode_insn16(ctx, opcode)) { 751 gen_exception_illegal(ctx); 752 } 753 } 754 } else { 755 uint32_t opcode32 = opcode; 756 opcode32 = deposit32(opcode32, 16, 16, 757 translator_lduw(env, ctx->base.pc_next + 2)); 758 ctx->pc_succ_insn = ctx->base.pc_next + 4; 759 if (!decode_insn32(ctx, opcode32)) { 760 gen_exception_illegal(ctx); 761 } 762 } 763 } 764 765 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 766 { 767 DisasContext *ctx = container_of(dcbase, DisasContext, base); 768 CPURISCVState *env = cs->env_ptr; 769 RISCVCPU *cpu = RISCV_CPU(cs); 770 uint32_t tb_flags = ctx->base.tb->flags; 771 772 ctx->pc_succ_insn = ctx->base.pc_first; 773 ctx->mem_idx = tb_flags & TB_FLAGS_MMU_MASK; 774 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 775 ctx->priv_ver = env->priv_ver; 776 #if !defined(CONFIG_USER_ONLY) 777 if (riscv_has_ext(env, RVH)) { 778 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 779 } else { 780 ctx->virt_enabled = false; 781 } 782 #else 783 ctx->virt_enabled = false; 784 #endif 785 ctx->misa = env->misa; 786 ctx->frm = -1; /* unknown rounding mode */ 787 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 788 ctx->vlen = cpu->cfg.vlen; 789 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 790 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 791 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 792 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); 793 ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); 794 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 795 ctx->cs = cs; 796 ctx->w = false; 797 ctx->ntemp = 0; 798 memset(ctx->temp, 0, sizeof(ctx->temp)); 799 800 ctx->zero = tcg_constant_tl(0); 801 } 802 803 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 804 { 805 } 806 807 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 808 { 809 DisasContext *ctx = container_of(dcbase, DisasContext, base); 810 811 tcg_gen_insn_start(ctx->base.pc_next); 812 } 813 814 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 815 { 816 DisasContext *ctx = container_of(dcbase, DisasContext, base); 817 CPURISCVState *env = cpu->env_ptr; 818 uint16_t opcode16 = translator_lduw(env, ctx->base.pc_next); 819 820 decode_opc(env, ctx, opcode16); 821 ctx->base.pc_next = ctx->pc_succ_insn; 822 ctx->w = false; 823 824 for (int i = ctx->ntemp - 1; i >= 0; --i) { 825 tcg_temp_free(ctx->temp[i]); 826 ctx->temp[i] = NULL; 827 } 828 ctx->ntemp = 0; 829 830 if (ctx->base.is_jmp == DISAS_NEXT) { 831 target_ulong page_start; 832 833 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 834 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 835 ctx->base.is_jmp = DISAS_TOO_MANY; 836 } 837 } 838 } 839 840 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 841 { 842 DisasContext *ctx = container_of(dcbase, DisasContext, base); 843 844 switch (ctx->base.is_jmp) { 845 case DISAS_TOO_MANY: 846 gen_goto_tb(ctx, 0, ctx->base.pc_next); 847 break; 848 case DISAS_NORETURN: 849 break; 850 default: 851 g_assert_not_reached(); 852 } 853 } 854 855 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 856 { 857 #ifndef CONFIG_USER_ONLY 858 RISCVCPU *rvcpu = RISCV_CPU(cpu); 859 CPURISCVState *env = &rvcpu->env; 860 #endif 861 862 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 863 #ifndef CONFIG_USER_ONLY 864 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 865 #endif 866 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 867 } 868 869 static const TranslatorOps riscv_tr_ops = { 870 .init_disas_context = riscv_tr_init_disas_context, 871 .tb_start = riscv_tr_tb_start, 872 .insn_start = riscv_tr_insn_start, 873 .translate_insn = riscv_tr_translate_insn, 874 .tb_stop = riscv_tr_tb_stop, 875 .disas_log = riscv_tr_disas_log, 876 }; 877 878 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 879 { 880 DisasContext ctx; 881 882 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 883 } 884 885 void riscv_translate_init(void) 886 { 887 int i; 888 889 /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ 890 /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ 891 /* registers, unless you specifically block reads/writes to reg 0 */ 892 cpu_gpr[0] = NULL; 893 894 for (i = 1; i < 32; i++) { 895 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 896 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 897 } 898 899 for (i = 0; i < 32; i++) { 900 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 901 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 902 } 903 904 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 905 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 906 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 907 "load_res"); 908 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 909 "load_val"); 910 } 911