1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_inst_excp; 80 bool virt_enabled; 81 const RISCVCPUConfig *cfg_ptr; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 target_ulong vstart; 103 bool vl_eq_vlmax; 104 uint8_t ntemp; 105 CPUState *cs; 106 TCGv zero; 107 /* Space for 3 operands plus 1 extra for address computation. */ 108 TCGv temp[4]; 109 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 110 TCGv_i64 ftemp[4]; 111 uint8_t nftemp; 112 /* PointerMasking extension */ 113 bool pm_mask_enabled; 114 bool pm_base_enabled; 115 /* Use icount trigger for native debug */ 116 bool itrigger; 117 /* FRM is known to contain a valid value. */ 118 bool frm_valid; 119 /* TCG of the current insn_start */ 120 TCGOp *insn_start; 121 } DisasContext; 122 123 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 124 { 125 return ctx->misa_ext & ext; 126 } 127 128 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 129 { 130 return true; 131 } 132 133 static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) 134 { 135 return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || 136 ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || 137 ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || 138 ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; 139 } 140 141 #define MATERIALISE_EXT_PREDICATE(ext) \ 142 static bool has_ ## ext ## _p(DisasContext *ctx) \ 143 { \ 144 return ctx->cfg_ptr->ext_ ## ext ; \ 145 } 146 147 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 148 149 #ifdef TARGET_RISCV32 150 #define get_xl(ctx) MXL_RV32 151 #elif defined(CONFIG_USER_ONLY) 152 #define get_xl(ctx) MXL_RV64 153 #else 154 #define get_xl(ctx) ((ctx)->xl) 155 #endif 156 157 /* The word size for this machine mode. */ 158 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 159 { 160 return 16 << get_xl(ctx); 161 } 162 163 /* The operation length, as opposed to the xlen. */ 164 #ifdef TARGET_RISCV32 165 #define get_ol(ctx) MXL_RV32 166 #else 167 #define get_ol(ctx) ((ctx)->ol) 168 #endif 169 170 static inline int get_olen(DisasContext *ctx) 171 { 172 return 16 << get_ol(ctx); 173 } 174 175 /* The maximum register length */ 176 #ifdef TARGET_RISCV32 177 #define get_xl_max(ctx) MXL_RV32 178 #else 179 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 180 #endif 181 182 /* 183 * RISC-V requires NaN-boxing of narrower width floating point values. 184 * This applies when a 32-bit value is assigned to a 64-bit FP register. 185 * For consistency and simplicity, we nanbox results even when the RVD 186 * extension is not present. 187 */ 188 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 189 { 190 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 191 } 192 193 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 194 { 195 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 196 } 197 198 /* 199 * A narrow n-bit operation, where n < FLEN, checks that input operands 200 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 201 * If so, the least-significant bits of the input are used, otherwise the 202 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 203 * 204 * Here, the result is always nan-boxed, even the canonical nan. 205 */ 206 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 207 { 208 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 209 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 210 211 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 212 tcg_temp_free_i64(t_max); 213 tcg_temp_free_i64(t_nan); 214 } 215 216 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 217 { 218 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 219 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 220 221 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 222 } 223 224 static void decode_save_opc(DisasContext *ctx) 225 { 226 assert(ctx->insn_start != NULL); 227 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 228 ctx->insn_start = NULL; 229 } 230 231 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 232 { 233 if (get_xl(ctx) == MXL_RV32) { 234 dest = (int32_t)dest; 235 } 236 tcg_gen_movi_tl(cpu_pc, dest); 237 } 238 239 static void gen_set_pc(DisasContext *ctx, TCGv dest) 240 { 241 if (get_xl(ctx) == MXL_RV32) { 242 tcg_gen_ext32s_tl(cpu_pc, dest); 243 } else { 244 tcg_gen_mov_tl(cpu_pc, dest); 245 } 246 } 247 248 static void generate_exception(DisasContext *ctx, int excp) 249 { 250 gen_set_pc_imm(ctx, ctx->base.pc_next); 251 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 252 ctx->base.is_jmp = DISAS_NORETURN; 253 } 254 255 static void gen_exception_illegal(DisasContext *ctx) 256 { 257 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 258 offsetof(CPURISCVState, bins)); 259 if (ctx->virt_inst_excp) { 260 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 261 } else { 262 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 263 } 264 } 265 266 static void gen_exception_inst_addr_mis(DisasContext *ctx) 267 { 268 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 269 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 270 } 271 272 static void lookup_and_goto_ptr(DisasContext *ctx) 273 { 274 #ifndef CONFIG_USER_ONLY 275 if (ctx->itrigger) { 276 gen_helper_itrigger_match(cpu_env); 277 } 278 #endif 279 tcg_gen_lookup_and_goto_ptr(); 280 } 281 282 static void exit_tb(DisasContext *ctx) 283 { 284 #ifndef CONFIG_USER_ONLY 285 if (ctx->itrigger) { 286 gen_helper_itrigger_match(cpu_env); 287 } 288 #endif 289 tcg_gen_exit_tb(NULL, 0); 290 } 291 292 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 293 { 294 /* 295 * Under itrigger, instruction executes one by one like singlestep, 296 * direct block chain benefits will be small. 297 */ 298 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 299 tcg_gen_goto_tb(n); 300 gen_set_pc_imm(ctx, dest); 301 tcg_gen_exit_tb(ctx->base.tb, n); 302 } else { 303 gen_set_pc_imm(ctx, dest); 304 lookup_and_goto_ptr(ctx); 305 } 306 } 307 308 /* 309 * Wrappers for getting reg values. 310 * 311 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 312 * constant zero as a source, and an uninitialized sink as destination. 313 * 314 * Further, we may provide an extension for word operations. 315 */ 316 static TCGv temp_new(DisasContext *ctx) 317 { 318 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 319 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 320 } 321 322 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 323 { 324 TCGv t; 325 326 if (reg_num == 0) { 327 return ctx->zero; 328 } 329 330 switch (get_ol(ctx)) { 331 case MXL_RV32: 332 switch (ext) { 333 case EXT_NONE: 334 break; 335 case EXT_SIGN: 336 t = temp_new(ctx); 337 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 338 return t; 339 case EXT_ZERO: 340 t = temp_new(ctx); 341 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 342 return t; 343 default: 344 g_assert_not_reached(); 345 } 346 break; 347 case MXL_RV64: 348 case MXL_RV128: 349 break; 350 default: 351 g_assert_not_reached(); 352 } 353 return cpu_gpr[reg_num]; 354 } 355 356 static TCGv get_gprh(DisasContext *ctx, int reg_num) 357 { 358 assert(get_xl(ctx) == MXL_RV128); 359 if (reg_num == 0) { 360 return ctx->zero; 361 } 362 return cpu_gprh[reg_num]; 363 } 364 365 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 366 { 367 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 368 return temp_new(ctx); 369 } 370 return cpu_gpr[reg_num]; 371 } 372 373 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 374 { 375 if (reg_num == 0) { 376 return temp_new(ctx); 377 } 378 return cpu_gprh[reg_num]; 379 } 380 381 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 382 { 383 if (reg_num != 0) { 384 switch (get_ol(ctx)) { 385 case MXL_RV32: 386 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 387 break; 388 case MXL_RV64: 389 case MXL_RV128: 390 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 391 break; 392 default: 393 g_assert_not_reached(); 394 } 395 396 if (get_xl_max(ctx) == MXL_RV128) { 397 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 398 } 399 } 400 } 401 402 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 403 { 404 if (reg_num != 0) { 405 switch (get_ol(ctx)) { 406 case MXL_RV32: 407 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 408 break; 409 case MXL_RV64: 410 case MXL_RV128: 411 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 412 break; 413 default: 414 g_assert_not_reached(); 415 } 416 417 if (get_xl_max(ctx) == MXL_RV128) { 418 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 419 } 420 } 421 } 422 423 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 424 { 425 assert(get_ol(ctx) == MXL_RV128); 426 if (reg_num != 0) { 427 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 428 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 429 } 430 } 431 432 static TCGv_i64 ftemp_new(DisasContext *ctx) 433 { 434 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 435 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 436 } 437 438 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 439 { 440 if (!ctx->cfg_ptr->ext_zfinx) { 441 return cpu_fpr[reg_num]; 442 } 443 444 if (reg_num == 0) { 445 return tcg_constant_i64(0); 446 } 447 switch (get_xl(ctx)) { 448 case MXL_RV32: 449 #ifdef TARGET_RISCV32 450 { 451 TCGv_i64 t = ftemp_new(ctx); 452 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 453 return t; 454 } 455 #else 456 /* fall through */ 457 case MXL_RV64: 458 return cpu_gpr[reg_num]; 459 #endif 460 default: 461 g_assert_not_reached(); 462 } 463 } 464 465 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 466 { 467 if (!ctx->cfg_ptr->ext_zfinx) { 468 return cpu_fpr[reg_num]; 469 } 470 471 if (reg_num == 0) { 472 return tcg_constant_i64(0); 473 } 474 switch (get_xl(ctx)) { 475 case MXL_RV32: 476 { 477 TCGv_i64 t = ftemp_new(ctx); 478 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 479 return t; 480 } 481 #ifdef TARGET_RISCV64 482 case MXL_RV64: 483 return cpu_gpr[reg_num]; 484 #endif 485 default: 486 g_assert_not_reached(); 487 } 488 } 489 490 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 491 { 492 if (!ctx->cfg_ptr->ext_zfinx) { 493 return cpu_fpr[reg_num]; 494 } 495 496 if (reg_num == 0) { 497 return ftemp_new(ctx); 498 } 499 500 switch (get_xl(ctx)) { 501 case MXL_RV32: 502 return ftemp_new(ctx); 503 #ifdef TARGET_RISCV64 504 case MXL_RV64: 505 return cpu_gpr[reg_num]; 506 #endif 507 default: 508 g_assert_not_reached(); 509 } 510 } 511 512 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 513 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 514 { 515 if (!ctx->cfg_ptr->ext_zfinx) { 516 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 517 return; 518 } 519 if (reg_num != 0) { 520 switch (get_xl(ctx)) { 521 case MXL_RV32: 522 #ifdef TARGET_RISCV32 523 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 524 break; 525 #else 526 /* fall through */ 527 case MXL_RV64: 528 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 529 break; 530 #endif 531 default: 532 g_assert_not_reached(); 533 } 534 } 535 } 536 537 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 538 { 539 if (!ctx->cfg_ptr->ext_zfinx) { 540 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 541 return; 542 } 543 544 if (reg_num != 0) { 545 switch (get_xl(ctx)) { 546 case MXL_RV32: 547 #ifdef TARGET_RISCV32 548 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 549 break; 550 #else 551 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 552 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 553 break; 554 case MXL_RV64: 555 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 556 break; 557 #endif 558 default: 559 g_assert_not_reached(); 560 } 561 } 562 } 563 564 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 565 { 566 target_ulong next_pc; 567 568 /* check misaligned: */ 569 next_pc = ctx->base.pc_next + imm; 570 if (!has_ext(ctx, RVC)) { 571 if ((next_pc & 0x3) != 0) { 572 gen_exception_inst_addr_mis(ctx); 573 return; 574 } 575 } 576 577 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 578 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 579 ctx->base.is_jmp = DISAS_NORETURN; 580 } 581 582 /* Compute a canonical address from a register plus offset. */ 583 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 584 { 585 TCGv addr = temp_new(ctx); 586 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 587 588 tcg_gen_addi_tl(addr, src1, imm); 589 if (ctx->pm_mask_enabled) { 590 tcg_gen_andc_tl(addr, addr, pm_mask); 591 } else if (get_xl(ctx) == MXL_RV32) { 592 tcg_gen_ext32u_tl(addr, addr); 593 } 594 if (ctx->pm_base_enabled) { 595 tcg_gen_or_tl(addr, addr, pm_base); 596 } 597 return addr; 598 } 599 600 #ifndef CONFIG_USER_ONLY 601 /* The states of mstatus_fs are: 602 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 603 * We will have already diagnosed disabled state, 604 * and need to turn initial/clean into dirty. 605 */ 606 static void mark_fs_dirty(DisasContext *ctx) 607 { 608 TCGv tmp; 609 610 if (!has_ext(ctx, RVF)) { 611 return; 612 } 613 614 if (ctx->mstatus_fs != MSTATUS_FS) { 615 /* Remember the state change for the rest of the TB. */ 616 ctx->mstatus_fs = MSTATUS_FS; 617 618 tmp = tcg_temp_new(); 619 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 620 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 621 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 622 tcg_temp_free(tmp); 623 } 624 625 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 626 /* Remember the stage change for the rest of the TB. */ 627 ctx->mstatus_hs_fs = MSTATUS_FS; 628 629 tmp = tcg_temp_new(); 630 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 631 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 632 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 633 tcg_temp_free(tmp); 634 } 635 } 636 #else 637 static inline void mark_fs_dirty(DisasContext *ctx) { } 638 #endif 639 640 #ifndef CONFIG_USER_ONLY 641 /* The states of mstatus_vs are: 642 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 643 * We will have already diagnosed disabled state, 644 * and need to turn initial/clean into dirty. 645 */ 646 static void mark_vs_dirty(DisasContext *ctx) 647 { 648 TCGv tmp; 649 650 if (ctx->mstatus_vs != MSTATUS_VS) { 651 /* Remember the state change for the rest of the TB. */ 652 ctx->mstatus_vs = MSTATUS_VS; 653 654 tmp = tcg_temp_new(); 655 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 656 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 657 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 658 tcg_temp_free(tmp); 659 } 660 661 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 662 /* Remember the stage change for the rest of the TB. */ 663 ctx->mstatus_hs_vs = MSTATUS_VS; 664 665 tmp = tcg_temp_new(); 666 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 667 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 668 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 669 tcg_temp_free(tmp); 670 } 671 } 672 #else 673 static inline void mark_vs_dirty(DisasContext *ctx) { } 674 #endif 675 676 static void gen_set_rm(DisasContext *ctx, int rm) 677 { 678 if (ctx->frm == rm) { 679 return; 680 } 681 ctx->frm = rm; 682 683 if (rm == RISCV_FRM_DYN) { 684 /* The helper will return only if frm valid. */ 685 ctx->frm_valid = true; 686 } 687 688 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 689 decode_save_opc(ctx); 690 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 691 } 692 693 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 694 { 695 if (ctx->frm == rm && ctx->frm_valid) { 696 return; 697 } 698 ctx->frm = rm; 699 ctx->frm_valid = true; 700 701 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 702 decode_save_opc(ctx); 703 gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); 704 } 705 706 static int ex_plus_1(DisasContext *ctx, int nf) 707 { 708 return nf + 1; 709 } 710 711 #define EX_SH(amount) \ 712 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 713 { \ 714 return imm << amount; \ 715 } 716 EX_SH(1) 717 EX_SH(2) 718 EX_SH(3) 719 EX_SH(4) 720 EX_SH(12) 721 722 #define REQUIRE_EXT(ctx, ext) do { \ 723 if (!has_ext(ctx, ext)) { \ 724 return false; \ 725 } \ 726 } while (0) 727 728 #define REQUIRE_32BIT(ctx) do { \ 729 if (get_xl(ctx) != MXL_RV32) { \ 730 return false; \ 731 } \ 732 } while (0) 733 734 #define REQUIRE_64BIT(ctx) do { \ 735 if (get_xl(ctx) != MXL_RV64) { \ 736 return false; \ 737 } \ 738 } while (0) 739 740 #define REQUIRE_128BIT(ctx) do { \ 741 if (get_xl(ctx) != MXL_RV128) { \ 742 return false; \ 743 } \ 744 } while (0) 745 746 #define REQUIRE_64_OR_128BIT(ctx) do { \ 747 if (get_xl(ctx) == MXL_RV32) { \ 748 return false; \ 749 } \ 750 } while (0) 751 752 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 753 if (!ctx->cfg_ptr->ext_##A && \ 754 !ctx->cfg_ptr->ext_##B) { \ 755 return false; \ 756 } \ 757 } while (0) 758 759 static int ex_rvc_register(DisasContext *ctx, int reg) 760 { 761 return 8 + reg; 762 } 763 764 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 765 { 766 /* For RV128 a shamt of 0 means a shift by 64. */ 767 if (get_ol(ctx) == MXL_RV128) { 768 imm = imm ? imm : 64; 769 } 770 return imm; 771 } 772 773 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 774 { 775 /* 776 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 777 * shifts, the shamt is sign-extended. 778 */ 779 if (get_ol(ctx) == MXL_RV128) { 780 imm = imm | (imm & 32) << 1; 781 imm = imm ? imm : 64; 782 } 783 return imm; 784 } 785 786 /* Include the auto-generated decoder for 32 bit insn */ 787 #include "decode-insn32.c.inc" 788 789 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 790 void (*func)(TCGv, TCGv, target_long)) 791 { 792 TCGv dest = dest_gpr(ctx, a->rd); 793 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 794 795 func(dest, src1, a->imm); 796 797 if (get_xl(ctx) == MXL_RV128) { 798 TCGv src1h = get_gprh(ctx, a->rs1); 799 TCGv desth = dest_gprh(ctx, a->rd); 800 801 func(desth, src1h, -(a->imm < 0)); 802 gen_set_gpr128(ctx, a->rd, dest, desth); 803 } else { 804 gen_set_gpr(ctx, a->rd, dest); 805 } 806 807 return true; 808 } 809 810 static bool gen_logic(DisasContext *ctx, arg_r *a, 811 void (*func)(TCGv, TCGv, TCGv)) 812 { 813 TCGv dest = dest_gpr(ctx, a->rd); 814 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 815 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 816 817 func(dest, src1, src2); 818 819 if (get_xl(ctx) == MXL_RV128) { 820 TCGv src1h = get_gprh(ctx, a->rs1); 821 TCGv src2h = get_gprh(ctx, a->rs2); 822 TCGv desth = dest_gprh(ctx, a->rd); 823 824 func(desth, src1h, src2h); 825 gen_set_gpr128(ctx, a->rd, dest, desth); 826 } else { 827 gen_set_gpr(ctx, a->rd, dest); 828 } 829 830 return true; 831 } 832 833 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 834 void (*func)(TCGv, TCGv, target_long), 835 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 836 { 837 TCGv dest = dest_gpr(ctx, a->rd); 838 TCGv src1 = get_gpr(ctx, a->rs1, ext); 839 840 if (get_ol(ctx) < MXL_RV128) { 841 func(dest, src1, a->imm); 842 gen_set_gpr(ctx, a->rd, dest); 843 } else { 844 if (f128 == NULL) { 845 return false; 846 } 847 848 TCGv src1h = get_gprh(ctx, a->rs1); 849 TCGv desth = dest_gprh(ctx, a->rd); 850 851 f128(dest, desth, src1, src1h, a->imm); 852 gen_set_gpr128(ctx, a->rd, dest, desth); 853 } 854 return true; 855 } 856 857 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 858 void (*func)(TCGv, TCGv, TCGv), 859 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 860 { 861 TCGv dest = dest_gpr(ctx, a->rd); 862 TCGv src1 = get_gpr(ctx, a->rs1, ext); 863 TCGv src2 = tcg_constant_tl(a->imm); 864 865 if (get_ol(ctx) < MXL_RV128) { 866 func(dest, src1, src2); 867 gen_set_gpr(ctx, a->rd, dest); 868 } else { 869 if (f128 == NULL) { 870 return false; 871 } 872 873 TCGv src1h = get_gprh(ctx, a->rs1); 874 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 875 TCGv desth = dest_gprh(ctx, a->rd); 876 877 f128(dest, desth, src1, src1h, src2, src2h); 878 gen_set_gpr128(ctx, a->rd, dest, desth); 879 } 880 return true; 881 } 882 883 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 884 void (*func)(TCGv, TCGv, TCGv), 885 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 886 { 887 TCGv dest = dest_gpr(ctx, a->rd); 888 TCGv src1 = get_gpr(ctx, a->rs1, ext); 889 TCGv src2 = get_gpr(ctx, a->rs2, ext); 890 891 if (get_ol(ctx) < MXL_RV128) { 892 func(dest, src1, src2); 893 gen_set_gpr(ctx, a->rd, dest); 894 } else { 895 if (f128 == NULL) { 896 return false; 897 } 898 899 TCGv src1h = get_gprh(ctx, a->rs1); 900 TCGv src2h = get_gprh(ctx, a->rs2); 901 TCGv desth = dest_gprh(ctx, a->rd); 902 903 f128(dest, desth, src1, src1h, src2, src2h); 904 gen_set_gpr128(ctx, a->rd, dest, desth); 905 } 906 return true; 907 } 908 909 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 910 void (*f_tl)(TCGv, TCGv, TCGv), 911 void (*f_32)(TCGv, TCGv, TCGv), 912 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 913 { 914 int olen = get_olen(ctx); 915 916 if (olen != TARGET_LONG_BITS) { 917 if (olen == 32) { 918 f_tl = f_32; 919 } else if (olen != 128) { 920 g_assert_not_reached(); 921 } 922 } 923 return gen_arith(ctx, a, ext, f_tl, f_128); 924 } 925 926 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 927 void (*func)(TCGv, TCGv, target_long), 928 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 929 { 930 TCGv dest, src1; 931 int max_len = get_olen(ctx); 932 933 if (a->shamt >= max_len) { 934 return false; 935 } 936 937 dest = dest_gpr(ctx, a->rd); 938 src1 = get_gpr(ctx, a->rs1, ext); 939 940 if (max_len < 128) { 941 func(dest, src1, a->shamt); 942 gen_set_gpr(ctx, a->rd, dest); 943 } else { 944 TCGv src1h = get_gprh(ctx, a->rs1); 945 TCGv desth = dest_gprh(ctx, a->rd); 946 947 if (f128 == NULL) { 948 return false; 949 } 950 f128(dest, desth, src1, src1h, a->shamt); 951 gen_set_gpr128(ctx, a->rd, dest, desth); 952 } 953 return true; 954 } 955 956 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 957 DisasExtend ext, 958 void (*f_tl)(TCGv, TCGv, target_long), 959 void (*f_32)(TCGv, TCGv, target_long), 960 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 961 target_long)) 962 { 963 int olen = get_olen(ctx); 964 if (olen != TARGET_LONG_BITS) { 965 if (olen == 32) { 966 f_tl = f_32; 967 } else if (olen != 128) { 968 g_assert_not_reached(); 969 } 970 } 971 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 972 } 973 974 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 975 void (*func)(TCGv, TCGv, TCGv)) 976 { 977 TCGv dest, src1, src2; 978 int max_len = get_olen(ctx); 979 980 if (a->shamt >= max_len) { 981 return false; 982 } 983 984 dest = dest_gpr(ctx, a->rd); 985 src1 = get_gpr(ctx, a->rs1, ext); 986 src2 = tcg_constant_tl(a->shamt); 987 988 func(dest, src1, src2); 989 990 gen_set_gpr(ctx, a->rd, dest); 991 return true; 992 } 993 994 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 995 void (*func)(TCGv, TCGv, TCGv), 996 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 997 { 998 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 999 TCGv ext2 = tcg_temp_new(); 1000 int max_len = get_olen(ctx); 1001 1002 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1003 1004 TCGv dest = dest_gpr(ctx, a->rd); 1005 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1006 1007 if (max_len < 128) { 1008 func(dest, src1, ext2); 1009 gen_set_gpr(ctx, a->rd, dest); 1010 } else { 1011 TCGv src1h = get_gprh(ctx, a->rs1); 1012 TCGv desth = dest_gprh(ctx, a->rd); 1013 1014 if (f128 == NULL) { 1015 return false; 1016 } 1017 f128(dest, desth, src1, src1h, ext2); 1018 gen_set_gpr128(ctx, a->rd, dest, desth); 1019 } 1020 tcg_temp_free(ext2); 1021 return true; 1022 } 1023 1024 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1025 void (*f_tl)(TCGv, TCGv, TCGv), 1026 void (*f_32)(TCGv, TCGv, TCGv), 1027 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1028 { 1029 int olen = get_olen(ctx); 1030 if (olen != TARGET_LONG_BITS) { 1031 if (olen == 32) { 1032 f_tl = f_32; 1033 } else if (olen != 128) { 1034 g_assert_not_reached(); 1035 } 1036 } 1037 return gen_shift(ctx, a, ext, f_tl, f_128); 1038 } 1039 1040 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1041 void (*func)(TCGv, TCGv)) 1042 { 1043 TCGv dest = dest_gpr(ctx, a->rd); 1044 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1045 1046 func(dest, src1); 1047 1048 gen_set_gpr(ctx, a->rd, dest); 1049 return true; 1050 } 1051 1052 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1053 void (*f_tl)(TCGv, TCGv), 1054 void (*f_32)(TCGv, TCGv)) 1055 { 1056 int olen = get_olen(ctx); 1057 1058 if (olen != TARGET_LONG_BITS) { 1059 if (olen == 32) { 1060 f_tl = f_32; 1061 } else { 1062 g_assert_not_reached(); 1063 } 1064 } 1065 return gen_unary(ctx, a, ext, f_tl); 1066 } 1067 1068 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1069 { 1070 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1071 CPUState *cpu = ctx->cs; 1072 CPURISCVState *env = cpu->env_ptr; 1073 1074 return cpu_ldl_code(env, pc); 1075 } 1076 1077 /* Include insn module translation function */ 1078 #include "insn_trans/trans_rvi.c.inc" 1079 #include "insn_trans/trans_rvm.c.inc" 1080 #include "insn_trans/trans_rva.c.inc" 1081 #include "insn_trans/trans_rvf.c.inc" 1082 #include "insn_trans/trans_rvd.c.inc" 1083 #include "insn_trans/trans_rvh.c.inc" 1084 #include "insn_trans/trans_rvv.c.inc" 1085 #include "insn_trans/trans_rvb.c.inc" 1086 #include "insn_trans/trans_rvzawrs.c.inc" 1087 #include "insn_trans/trans_rvzfh.c.inc" 1088 #include "insn_trans/trans_rvk.c.inc" 1089 #include "insn_trans/trans_privileged.c.inc" 1090 #include "insn_trans/trans_svinval.c.inc" 1091 #include "decode-xthead.c.inc" 1092 #include "insn_trans/trans_xthead.c.inc" 1093 #include "insn_trans/trans_xventanacondops.c.inc" 1094 1095 /* Include the auto-generated decoder for 16 bit insn */ 1096 #include "decode-insn16.c.inc" 1097 /* Include decoders for factored-out extensions */ 1098 #include "decode-XVentanaCondOps.c.inc" 1099 1100 /* The specification allows for longer insns, but not supported by qemu. */ 1101 #define MAX_INSN_LEN 4 1102 1103 static inline int insn_len(uint16_t first_word) 1104 { 1105 return (first_word & 3) == 3 ? 4 : 2; 1106 } 1107 1108 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1109 { 1110 /* 1111 * A table with predicate (i.e., guard) functions and decoder functions 1112 * that are tested in-order until a decoder matches onto the opcode. 1113 */ 1114 static const struct { 1115 bool (*guard_func)(DisasContext *); 1116 bool (*decode_func)(DisasContext *, uint32_t); 1117 } decoders[] = { 1118 { always_true_p, decode_insn32 }, 1119 { has_xthead_p, decode_xthead }, 1120 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1121 }; 1122 1123 ctx->virt_inst_excp = false; 1124 /* Check for compressed insn */ 1125 if (insn_len(opcode) == 2) { 1126 ctx->opcode = opcode; 1127 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1128 if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { 1129 return; 1130 } 1131 } else { 1132 uint32_t opcode32 = opcode; 1133 opcode32 = deposit32(opcode32, 16, 16, 1134 translator_lduw(env, &ctx->base, 1135 ctx->base.pc_next + 2)); 1136 ctx->opcode = opcode32; 1137 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1138 1139 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1140 if (decoders[i].guard_func(ctx) && 1141 decoders[i].decode_func(ctx, opcode32)) { 1142 return; 1143 } 1144 } 1145 } 1146 1147 gen_exception_illegal(ctx); 1148 } 1149 1150 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1151 { 1152 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1153 CPURISCVState *env = cs->env_ptr; 1154 RISCVCPU *cpu = RISCV_CPU(cs); 1155 uint32_t tb_flags = ctx->base.tb->flags; 1156 1157 ctx->pc_succ_insn = ctx->base.pc_first; 1158 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1159 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1160 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1161 ctx->priv_ver = env->priv_ver; 1162 #if !defined(CONFIG_USER_ONLY) 1163 if (riscv_has_ext(env, RVH)) { 1164 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1165 } else { 1166 ctx->virt_enabled = false; 1167 } 1168 #else 1169 ctx->virt_enabled = false; 1170 #endif 1171 ctx->misa_ext = env->misa_ext; 1172 ctx->frm = -1; /* unknown rounding mode */ 1173 ctx->cfg_ptr = &(cpu->cfg); 1174 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1175 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1176 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1177 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1178 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1179 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1180 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1181 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1182 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1183 ctx->vstart = env->vstart; 1184 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1185 ctx->misa_mxl_max = env->misa_mxl_max; 1186 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1187 ctx->cs = cs; 1188 ctx->ntemp = 0; 1189 memset(ctx->temp, 0, sizeof(ctx->temp)); 1190 ctx->nftemp = 0; 1191 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1192 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1193 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1194 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1195 ctx->zero = tcg_constant_tl(0); 1196 } 1197 1198 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1199 { 1200 } 1201 1202 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1203 { 1204 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1205 1206 tcg_gen_insn_start(ctx->base.pc_next, 0); 1207 ctx->insn_start = tcg_last_op(); 1208 } 1209 1210 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1211 { 1212 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1213 CPURISCVState *env = cpu->env_ptr; 1214 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1215 int i; 1216 1217 ctx->ol = ctx->xl; 1218 decode_opc(env, ctx, opcode16); 1219 ctx->base.pc_next = ctx->pc_succ_insn; 1220 1221 for (i = ctx->ntemp - 1; i >= 0; --i) { 1222 tcg_temp_free(ctx->temp[i]); 1223 ctx->temp[i] = NULL; 1224 } 1225 ctx->ntemp = 0; 1226 for (i = ctx->nftemp - 1; i >= 0; --i) { 1227 tcg_temp_free_i64(ctx->ftemp[i]); 1228 ctx->ftemp[i] = NULL; 1229 } 1230 ctx->nftemp = 0; 1231 1232 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1233 if (ctx->base.is_jmp == DISAS_NEXT) { 1234 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1235 ctx->base.is_jmp = DISAS_TOO_MANY; 1236 } else { 1237 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1238 1239 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1240 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1241 int len = insn_len(next_insn); 1242 1243 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1244 ctx->base.is_jmp = DISAS_TOO_MANY; 1245 } 1246 } 1247 } 1248 } 1249 } 1250 1251 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1252 { 1253 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1254 1255 switch (ctx->base.is_jmp) { 1256 case DISAS_TOO_MANY: 1257 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1258 break; 1259 case DISAS_NORETURN: 1260 break; 1261 default: 1262 g_assert_not_reached(); 1263 } 1264 } 1265 1266 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1267 CPUState *cpu, FILE *logfile) 1268 { 1269 #ifndef CONFIG_USER_ONLY 1270 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1271 CPURISCVState *env = &rvcpu->env; 1272 #endif 1273 1274 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1275 #ifndef CONFIG_USER_ONLY 1276 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1277 env->priv, env->virt); 1278 #endif 1279 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1280 } 1281 1282 static const TranslatorOps riscv_tr_ops = { 1283 .init_disas_context = riscv_tr_init_disas_context, 1284 .tb_start = riscv_tr_tb_start, 1285 .insn_start = riscv_tr_insn_start, 1286 .translate_insn = riscv_tr_translate_insn, 1287 .tb_stop = riscv_tr_tb_stop, 1288 .disas_log = riscv_tr_disas_log, 1289 }; 1290 1291 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1292 target_ulong pc, void *host_pc) 1293 { 1294 DisasContext ctx; 1295 1296 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1297 } 1298 1299 void riscv_translate_init(void) 1300 { 1301 int i; 1302 1303 /* 1304 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1305 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1306 * unless you specifically block reads/writes to reg 0. 1307 */ 1308 cpu_gpr[0] = NULL; 1309 cpu_gprh[0] = NULL; 1310 1311 for (i = 1; i < 32; i++) { 1312 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1313 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1314 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1315 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1316 } 1317 1318 for (i = 0; i < 32; i++) { 1319 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1320 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1321 } 1322 1323 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1324 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1325 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1326 "vstart"); 1327 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1328 "load_res"); 1329 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1330 "load_val"); 1331 /* Assign PM CSRs to tcg globals */ 1332 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1333 "pmmask"); 1334 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1335 "pmbase"); 1336 } 1337