1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 #include "semihosting/semihost.h" 32 33 #include "instmap.h" 34 #include "internals.h" 35 36 /* global register indices */ 37 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 38 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 39 static TCGv load_res; 40 static TCGv load_val; 41 /* globals for PM CSRs */ 42 static TCGv pm_mask; 43 static TCGv pm_base; 44 45 #include "exec/gen-icount.h" 46 47 /* 48 * If an operation is being performed on less than TARGET_LONG_BITS, 49 * it may require the inputs to be sign- or zero-extended; which will 50 * depend on the exact operation being performed. 51 */ 52 typedef enum { 53 EXT_NONE, 54 EXT_SIGN, 55 EXT_ZERO, 56 } DisasExtend; 57 58 typedef struct DisasContext { 59 DisasContextBase base; 60 /* pc_succ_insn points to the instruction following base.pc_next */ 61 target_ulong pc_succ_insn; 62 target_ulong priv_ver; 63 RISCVMXL misa_mxl_max; 64 RISCVMXL xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 uint32_t mstatus_fs; 68 uint32_t mstatus_vs; 69 uint32_t mstatus_hs_fs; 70 uint32_t mstatus_hs_vs; 71 uint32_t mem_idx; 72 /* Remember the rounding mode encoded in the previous fp instruction, 73 which we have already installed into env->fp_status. Or -1 for 74 no previous fp instruction. Note that we exit the TB when writing 75 to any system register, which includes CSR_FRM, so we do not have 76 to reset this known value. */ 77 int frm; 78 RISCVMXL ol; 79 bool virt_enabled; 80 const RISCVCPUConfig *cfg_ptr; 81 bool hlsx; 82 /* vector extension */ 83 bool vill; 84 /* 85 * Encode LMUL to lmul as follows: 86 * LMUL vlmul lmul 87 * 1 000 0 88 * 2 001 1 89 * 4 010 2 90 * 8 011 3 91 * - 100 - 92 * 1/8 101 -3 93 * 1/4 110 -2 94 * 1/2 111 -1 95 */ 96 int8_t lmul; 97 uint8_t sew; 98 uint8_t vta; 99 uint8_t vma; 100 bool cfg_vta_all_1s; 101 target_ulong vstart; 102 bool vl_eq_vlmax; 103 uint8_t ntemp; 104 CPUState *cs; 105 TCGv zero; 106 /* Space for 3 operands plus 1 extra for address computation. */ 107 TCGv temp[4]; 108 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 109 TCGv_i64 ftemp[4]; 110 uint8_t nftemp; 111 /* PointerMasking extension */ 112 bool pm_mask_enabled; 113 bool pm_base_enabled; 114 /* TCG of the current insn_start */ 115 TCGOp *insn_start; 116 } DisasContext; 117 118 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 119 { 120 return ctx->misa_ext & ext; 121 } 122 123 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 124 { 125 return true; 126 } 127 128 #define MATERIALISE_EXT_PREDICATE(ext) \ 129 static bool has_ ## ext ## _p(DisasContext *ctx) \ 130 { \ 131 return ctx->cfg_ptr->ext_ ## ext ; \ 132 } 133 134 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 135 136 #ifdef TARGET_RISCV32 137 #define get_xl(ctx) MXL_RV32 138 #elif defined(CONFIG_USER_ONLY) 139 #define get_xl(ctx) MXL_RV64 140 #else 141 #define get_xl(ctx) ((ctx)->xl) 142 #endif 143 144 /* The word size for this machine mode. */ 145 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 146 { 147 return 16 << get_xl(ctx); 148 } 149 150 /* The operation length, as opposed to the xlen. */ 151 #ifdef TARGET_RISCV32 152 #define get_ol(ctx) MXL_RV32 153 #else 154 #define get_ol(ctx) ((ctx)->ol) 155 #endif 156 157 static inline int get_olen(DisasContext *ctx) 158 { 159 return 16 << get_ol(ctx); 160 } 161 162 /* The maximum register length */ 163 #ifdef TARGET_RISCV32 164 #define get_xl_max(ctx) MXL_RV32 165 #else 166 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 167 #endif 168 169 /* 170 * RISC-V requires NaN-boxing of narrower width floating point values. 171 * This applies when a 32-bit value is assigned to a 64-bit FP register. 172 * For consistency and simplicity, we nanbox results even when the RVD 173 * extension is not present. 174 */ 175 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 176 { 177 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 178 } 179 180 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 181 { 182 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 183 } 184 185 /* 186 * A narrow n-bit operation, where n < FLEN, checks that input operands 187 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 188 * If so, the least-significant bits of the input are used, otherwise the 189 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 190 * 191 * Here, the result is always nan-boxed, even the canonical nan. 192 */ 193 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 194 { 195 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 196 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 197 198 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 199 tcg_temp_free_i64(t_max); 200 tcg_temp_free_i64(t_nan); 201 } 202 203 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 204 { 205 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 206 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 207 208 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 209 } 210 211 static void decode_save_opc(DisasContext *ctx) 212 { 213 assert(ctx->insn_start != NULL); 214 tcg_set_insn_start_param(ctx->insn_start, 1, ctx->opcode); 215 ctx->insn_start = NULL; 216 } 217 218 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 219 { 220 if (get_xl(ctx) == MXL_RV32) { 221 dest = (int32_t)dest; 222 } 223 tcg_gen_movi_tl(cpu_pc, dest); 224 } 225 226 static void gen_set_pc(DisasContext *ctx, TCGv dest) 227 { 228 if (get_xl(ctx) == MXL_RV32) { 229 tcg_gen_ext32s_tl(cpu_pc, dest); 230 } else { 231 tcg_gen_mov_tl(cpu_pc, dest); 232 } 233 } 234 235 static void generate_exception(DisasContext *ctx, int excp) 236 { 237 gen_set_pc_imm(ctx, ctx->base.pc_next); 238 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 239 ctx->base.is_jmp = DISAS_NORETURN; 240 } 241 242 static void gen_exception_illegal(DisasContext *ctx) 243 { 244 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 245 offsetof(CPURISCVState, bins)); 246 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 247 } 248 249 static void gen_exception_inst_addr_mis(DisasContext *ctx) 250 { 251 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 252 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 253 } 254 255 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 256 { 257 if (translator_use_goto_tb(&ctx->base, dest)) { 258 tcg_gen_goto_tb(n); 259 gen_set_pc_imm(ctx, dest); 260 tcg_gen_exit_tb(ctx->base.tb, n); 261 } else { 262 gen_set_pc_imm(ctx, dest); 263 tcg_gen_lookup_and_goto_ptr(); 264 } 265 } 266 267 /* 268 * Wrappers for getting reg values. 269 * 270 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 271 * constant zero as a source, and an uninitialized sink as destination. 272 * 273 * Further, we may provide an extension for word operations. 274 */ 275 static TCGv temp_new(DisasContext *ctx) 276 { 277 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 278 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 279 } 280 281 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 282 { 283 TCGv t; 284 285 if (reg_num == 0) { 286 return ctx->zero; 287 } 288 289 switch (get_ol(ctx)) { 290 case MXL_RV32: 291 switch (ext) { 292 case EXT_NONE: 293 break; 294 case EXT_SIGN: 295 t = temp_new(ctx); 296 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 297 return t; 298 case EXT_ZERO: 299 t = temp_new(ctx); 300 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 301 return t; 302 default: 303 g_assert_not_reached(); 304 } 305 break; 306 case MXL_RV64: 307 case MXL_RV128: 308 break; 309 default: 310 g_assert_not_reached(); 311 } 312 return cpu_gpr[reg_num]; 313 } 314 315 static TCGv get_gprh(DisasContext *ctx, int reg_num) 316 { 317 assert(get_xl(ctx) == MXL_RV128); 318 if (reg_num == 0) { 319 return ctx->zero; 320 } 321 return cpu_gprh[reg_num]; 322 } 323 324 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 325 { 326 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 327 return temp_new(ctx); 328 } 329 return cpu_gpr[reg_num]; 330 } 331 332 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 333 { 334 if (reg_num == 0) { 335 return temp_new(ctx); 336 } 337 return cpu_gprh[reg_num]; 338 } 339 340 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 341 { 342 if (reg_num != 0) { 343 switch (get_ol(ctx)) { 344 case MXL_RV32: 345 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 346 break; 347 case MXL_RV64: 348 case MXL_RV128: 349 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 350 break; 351 default: 352 g_assert_not_reached(); 353 } 354 355 if (get_xl_max(ctx) == MXL_RV128) { 356 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 357 } 358 } 359 } 360 361 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 362 { 363 if (reg_num != 0) { 364 switch (get_ol(ctx)) { 365 case MXL_RV32: 366 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 367 break; 368 case MXL_RV64: 369 case MXL_RV128: 370 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 371 break; 372 default: 373 g_assert_not_reached(); 374 } 375 376 if (get_xl_max(ctx) == MXL_RV128) { 377 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 378 } 379 } 380 } 381 382 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 383 { 384 assert(get_ol(ctx) == MXL_RV128); 385 if (reg_num != 0) { 386 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 387 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 388 } 389 } 390 391 static TCGv_i64 ftemp_new(DisasContext *ctx) 392 { 393 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 394 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 395 } 396 397 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 398 { 399 if (!ctx->cfg_ptr->ext_zfinx) { 400 return cpu_fpr[reg_num]; 401 } 402 403 if (reg_num == 0) { 404 return tcg_constant_i64(0); 405 } 406 switch (get_xl(ctx)) { 407 case MXL_RV32: 408 #ifdef TARGET_RISCV32 409 { 410 TCGv_i64 t = ftemp_new(ctx); 411 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 412 return t; 413 } 414 #else 415 /* fall through */ 416 case MXL_RV64: 417 return cpu_gpr[reg_num]; 418 #endif 419 default: 420 g_assert_not_reached(); 421 } 422 } 423 424 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 425 { 426 if (!ctx->cfg_ptr->ext_zfinx) { 427 return cpu_fpr[reg_num]; 428 } 429 430 if (reg_num == 0) { 431 return tcg_constant_i64(0); 432 } 433 switch (get_xl(ctx)) { 434 case MXL_RV32: 435 { 436 TCGv_i64 t = ftemp_new(ctx); 437 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 438 return t; 439 } 440 #ifdef TARGET_RISCV64 441 case MXL_RV64: 442 return cpu_gpr[reg_num]; 443 #endif 444 default: 445 g_assert_not_reached(); 446 } 447 } 448 449 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 450 { 451 if (!ctx->cfg_ptr->ext_zfinx) { 452 return cpu_fpr[reg_num]; 453 } 454 455 if (reg_num == 0) { 456 return ftemp_new(ctx); 457 } 458 459 switch (get_xl(ctx)) { 460 case MXL_RV32: 461 return ftemp_new(ctx); 462 #ifdef TARGET_RISCV64 463 case MXL_RV64: 464 return cpu_gpr[reg_num]; 465 #endif 466 default: 467 g_assert_not_reached(); 468 } 469 } 470 471 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 472 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 473 { 474 if (!ctx->cfg_ptr->ext_zfinx) { 475 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 476 return; 477 } 478 if (reg_num != 0) { 479 switch (get_xl(ctx)) { 480 case MXL_RV32: 481 #ifdef TARGET_RISCV32 482 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 483 break; 484 #else 485 /* fall through */ 486 case MXL_RV64: 487 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 488 break; 489 #endif 490 default: 491 g_assert_not_reached(); 492 } 493 } 494 } 495 496 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 497 { 498 if (!ctx->cfg_ptr->ext_zfinx) { 499 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 500 return; 501 } 502 503 if (reg_num != 0) { 504 switch (get_xl(ctx)) { 505 case MXL_RV32: 506 #ifdef TARGET_RISCV32 507 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 508 break; 509 #else 510 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 511 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 512 break; 513 case MXL_RV64: 514 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 515 break; 516 #endif 517 default: 518 g_assert_not_reached(); 519 } 520 } 521 } 522 523 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 524 { 525 target_ulong next_pc; 526 527 /* check misaligned: */ 528 next_pc = ctx->base.pc_next + imm; 529 if (!has_ext(ctx, RVC)) { 530 if ((next_pc & 0x3) != 0) { 531 gen_exception_inst_addr_mis(ctx); 532 return; 533 } 534 } 535 536 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 537 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 538 ctx->base.is_jmp = DISAS_NORETURN; 539 } 540 541 /* Compute a canonical address from a register plus offset. */ 542 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 543 { 544 TCGv addr = temp_new(ctx); 545 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 546 547 tcg_gen_addi_tl(addr, src1, imm); 548 if (ctx->pm_mask_enabled) { 549 tcg_gen_andc_tl(addr, addr, pm_mask); 550 } else if (get_xl(ctx) == MXL_RV32) { 551 tcg_gen_ext32u_tl(addr, addr); 552 } 553 if (ctx->pm_base_enabled) { 554 tcg_gen_or_tl(addr, addr, pm_base); 555 } 556 return addr; 557 } 558 559 #ifndef CONFIG_USER_ONLY 560 /* The states of mstatus_fs are: 561 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 562 * We will have already diagnosed disabled state, 563 * and need to turn initial/clean into dirty. 564 */ 565 static void mark_fs_dirty(DisasContext *ctx) 566 { 567 TCGv tmp; 568 569 if (!has_ext(ctx, RVF)) { 570 return; 571 } 572 573 if (ctx->mstatus_fs != MSTATUS_FS) { 574 /* Remember the state change for the rest of the TB. */ 575 ctx->mstatus_fs = MSTATUS_FS; 576 577 tmp = tcg_temp_new(); 578 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 579 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 580 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 581 tcg_temp_free(tmp); 582 } 583 584 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 585 /* Remember the stage change for the rest of the TB. */ 586 ctx->mstatus_hs_fs = MSTATUS_FS; 587 588 tmp = tcg_temp_new(); 589 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 590 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 591 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 592 tcg_temp_free(tmp); 593 } 594 } 595 #else 596 static inline void mark_fs_dirty(DisasContext *ctx) { } 597 #endif 598 599 #ifndef CONFIG_USER_ONLY 600 /* The states of mstatus_vs are: 601 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 602 * We will have already diagnosed disabled state, 603 * and need to turn initial/clean into dirty. 604 */ 605 static void mark_vs_dirty(DisasContext *ctx) 606 { 607 TCGv tmp; 608 609 if (ctx->mstatus_vs != MSTATUS_VS) { 610 /* Remember the state change for the rest of the TB. */ 611 ctx->mstatus_vs = MSTATUS_VS; 612 613 tmp = tcg_temp_new(); 614 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 615 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 616 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 617 tcg_temp_free(tmp); 618 } 619 620 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 621 /* Remember the stage change for the rest of the TB. */ 622 ctx->mstatus_hs_vs = MSTATUS_VS; 623 624 tmp = tcg_temp_new(); 625 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 626 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 627 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 628 tcg_temp_free(tmp); 629 } 630 } 631 #else 632 static inline void mark_vs_dirty(DisasContext *ctx) { } 633 #endif 634 635 static void gen_set_rm(DisasContext *ctx, int rm) 636 { 637 if (ctx->frm == rm) { 638 return; 639 } 640 ctx->frm = rm; 641 642 if (rm == RISCV_FRM_ROD) { 643 gen_helper_set_rod_rounding_mode(cpu_env); 644 return; 645 } 646 647 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 648 decode_save_opc(ctx); 649 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 650 } 651 652 static int ex_plus_1(DisasContext *ctx, int nf) 653 { 654 return nf + 1; 655 } 656 657 #define EX_SH(amount) \ 658 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 659 { \ 660 return imm << amount; \ 661 } 662 EX_SH(1) 663 EX_SH(2) 664 EX_SH(3) 665 EX_SH(4) 666 EX_SH(12) 667 668 #define REQUIRE_EXT(ctx, ext) do { \ 669 if (!has_ext(ctx, ext)) { \ 670 return false; \ 671 } \ 672 } while (0) 673 674 #define REQUIRE_32BIT(ctx) do { \ 675 if (get_xl(ctx) != MXL_RV32) { \ 676 return false; \ 677 } \ 678 } while (0) 679 680 #define REQUIRE_64BIT(ctx) do { \ 681 if (get_xl(ctx) != MXL_RV64) { \ 682 return false; \ 683 } \ 684 } while (0) 685 686 #define REQUIRE_128BIT(ctx) do { \ 687 if (get_xl(ctx) != MXL_RV128) { \ 688 return false; \ 689 } \ 690 } while (0) 691 692 #define REQUIRE_64_OR_128BIT(ctx) do { \ 693 if (get_xl(ctx) == MXL_RV32) { \ 694 return false; \ 695 } \ 696 } while (0) 697 698 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 699 if (!ctx->cfg_ptr->ext_##A && \ 700 !ctx->cfg_ptr->ext_##B) { \ 701 return false; \ 702 } \ 703 } while (0) 704 705 static int ex_rvc_register(DisasContext *ctx, int reg) 706 { 707 return 8 + reg; 708 } 709 710 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 711 { 712 /* For RV128 a shamt of 0 means a shift by 64. */ 713 if (get_ol(ctx) == MXL_RV128) { 714 imm = imm ? imm : 64; 715 } 716 return imm; 717 } 718 719 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 720 { 721 /* 722 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 723 * shifts, the shamt is sign-extended. 724 */ 725 if (get_ol(ctx) == MXL_RV128) { 726 imm = imm | (imm & 32) << 1; 727 imm = imm ? imm : 64; 728 } 729 return imm; 730 } 731 732 /* Include the auto-generated decoder for 32 bit insn */ 733 #include "decode-insn32.c.inc" 734 735 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 736 void (*func)(TCGv, TCGv, target_long)) 737 { 738 TCGv dest = dest_gpr(ctx, a->rd); 739 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 740 741 func(dest, src1, a->imm); 742 743 if (get_xl(ctx) == MXL_RV128) { 744 TCGv src1h = get_gprh(ctx, a->rs1); 745 TCGv desth = dest_gprh(ctx, a->rd); 746 747 func(desth, src1h, -(a->imm < 0)); 748 gen_set_gpr128(ctx, a->rd, dest, desth); 749 } else { 750 gen_set_gpr(ctx, a->rd, dest); 751 } 752 753 return true; 754 } 755 756 static bool gen_logic(DisasContext *ctx, arg_r *a, 757 void (*func)(TCGv, TCGv, TCGv)) 758 { 759 TCGv dest = dest_gpr(ctx, a->rd); 760 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 761 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 762 763 func(dest, src1, src2); 764 765 if (get_xl(ctx) == MXL_RV128) { 766 TCGv src1h = get_gprh(ctx, a->rs1); 767 TCGv src2h = get_gprh(ctx, a->rs2); 768 TCGv desth = dest_gprh(ctx, a->rd); 769 770 func(desth, src1h, src2h); 771 gen_set_gpr128(ctx, a->rd, dest, desth); 772 } else { 773 gen_set_gpr(ctx, a->rd, dest); 774 } 775 776 return true; 777 } 778 779 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 780 void (*func)(TCGv, TCGv, target_long), 781 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 782 { 783 TCGv dest = dest_gpr(ctx, a->rd); 784 TCGv src1 = get_gpr(ctx, a->rs1, ext); 785 786 if (get_ol(ctx) < MXL_RV128) { 787 func(dest, src1, a->imm); 788 gen_set_gpr(ctx, a->rd, dest); 789 } else { 790 if (f128 == NULL) { 791 return false; 792 } 793 794 TCGv src1h = get_gprh(ctx, a->rs1); 795 TCGv desth = dest_gprh(ctx, a->rd); 796 797 f128(dest, desth, src1, src1h, a->imm); 798 gen_set_gpr128(ctx, a->rd, dest, desth); 799 } 800 return true; 801 } 802 803 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 804 void (*func)(TCGv, TCGv, TCGv), 805 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 806 { 807 TCGv dest = dest_gpr(ctx, a->rd); 808 TCGv src1 = get_gpr(ctx, a->rs1, ext); 809 TCGv src2 = tcg_constant_tl(a->imm); 810 811 if (get_ol(ctx) < MXL_RV128) { 812 func(dest, src1, src2); 813 gen_set_gpr(ctx, a->rd, dest); 814 } else { 815 if (f128 == NULL) { 816 return false; 817 } 818 819 TCGv src1h = get_gprh(ctx, a->rs1); 820 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 821 TCGv desth = dest_gprh(ctx, a->rd); 822 823 f128(dest, desth, src1, src1h, src2, src2h); 824 gen_set_gpr128(ctx, a->rd, dest, desth); 825 } 826 return true; 827 } 828 829 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 830 void (*func)(TCGv, TCGv, TCGv), 831 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 832 { 833 TCGv dest = dest_gpr(ctx, a->rd); 834 TCGv src1 = get_gpr(ctx, a->rs1, ext); 835 TCGv src2 = get_gpr(ctx, a->rs2, ext); 836 837 if (get_ol(ctx) < MXL_RV128) { 838 func(dest, src1, src2); 839 gen_set_gpr(ctx, a->rd, dest); 840 } else { 841 if (f128 == NULL) { 842 return false; 843 } 844 845 TCGv src1h = get_gprh(ctx, a->rs1); 846 TCGv src2h = get_gprh(ctx, a->rs2); 847 TCGv desth = dest_gprh(ctx, a->rd); 848 849 f128(dest, desth, src1, src1h, src2, src2h); 850 gen_set_gpr128(ctx, a->rd, dest, desth); 851 } 852 return true; 853 } 854 855 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 856 void (*f_tl)(TCGv, TCGv, TCGv), 857 void (*f_32)(TCGv, TCGv, TCGv), 858 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 859 { 860 int olen = get_olen(ctx); 861 862 if (olen != TARGET_LONG_BITS) { 863 if (olen == 32) { 864 f_tl = f_32; 865 } else if (olen != 128) { 866 g_assert_not_reached(); 867 } 868 } 869 return gen_arith(ctx, a, ext, f_tl, f_128); 870 } 871 872 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 873 void (*func)(TCGv, TCGv, target_long), 874 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 875 { 876 TCGv dest, src1; 877 int max_len = get_olen(ctx); 878 879 if (a->shamt >= max_len) { 880 return false; 881 } 882 883 dest = dest_gpr(ctx, a->rd); 884 src1 = get_gpr(ctx, a->rs1, ext); 885 886 if (max_len < 128) { 887 func(dest, src1, a->shamt); 888 gen_set_gpr(ctx, a->rd, dest); 889 } else { 890 TCGv src1h = get_gprh(ctx, a->rs1); 891 TCGv desth = dest_gprh(ctx, a->rd); 892 893 if (f128 == NULL) { 894 return false; 895 } 896 f128(dest, desth, src1, src1h, a->shamt); 897 gen_set_gpr128(ctx, a->rd, dest, desth); 898 } 899 return true; 900 } 901 902 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 903 DisasExtend ext, 904 void (*f_tl)(TCGv, TCGv, target_long), 905 void (*f_32)(TCGv, TCGv, target_long), 906 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 907 target_long)) 908 { 909 int olen = get_olen(ctx); 910 if (olen != TARGET_LONG_BITS) { 911 if (olen == 32) { 912 f_tl = f_32; 913 } else if (olen != 128) { 914 g_assert_not_reached(); 915 } 916 } 917 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 918 } 919 920 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 921 void (*func)(TCGv, TCGv, TCGv)) 922 { 923 TCGv dest, src1, src2; 924 int max_len = get_olen(ctx); 925 926 if (a->shamt >= max_len) { 927 return false; 928 } 929 930 dest = dest_gpr(ctx, a->rd); 931 src1 = get_gpr(ctx, a->rs1, ext); 932 src2 = tcg_constant_tl(a->shamt); 933 934 func(dest, src1, src2); 935 936 gen_set_gpr(ctx, a->rd, dest); 937 return true; 938 } 939 940 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 941 void (*func)(TCGv, TCGv, TCGv), 942 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 943 { 944 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 945 TCGv ext2 = tcg_temp_new(); 946 int max_len = get_olen(ctx); 947 948 tcg_gen_andi_tl(ext2, src2, max_len - 1); 949 950 TCGv dest = dest_gpr(ctx, a->rd); 951 TCGv src1 = get_gpr(ctx, a->rs1, ext); 952 953 if (max_len < 128) { 954 func(dest, src1, ext2); 955 gen_set_gpr(ctx, a->rd, dest); 956 } else { 957 TCGv src1h = get_gprh(ctx, a->rs1); 958 TCGv desth = dest_gprh(ctx, a->rd); 959 960 if (f128 == NULL) { 961 return false; 962 } 963 f128(dest, desth, src1, src1h, ext2); 964 gen_set_gpr128(ctx, a->rd, dest, desth); 965 } 966 tcg_temp_free(ext2); 967 return true; 968 } 969 970 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 971 void (*f_tl)(TCGv, TCGv, TCGv), 972 void (*f_32)(TCGv, TCGv, TCGv), 973 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 974 { 975 int olen = get_olen(ctx); 976 if (olen != TARGET_LONG_BITS) { 977 if (olen == 32) { 978 f_tl = f_32; 979 } else if (olen != 128) { 980 g_assert_not_reached(); 981 } 982 } 983 return gen_shift(ctx, a, ext, f_tl, f_128); 984 } 985 986 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 987 void (*func)(TCGv, TCGv)) 988 { 989 TCGv dest = dest_gpr(ctx, a->rd); 990 TCGv src1 = get_gpr(ctx, a->rs1, ext); 991 992 func(dest, src1); 993 994 gen_set_gpr(ctx, a->rd, dest); 995 return true; 996 } 997 998 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 999 void (*f_tl)(TCGv, TCGv), 1000 void (*f_32)(TCGv, TCGv)) 1001 { 1002 int olen = get_olen(ctx); 1003 1004 if (olen != TARGET_LONG_BITS) { 1005 if (olen == 32) { 1006 f_tl = f_32; 1007 } else { 1008 g_assert_not_reached(); 1009 } 1010 } 1011 return gen_unary(ctx, a, ext, f_tl); 1012 } 1013 1014 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1015 { 1016 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1017 CPUState *cpu = ctx->cs; 1018 CPURISCVState *env = cpu->env_ptr; 1019 1020 return cpu_ldl_code(env, pc); 1021 } 1022 1023 /* Include insn module translation function */ 1024 #include "insn_trans/trans_rvi.c.inc" 1025 #include "insn_trans/trans_rvm.c.inc" 1026 #include "insn_trans/trans_rva.c.inc" 1027 #include "insn_trans/trans_rvf.c.inc" 1028 #include "insn_trans/trans_rvd.c.inc" 1029 #include "insn_trans/trans_rvh.c.inc" 1030 #include "insn_trans/trans_rvv.c.inc" 1031 #include "insn_trans/trans_rvb.c.inc" 1032 #include "insn_trans/trans_rvzfh.c.inc" 1033 #include "insn_trans/trans_rvk.c.inc" 1034 #include "insn_trans/trans_privileged.c.inc" 1035 #include "insn_trans/trans_svinval.c.inc" 1036 #include "insn_trans/trans_xventanacondops.c.inc" 1037 1038 /* Include the auto-generated decoder for 16 bit insn */ 1039 #include "decode-insn16.c.inc" 1040 /* Include decoders for factored-out extensions */ 1041 #include "decode-XVentanaCondOps.c.inc" 1042 1043 /* The specification allows for longer insns, but not supported by qemu. */ 1044 #define MAX_INSN_LEN 4 1045 1046 static inline int insn_len(uint16_t first_word) 1047 { 1048 return (first_word & 3) == 3 ? 4 : 2; 1049 } 1050 1051 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1052 { 1053 /* 1054 * A table with predicate (i.e., guard) functions and decoder functions 1055 * that are tested in-order until a decoder matches onto the opcode. 1056 */ 1057 static const struct { 1058 bool (*guard_func)(DisasContext *); 1059 bool (*decode_func)(DisasContext *, uint32_t); 1060 } decoders[] = { 1061 { always_true_p, decode_insn32 }, 1062 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1063 }; 1064 1065 /* Check for compressed insn */ 1066 if (insn_len(opcode) == 2) { 1067 if (!has_ext(ctx, RVC)) { 1068 gen_exception_illegal(ctx); 1069 } else { 1070 ctx->opcode = opcode; 1071 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1072 if (decode_insn16(ctx, opcode)) { 1073 return; 1074 } 1075 } 1076 } else { 1077 uint32_t opcode32 = opcode; 1078 opcode32 = deposit32(opcode32, 16, 16, 1079 translator_lduw(env, &ctx->base, 1080 ctx->base.pc_next + 2)); 1081 ctx->opcode = opcode32; 1082 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1083 1084 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1085 if (decoders[i].guard_func(ctx) && 1086 decoders[i].decode_func(ctx, opcode32)) { 1087 return; 1088 } 1089 } 1090 } 1091 1092 gen_exception_illegal(ctx); 1093 } 1094 1095 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1096 { 1097 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1098 CPURISCVState *env = cs->env_ptr; 1099 RISCVCPU *cpu = RISCV_CPU(cs); 1100 uint32_t tb_flags = ctx->base.tb->flags; 1101 1102 ctx->pc_succ_insn = ctx->base.pc_first; 1103 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1104 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1105 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1106 ctx->priv_ver = env->priv_ver; 1107 #if !defined(CONFIG_USER_ONLY) 1108 if (riscv_has_ext(env, RVH)) { 1109 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1110 } else { 1111 ctx->virt_enabled = false; 1112 } 1113 #else 1114 ctx->virt_enabled = false; 1115 #endif 1116 ctx->misa_ext = env->misa_ext; 1117 ctx->frm = -1; /* unknown rounding mode */ 1118 ctx->cfg_ptr = &(cpu->cfg); 1119 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1120 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1121 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1122 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1123 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1124 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1125 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1126 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1127 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1128 ctx->vstart = env->vstart; 1129 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1130 ctx->misa_mxl_max = env->misa_mxl_max; 1131 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1132 ctx->cs = cs; 1133 ctx->ntemp = 0; 1134 memset(ctx->temp, 0, sizeof(ctx->temp)); 1135 ctx->nftemp = 0; 1136 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1137 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1138 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1139 ctx->zero = tcg_constant_tl(0); 1140 } 1141 1142 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1143 { 1144 } 1145 1146 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1147 { 1148 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1149 1150 tcg_gen_insn_start(ctx->base.pc_next, 0); 1151 ctx->insn_start = tcg_last_op(); 1152 } 1153 1154 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1155 { 1156 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1157 CPURISCVState *env = cpu->env_ptr; 1158 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1159 int i; 1160 1161 ctx->ol = ctx->xl; 1162 decode_opc(env, ctx, opcode16); 1163 ctx->base.pc_next = ctx->pc_succ_insn; 1164 1165 for (i = ctx->ntemp - 1; i >= 0; --i) { 1166 tcg_temp_free(ctx->temp[i]); 1167 ctx->temp[i] = NULL; 1168 } 1169 ctx->ntemp = 0; 1170 for (i = ctx->nftemp - 1; i >= 0; --i) { 1171 tcg_temp_free_i64(ctx->ftemp[i]); 1172 ctx->ftemp[i] = NULL; 1173 } 1174 ctx->nftemp = 0; 1175 1176 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1177 if (ctx->base.is_jmp == DISAS_NEXT) { 1178 if (!is_same_page(&ctx->base, ctx->base.pc_next)) { 1179 ctx->base.is_jmp = DISAS_TOO_MANY; 1180 } else { 1181 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1182 1183 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1184 uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next); 1185 int len = insn_len(next_insn); 1186 1187 if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) { 1188 ctx->base.is_jmp = DISAS_TOO_MANY; 1189 } 1190 } 1191 } 1192 } 1193 } 1194 1195 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1196 { 1197 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1198 1199 switch (ctx->base.is_jmp) { 1200 case DISAS_TOO_MANY: 1201 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1202 break; 1203 case DISAS_NORETURN: 1204 break; 1205 default: 1206 g_assert_not_reached(); 1207 } 1208 } 1209 1210 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1211 CPUState *cpu, FILE *logfile) 1212 { 1213 #ifndef CONFIG_USER_ONLY 1214 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1215 CPURISCVState *env = &rvcpu->env; 1216 #endif 1217 1218 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1219 #ifndef CONFIG_USER_ONLY 1220 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1221 env->priv, env->virt); 1222 #endif 1223 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1224 } 1225 1226 static const TranslatorOps riscv_tr_ops = { 1227 .init_disas_context = riscv_tr_init_disas_context, 1228 .tb_start = riscv_tr_tb_start, 1229 .insn_start = riscv_tr_insn_start, 1230 .translate_insn = riscv_tr_translate_insn, 1231 .tb_stop = riscv_tr_tb_stop, 1232 .disas_log = riscv_tr_disas_log, 1233 }; 1234 1235 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns, 1236 target_ulong pc, void *host_pc) 1237 { 1238 DisasContext ctx; 1239 1240 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1241 } 1242 1243 void riscv_translate_init(void) 1244 { 1245 int i; 1246 1247 /* 1248 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1249 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1250 * unless you specifically block reads/writes to reg 0. 1251 */ 1252 cpu_gpr[0] = NULL; 1253 cpu_gprh[0] = NULL; 1254 1255 for (i = 1; i < 32; i++) { 1256 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1257 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1258 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1259 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1260 } 1261 1262 for (i = 0; i < 32; i++) { 1263 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1264 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1265 } 1266 1267 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1268 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1269 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1270 "vstart"); 1271 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1272 "load_res"); 1273 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1274 "load_val"); 1275 /* Assign PM CSRs to tcg globals */ 1276 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1277 "pmmask"); 1278 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1279 "pmbase"); 1280 } 1281