1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint16_t vlen; 100 uint16_t elen; 101 target_ulong vstart; 102 bool vl_eq_vlmax; 103 uint8_t ntemp; 104 CPUState *cs; 105 TCGv zero; 106 /* Space for 3 operands plus 1 extra for address computation. */ 107 TCGv temp[4]; 108 /* PointerMasking extension */ 109 bool pm_enabled; 110 TCGv pm_mask; 111 TCGv pm_base; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void generate_exception(DisasContext *ctx, int excp) 195 { 196 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 198 ctx->base.is_jmp = DISAS_NORETURN; 199 } 200 201 static void generate_exception_mtval(DisasContext *ctx, int excp) 202 { 203 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 204 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 205 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 206 ctx->base.is_jmp = DISAS_NORETURN; 207 } 208 209 static void gen_exception_illegal(DisasContext *ctx) 210 { 211 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 212 } 213 214 static void gen_exception_inst_addr_mis(DisasContext *ctx) 215 { 216 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 217 } 218 219 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 220 { 221 if (translator_use_goto_tb(&ctx->base, dest)) { 222 tcg_gen_goto_tb(n); 223 tcg_gen_movi_tl(cpu_pc, dest); 224 tcg_gen_exit_tb(ctx->base.tb, n); 225 } else { 226 tcg_gen_movi_tl(cpu_pc, dest); 227 tcg_gen_lookup_and_goto_ptr(); 228 } 229 } 230 231 /* 232 * Wrappers for getting reg values. 233 * 234 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 235 * constant zero as a source, and an uninitialized sink as destination. 236 * 237 * Further, we may provide an extension for word operations. 238 */ 239 static TCGv temp_new(DisasContext *ctx) 240 { 241 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 242 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 243 } 244 245 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 246 { 247 TCGv t; 248 249 if (reg_num == 0) { 250 return ctx->zero; 251 } 252 253 switch (get_ol(ctx)) { 254 case MXL_RV32: 255 switch (ext) { 256 case EXT_NONE: 257 break; 258 case EXT_SIGN: 259 t = temp_new(ctx); 260 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 261 return t; 262 case EXT_ZERO: 263 t = temp_new(ctx); 264 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 265 return t; 266 default: 267 g_assert_not_reached(); 268 } 269 break; 270 case MXL_RV64: 271 case MXL_RV128: 272 break; 273 default: 274 g_assert_not_reached(); 275 } 276 return cpu_gpr[reg_num]; 277 } 278 279 static TCGv get_gprh(DisasContext *ctx, int reg_num) 280 { 281 assert(get_xl(ctx) == MXL_RV128); 282 if (reg_num == 0) { 283 return ctx->zero; 284 } 285 return cpu_gprh[reg_num]; 286 } 287 288 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 289 { 290 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 291 return temp_new(ctx); 292 } 293 return cpu_gpr[reg_num]; 294 } 295 296 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 297 { 298 if (reg_num == 0) { 299 return temp_new(ctx); 300 } 301 return cpu_gprh[reg_num]; 302 } 303 304 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 305 { 306 if (reg_num != 0) { 307 switch (get_ol(ctx)) { 308 case MXL_RV32: 309 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 310 break; 311 case MXL_RV64: 312 case MXL_RV128: 313 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 314 break; 315 default: 316 g_assert_not_reached(); 317 } 318 319 if (get_xl_max(ctx) == MXL_RV128) { 320 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 321 } 322 } 323 } 324 325 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 326 { 327 assert(get_ol(ctx) == MXL_RV128); 328 if (reg_num != 0) { 329 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 330 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 331 } 332 } 333 334 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 335 { 336 target_ulong next_pc; 337 338 /* check misaligned: */ 339 next_pc = ctx->base.pc_next + imm; 340 if (!has_ext(ctx, RVC)) { 341 if ((next_pc & 0x3) != 0) { 342 gen_exception_inst_addr_mis(ctx); 343 return; 344 } 345 } 346 if (rd != 0) { 347 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 348 } 349 350 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 351 ctx->base.is_jmp = DISAS_NORETURN; 352 } 353 354 /* 355 * Generates address adjustment for PointerMasking 356 */ 357 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 358 { 359 TCGv temp; 360 if (!s->pm_enabled) { 361 /* Load unmodified address */ 362 return src; 363 } else { 364 temp = temp_new(s); 365 tcg_gen_andc_tl(temp, src, s->pm_mask); 366 tcg_gen_or_tl(temp, temp, s->pm_base); 367 return temp; 368 } 369 } 370 371 #ifndef CONFIG_USER_ONLY 372 /* The states of mstatus_fs are: 373 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 374 * We will have already diagnosed disabled state, 375 * and need to turn initial/clean into dirty. 376 */ 377 static void mark_fs_dirty(DisasContext *ctx) 378 { 379 TCGv tmp; 380 381 if (ctx->mstatus_fs != MSTATUS_FS) { 382 /* Remember the state change for the rest of the TB. */ 383 ctx->mstatus_fs = MSTATUS_FS; 384 385 tmp = tcg_temp_new(); 386 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 387 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 388 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 389 tcg_temp_free(tmp); 390 } 391 392 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 393 /* Remember the stage change for the rest of the TB. */ 394 ctx->mstatus_hs_fs = MSTATUS_FS; 395 396 tmp = tcg_temp_new(); 397 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 398 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 399 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 400 tcg_temp_free(tmp); 401 } 402 } 403 #else 404 static inline void mark_fs_dirty(DisasContext *ctx) { } 405 #endif 406 407 #ifndef CONFIG_USER_ONLY 408 /* The states of mstatus_vs are: 409 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 410 * We will have already diagnosed disabled state, 411 * and need to turn initial/clean into dirty. 412 */ 413 static void mark_vs_dirty(DisasContext *ctx) 414 { 415 TCGv tmp; 416 417 if (ctx->mstatus_vs != MSTATUS_VS) { 418 /* Remember the state change for the rest of the TB. */ 419 ctx->mstatus_vs = MSTATUS_VS; 420 421 tmp = tcg_temp_new(); 422 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 423 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 424 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 425 tcg_temp_free(tmp); 426 } 427 428 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 429 /* Remember the stage change for the rest of the TB. */ 430 ctx->mstatus_hs_vs = MSTATUS_VS; 431 432 tmp = tcg_temp_new(); 433 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 434 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 435 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 436 tcg_temp_free(tmp); 437 } 438 } 439 #else 440 static inline void mark_vs_dirty(DisasContext *ctx) { } 441 #endif 442 443 static void gen_set_rm(DisasContext *ctx, int rm) 444 { 445 if (ctx->frm == rm) { 446 return; 447 } 448 ctx->frm = rm; 449 450 if (rm == RISCV_FRM_ROD) { 451 gen_helper_set_rod_rounding_mode(cpu_env); 452 return; 453 } 454 455 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 456 } 457 458 static int ex_plus_1(DisasContext *ctx, int nf) 459 { 460 return nf + 1; 461 } 462 463 #define EX_SH(amount) \ 464 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 465 { \ 466 return imm << amount; \ 467 } 468 EX_SH(1) 469 EX_SH(2) 470 EX_SH(3) 471 EX_SH(4) 472 EX_SH(12) 473 474 #define REQUIRE_EXT(ctx, ext) do { \ 475 if (!has_ext(ctx, ext)) { \ 476 return false; \ 477 } \ 478 } while (0) 479 480 #define REQUIRE_32BIT(ctx) do { \ 481 if (get_xl(ctx) != MXL_RV32) { \ 482 return false; \ 483 } \ 484 } while (0) 485 486 #define REQUIRE_64BIT(ctx) do { \ 487 if (get_xl(ctx) != MXL_RV64) { \ 488 return false; \ 489 } \ 490 } while (0) 491 492 #define REQUIRE_128BIT(ctx) do { \ 493 if (get_xl(ctx) != MXL_RV128) { \ 494 return false; \ 495 } \ 496 } while (0) 497 498 #define REQUIRE_64_OR_128BIT(ctx) do { \ 499 if (get_xl(ctx) == MXL_RV32) { \ 500 return false; \ 501 } \ 502 } while (0) 503 504 static int ex_rvc_register(DisasContext *ctx, int reg) 505 { 506 return 8 + reg; 507 } 508 509 static int ex_rvc_shifti(DisasContext *ctx, int imm) 510 { 511 /* For RV128 a shamt of 0 means a shift by 64. */ 512 return imm ? imm : 64; 513 } 514 515 /* Include the auto-generated decoder for 32 bit insn */ 516 #include "decode-insn32.c.inc" 517 518 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 519 void (*func)(TCGv, TCGv, target_long)) 520 { 521 TCGv dest = dest_gpr(ctx, a->rd); 522 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 523 524 func(dest, src1, a->imm); 525 526 gen_set_gpr(ctx, a->rd, dest); 527 528 return true; 529 } 530 531 static bool gen_logic(DisasContext *ctx, arg_r *a, 532 void (*func)(TCGv, TCGv, TCGv)) 533 { 534 TCGv dest = dest_gpr(ctx, a->rd); 535 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 536 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 537 538 func(dest, src1, src2); 539 540 gen_set_gpr(ctx, a->rd, dest); 541 542 return true; 543 } 544 545 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 546 void (*func)(TCGv, TCGv, target_long)) 547 { 548 TCGv dest = dest_gpr(ctx, a->rd); 549 TCGv src1 = get_gpr(ctx, a->rs1, ext); 550 551 func(dest, src1, a->imm); 552 553 gen_set_gpr(ctx, a->rd, dest); 554 return true; 555 } 556 557 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 558 void (*func)(TCGv, TCGv, TCGv)) 559 { 560 TCGv dest = dest_gpr(ctx, a->rd); 561 TCGv src1 = get_gpr(ctx, a->rs1, ext); 562 TCGv src2 = tcg_constant_tl(a->imm); 563 564 func(dest, src1, src2); 565 566 gen_set_gpr(ctx, a->rd, dest); 567 return true; 568 } 569 570 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 571 void (*func)(TCGv, TCGv, TCGv)) 572 { 573 TCGv dest = dest_gpr(ctx, a->rd); 574 TCGv src1 = get_gpr(ctx, a->rs1, ext); 575 TCGv src2 = get_gpr(ctx, a->rs2, ext); 576 577 func(dest, src1, src2); 578 579 gen_set_gpr(ctx, a->rd, dest); 580 return true; 581 } 582 583 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 584 void (*f_tl)(TCGv, TCGv, TCGv), 585 void (*f_32)(TCGv, TCGv, TCGv)) 586 { 587 int olen = get_olen(ctx); 588 589 if (olen != TARGET_LONG_BITS) { 590 if (olen == 32) { 591 f_tl = f_32; 592 } else { 593 g_assert_not_reached(); 594 } 595 } 596 return gen_arith(ctx, a, ext, f_tl); 597 } 598 599 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 600 void (*func)(TCGv, TCGv, target_long)) 601 { 602 TCGv dest, src1; 603 int max_len = get_olen(ctx); 604 605 if (a->shamt >= max_len) { 606 return false; 607 } 608 609 dest = dest_gpr(ctx, a->rd); 610 src1 = get_gpr(ctx, a->rs1, ext); 611 612 func(dest, src1, a->shamt); 613 614 gen_set_gpr(ctx, a->rd, dest); 615 return true; 616 } 617 618 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 619 DisasExtend ext, 620 void (*f_tl)(TCGv, TCGv, target_long), 621 void (*f_32)(TCGv, TCGv, target_long)) 622 { 623 int olen = get_olen(ctx); 624 if (olen != TARGET_LONG_BITS) { 625 if (olen == 32) { 626 f_tl = f_32; 627 } else { 628 g_assert_not_reached(); 629 } 630 } 631 return gen_shift_imm_fn(ctx, a, ext, f_tl); 632 } 633 634 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 635 void (*func)(TCGv, TCGv, TCGv)) 636 { 637 TCGv dest, src1, src2; 638 int max_len = get_olen(ctx); 639 640 if (a->shamt >= max_len) { 641 return false; 642 } 643 644 dest = dest_gpr(ctx, a->rd); 645 src1 = get_gpr(ctx, a->rs1, ext); 646 src2 = tcg_constant_tl(a->shamt); 647 648 func(dest, src1, src2); 649 650 gen_set_gpr(ctx, a->rd, dest); 651 return true; 652 } 653 654 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 655 void (*func)(TCGv, TCGv, TCGv)) 656 { 657 TCGv dest = dest_gpr(ctx, a->rd); 658 TCGv src1 = get_gpr(ctx, a->rs1, ext); 659 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 660 TCGv ext2 = tcg_temp_new(); 661 662 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 663 func(dest, src1, ext2); 664 665 gen_set_gpr(ctx, a->rd, dest); 666 tcg_temp_free(ext2); 667 return true; 668 } 669 670 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 671 void (*f_tl)(TCGv, TCGv, TCGv), 672 void (*f_32)(TCGv, TCGv, TCGv)) 673 { 674 int olen = get_olen(ctx); 675 if (olen != TARGET_LONG_BITS) { 676 if (olen == 32) { 677 f_tl = f_32; 678 } else { 679 g_assert_not_reached(); 680 } 681 } 682 return gen_shift(ctx, a, ext, f_tl); 683 } 684 685 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 686 void (*func)(TCGv, TCGv)) 687 { 688 TCGv dest = dest_gpr(ctx, a->rd); 689 TCGv src1 = get_gpr(ctx, a->rs1, ext); 690 691 func(dest, src1); 692 693 gen_set_gpr(ctx, a->rd, dest); 694 return true; 695 } 696 697 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 698 void (*f_tl)(TCGv, TCGv), 699 void (*f_32)(TCGv, TCGv)) 700 { 701 int olen = get_olen(ctx); 702 703 if (olen != TARGET_LONG_BITS) { 704 if (olen == 32) { 705 f_tl = f_32; 706 } else { 707 g_assert_not_reached(); 708 } 709 } 710 return gen_unary(ctx, a, ext, f_tl); 711 } 712 713 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 714 { 715 DisasContext *ctx = container_of(dcbase, DisasContext, base); 716 CPUState *cpu = ctx->cs; 717 CPURISCVState *env = cpu->env_ptr; 718 719 return cpu_ldl_code(env, pc); 720 } 721 722 /* Include insn module translation function */ 723 #include "insn_trans/trans_rvi.c.inc" 724 #include "insn_trans/trans_rvm.c.inc" 725 #include "insn_trans/trans_rva.c.inc" 726 #include "insn_trans/trans_rvf.c.inc" 727 #include "insn_trans/trans_rvd.c.inc" 728 #include "insn_trans/trans_rvh.c.inc" 729 #include "insn_trans/trans_rvv.c.inc" 730 #include "insn_trans/trans_rvb.c.inc" 731 #include "insn_trans/trans_rvzfh.c.inc" 732 #include "insn_trans/trans_privileged.c.inc" 733 734 /* Include the auto-generated decoder for 16 bit insn */ 735 #include "decode-insn16.c.inc" 736 737 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 738 { 739 /* check for compressed insn */ 740 if (extract16(opcode, 0, 2) != 3) { 741 if (!has_ext(ctx, RVC)) { 742 gen_exception_illegal(ctx); 743 } else { 744 ctx->pc_succ_insn = ctx->base.pc_next + 2; 745 if (!decode_insn16(ctx, opcode)) { 746 gen_exception_illegal(ctx); 747 } 748 } 749 } else { 750 uint32_t opcode32 = opcode; 751 opcode32 = deposit32(opcode32, 16, 16, 752 translator_lduw(env, &ctx->base, 753 ctx->base.pc_next + 2)); 754 ctx->pc_succ_insn = ctx->base.pc_next + 4; 755 if (!decode_insn32(ctx, opcode32)) { 756 gen_exception_illegal(ctx); 757 } 758 } 759 } 760 761 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 762 { 763 DisasContext *ctx = container_of(dcbase, DisasContext, base); 764 CPURISCVState *env = cs->env_ptr; 765 RISCVCPU *cpu = RISCV_CPU(cs); 766 uint32_t tb_flags = ctx->base.tb->flags; 767 768 ctx->pc_succ_insn = ctx->base.pc_first; 769 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 770 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 771 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 772 ctx->priv_ver = env->priv_ver; 773 #if !defined(CONFIG_USER_ONLY) 774 if (riscv_has_ext(env, RVH)) { 775 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 776 } else { 777 ctx->virt_enabled = false; 778 } 779 #else 780 ctx->virt_enabled = false; 781 #endif 782 ctx->misa_ext = env->misa_ext; 783 ctx->frm = -1; /* unknown rounding mode */ 784 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 785 ctx->ext_zfh = cpu->cfg.ext_zfh; 786 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 787 ctx->vlen = cpu->cfg.vlen; 788 ctx->elen = cpu->cfg.elen; 789 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 790 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 791 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 792 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 793 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 794 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 795 ctx->vstart = env->vstart; 796 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 797 ctx->misa_mxl_max = env->misa_mxl_max; 798 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 799 ctx->cs = cs; 800 ctx->ntemp = 0; 801 memset(ctx->temp, 0, sizeof(ctx->temp)); 802 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 803 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 804 ctx->pm_mask = pm_mask[priv]; 805 ctx->pm_base = pm_base[priv]; 806 807 ctx->zero = tcg_constant_tl(0); 808 } 809 810 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 811 { 812 } 813 814 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 815 { 816 DisasContext *ctx = container_of(dcbase, DisasContext, base); 817 818 tcg_gen_insn_start(ctx->base.pc_next); 819 } 820 821 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 822 { 823 DisasContext *ctx = container_of(dcbase, DisasContext, base); 824 CPURISCVState *env = cpu->env_ptr; 825 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 826 827 ctx->ol = ctx->xl; 828 decode_opc(env, ctx, opcode16); 829 ctx->base.pc_next = ctx->pc_succ_insn; 830 831 for (int i = ctx->ntemp - 1; i >= 0; --i) { 832 tcg_temp_free(ctx->temp[i]); 833 ctx->temp[i] = NULL; 834 } 835 ctx->ntemp = 0; 836 837 if (ctx->base.is_jmp == DISAS_NEXT) { 838 target_ulong page_start; 839 840 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 841 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 842 ctx->base.is_jmp = DISAS_TOO_MANY; 843 } 844 } 845 } 846 847 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 848 { 849 DisasContext *ctx = container_of(dcbase, DisasContext, base); 850 851 switch (ctx->base.is_jmp) { 852 case DISAS_TOO_MANY: 853 gen_goto_tb(ctx, 0, ctx->base.pc_next); 854 break; 855 case DISAS_NORETURN: 856 break; 857 default: 858 g_assert_not_reached(); 859 } 860 } 861 862 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 863 { 864 #ifndef CONFIG_USER_ONLY 865 RISCVCPU *rvcpu = RISCV_CPU(cpu); 866 CPURISCVState *env = &rvcpu->env; 867 #endif 868 869 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 870 #ifndef CONFIG_USER_ONLY 871 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 872 #endif 873 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 874 } 875 876 static const TranslatorOps riscv_tr_ops = { 877 .init_disas_context = riscv_tr_init_disas_context, 878 .tb_start = riscv_tr_tb_start, 879 .insn_start = riscv_tr_insn_start, 880 .translate_insn = riscv_tr_translate_insn, 881 .tb_stop = riscv_tr_tb_stop, 882 .disas_log = riscv_tr_disas_log, 883 }; 884 885 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 886 { 887 DisasContext ctx; 888 889 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 890 } 891 892 void riscv_translate_init(void) 893 { 894 int i; 895 896 /* 897 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 898 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 899 * unless you specifically block reads/writes to reg 0. 900 */ 901 cpu_gpr[0] = NULL; 902 cpu_gprh[0] = NULL; 903 904 for (i = 1; i < 32; i++) { 905 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 906 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 907 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 908 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 909 } 910 911 for (i = 0; i < 32; i++) { 912 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 913 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 914 } 915 916 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 917 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 918 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 919 "vstart"); 920 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 921 "load_res"); 922 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 923 "load_val"); 924 #ifndef CONFIG_USER_ONLY 925 /* Assign PM CSRs to tcg globals */ 926 pm_mask[PRV_U] = 927 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 928 pm_base[PRV_U] = 929 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 930 pm_mask[PRV_S] = 931 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 932 pm_base[PRV_S] = 933 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 934 pm_mask[PRV_M] = 935 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 936 pm_base[PRV_M] = 937 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 938 #endif 939 } 940