1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 34 /* global register indices */ 35 static TCGv cpu_gpr[32], cpu_pc, cpu_vl; 36 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 37 static TCGv load_res; 38 static TCGv load_val; 39 /* globals for PM CSRs */ 40 static TCGv pm_mask[4]; 41 static TCGv pm_base[4]; 42 43 #include "exec/gen-icount.h" 44 45 /* 46 * If an operation is being performed on less than TARGET_LONG_BITS, 47 * it may require the inputs to be sign- or zero-extended; which will 48 * depend on the exact operation being performed. 49 */ 50 typedef enum { 51 EXT_NONE, 52 EXT_SIGN, 53 EXT_ZERO, 54 } DisasExtend; 55 56 typedef struct DisasContext { 57 DisasContextBase base; 58 /* pc_succ_insn points to the instruction following base.pc_next */ 59 target_ulong pc_succ_insn; 60 target_ulong priv_ver; 61 RISCVMXL xl; 62 uint32_t misa_ext; 63 uint32_t opcode; 64 uint32_t mstatus_fs; 65 uint32_t mstatus_hs_fs; 66 uint32_t mem_idx; 67 /* Remember the rounding mode encoded in the previous fp instruction, 68 which we have already installed into env->fp_status. Or -1 for 69 no previous fp instruction. Note that we exit the TB when writing 70 to any system register, which includes CSR_FRM, so we do not have 71 to reset this known value. */ 72 int frm; 73 RISCVMXL ol; 74 bool virt_enabled; 75 bool ext_ifencei; 76 bool ext_zfh; 77 bool hlsx; 78 /* vector extension */ 79 bool vill; 80 uint8_t lmul; 81 uint8_t sew; 82 uint16_t vlen; 83 uint16_t mlen; 84 bool vl_eq_vlmax; 85 uint8_t ntemp; 86 CPUState *cs; 87 TCGv zero; 88 /* Space for 3 operands plus 1 extra for address computation. */ 89 TCGv temp[4]; 90 /* PointerMasking extension */ 91 bool pm_enabled; 92 TCGv pm_mask; 93 TCGv pm_base; 94 } DisasContext; 95 96 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 97 { 98 return ctx->misa_ext & ext; 99 } 100 101 #ifdef TARGET_RISCV32 102 #define get_xl(ctx) MXL_RV32 103 #elif defined(CONFIG_USER_ONLY) 104 #define get_xl(ctx) MXL_RV64 105 #else 106 #define get_xl(ctx) ((ctx)->xl) 107 #endif 108 109 /* The word size for this machine mode. */ 110 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 111 { 112 return 16 << get_xl(ctx); 113 } 114 115 /* The operation length, as opposed to the xlen. */ 116 #ifdef TARGET_RISCV32 117 #define get_ol(ctx) MXL_RV32 118 #else 119 #define get_ol(ctx) ((ctx)->ol) 120 #endif 121 122 static inline int get_olen(DisasContext *ctx) 123 { 124 return 16 << get_ol(ctx); 125 } 126 127 /* 128 * RISC-V requires NaN-boxing of narrower width floating point values. 129 * This applies when a 32-bit value is assigned to a 64-bit FP register. 130 * For consistency and simplicity, we nanbox results even when the RVD 131 * extension is not present. 132 */ 133 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 134 { 135 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 136 } 137 138 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 139 { 140 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 141 } 142 143 /* 144 * A narrow n-bit operation, where n < FLEN, checks that input operands 145 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 146 * If so, the least-significant bits of the input are used, otherwise the 147 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 148 * 149 * Here, the result is always nan-boxed, even the canonical nan. 150 */ 151 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 152 { 153 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 154 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 155 156 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 157 } 158 159 static void generate_exception(DisasContext *ctx, int excp) 160 { 161 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 162 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 163 ctx->base.is_jmp = DISAS_NORETURN; 164 } 165 166 static void generate_exception_mtval(DisasContext *ctx, int excp) 167 { 168 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 169 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 170 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 171 ctx->base.is_jmp = DISAS_NORETURN; 172 } 173 174 static void gen_exception_illegal(DisasContext *ctx) 175 { 176 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 177 } 178 179 static void gen_exception_inst_addr_mis(DisasContext *ctx) 180 { 181 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 182 } 183 184 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 185 { 186 if (translator_use_goto_tb(&ctx->base, dest)) { 187 tcg_gen_goto_tb(n); 188 tcg_gen_movi_tl(cpu_pc, dest); 189 tcg_gen_exit_tb(ctx->base.tb, n); 190 } else { 191 tcg_gen_movi_tl(cpu_pc, dest); 192 tcg_gen_lookup_and_goto_ptr(); 193 } 194 } 195 196 /* 197 * Wrappers for getting reg values. 198 * 199 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 200 * constant zero as a source, and an uninitialized sink as destination. 201 * 202 * Further, we may provide an extension for word operations. 203 */ 204 static TCGv temp_new(DisasContext *ctx) 205 { 206 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 207 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 208 } 209 210 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 211 { 212 TCGv t; 213 214 if (reg_num == 0) { 215 return ctx->zero; 216 } 217 218 switch (get_ol(ctx)) { 219 case MXL_RV32: 220 switch (ext) { 221 case EXT_NONE: 222 break; 223 case EXT_SIGN: 224 t = temp_new(ctx); 225 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 226 return t; 227 case EXT_ZERO: 228 t = temp_new(ctx); 229 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 230 return t; 231 default: 232 g_assert_not_reached(); 233 } 234 break; 235 case MXL_RV64: 236 break; 237 default: 238 g_assert_not_reached(); 239 } 240 return cpu_gpr[reg_num]; 241 } 242 243 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 244 { 245 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 246 return temp_new(ctx); 247 } 248 return cpu_gpr[reg_num]; 249 } 250 251 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 252 { 253 if (reg_num != 0) { 254 switch (get_ol(ctx)) { 255 case MXL_RV32: 256 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 257 break; 258 case MXL_RV64: 259 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 260 break; 261 default: 262 g_assert_not_reached(); 263 } 264 } 265 } 266 267 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 268 { 269 target_ulong next_pc; 270 271 /* check misaligned: */ 272 next_pc = ctx->base.pc_next + imm; 273 if (!has_ext(ctx, RVC)) { 274 if ((next_pc & 0x3) != 0) { 275 gen_exception_inst_addr_mis(ctx); 276 return; 277 } 278 } 279 if (rd != 0) { 280 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 281 } 282 283 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 284 ctx->base.is_jmp = DISAS_NORETURN; 285 } 286 287 /* 288 * Generates address adjustment for PointerMasking 289 */ 290 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 291 { 292 TCGv temp; 293 if (!s->pm_enabled) { 294 /* Load unmodified address */ 295 return src; 296 } else { 297 temp = temp_new(s); 298 tcg_gen_andc_tl(temp, src, s->pm_mask); 299 tcg_gen_or_tl(temp, temp, s->pm_base); 300 return temp; 301 } 302 } 303 304 #ifndef CONFIG_USER_ONLY 305 /* The states of mstatus_fs are: 306 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 307 * We will have already diagnosed disabled state, 308 * and need to turn initial/clean into dirty. 309 */ 310 static void mark_fs_dirty(DisasContext *ctx) 311 { 312 TCGv tmp; 313 314 if (ctx->mstatus_fs != MSTATUS_FS) { 315 /* Remember the state change for the rest of the TB. */ 316 ctx->mstatus_fs = MSTATUS_FS; 317 318 tmp = tcg_temp_new(); 319 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 320 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 321 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 322 tcg_temp_free(tmp); 323 } 324 325 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 326 /* Remember the stage change for the rest of the TB. */ 327 ctx->mstatus_hs_fs = MSTATUS_FS; 328 329 tmp = tcg_temp_new(); 330 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 331 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 332 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 333 tcg_temp_free(tmp); 334 } 335 } 336 #else 337 static inline void mark_fs_dirty(DisasContext *ctx) { } 338 #endif 339 340 static void gen_set_rm(DisasContext *ctx, int rm) 341 { 342 if (ctx->frm == rm) { 343 return; 344 } 345 ctx->frm = rm; 346 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 347 } 348 349 static int ex_plus_1(DisasContext *ctx, int nf) 350 { 351 return nf + 1; 352 } 353 354 #define EX_SH(amount) \ 355 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 356 { \ 357 return imm << amount; \ 358 } 359 EX_SH(1) 360 EX_SH(2) 361 EX_SH(3) 362 EX_SH(4) 363 EX_SH(12) 364 365 #define REQUIRE_EXT(ctx, ext) do { \ 366 if (!has_ext(ctx, ext)) { \ 367 return false; \ 368 } \ 369 } while (0) 370 371 #define REQUIRE_32BIT(ctx) do { \ 372 if (get_xl(ctx) != MXL_RV32) { \ 373 return false; \ 374 } \ 375 } while (0) 376 377 #define REQUIRE_64BIT(ctx) do { \ 378 if (get_xl(ctx) < MXL_RV64) { \ 379 return false; \ 380 } \ 381 } while (0) 382 383 static int ex_rvc_register(DisasContext *ctx, int reg) 384 { 385 return 8 + reg; 386 } 387 388 static int ex_rvc_shifti(DisasContext *ctx, int imm) 389 { 390 /* For RV128 a shamt of 0 means a shift by 64. */ 391 return imm ? imm : 64; 392 } 393 394 /* Include the auto-generated decoder for 32 bit insn */ 395 #include "decode-insn32.c.inc" 396 397 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 398 void (*func)(TCGv, TCGv, target_long)) 399 { 400 TCGv dest = dest_gpr(ctx, a->rd); 401 TCGv src1 = get_gpr(ctx, a->rs1, ext); 402 403 func(dest, src1, a->imm); 404 405 gen_set_gpr(ctx, a->rd, dest); 406 return true; 407 } 408 409 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 410 void (*func)(TCGv, TCGv, TCGv)) 411 { 412 TCGv dest = dest_gpr(ctx, a->rd); 413 TCGv src1 = get_gpr(ctx, a->rs1, ext); 414 TCGv src2 = tcg_constant_tl(a->imm); 415 416 func(dest, src1, src2); 417 418 gen_set_gpr(ctx, a->rd, dest); 419 return true; 420 } 421 422 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 423 void (*func)(TCGv, TCGv, TCGv)) 424 { 425 TCGv dest = dest_gpr(ctx, a->rd); 426 TCGv src1 = get_gpr(ctx, a->rs1, ext); 427 TCGv src2 = get_gpr(ctx, a->rs2, ext); 428 429 func(dest, src1, src2); 430 431 gen_set_gpr(ctx, a->rd, dest); 432 return true; 433 } 434 435 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 436 void (*f_tl)(TCGv, TCGv, TCGv), 437 void (*f_32)(TCGv, TCGv, TCGv)) 438 { 439 int olen = get_olen(ctx); 440 441 if (olen != TARGET_LONG_BITS) { 442 if (olen == 32) { 443 f_tl = f_32; 444 } else { 445 g_assert_not_reached(); 446 } 447 } 448 return gen_arith(ctx, a, ext, f_tl); 449 } 450 451 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 452 void (*func)(TCGv, TCGv, target_long)) 453 { 454 TCGv dest, src1; 455 int max_len = get_olen(ctx); 456 457 if (a->shamt >= max_len) { 458 return false; 459 } 460 461 dest = dest_gpr(ctx, a->rd); 462 src1 = get_gpr(ctx, a->rs1, ext); 463 464 func(dest, src1, a->shamt); 465 466 gen_set_gpr(ctx, a->rd, dest); 467 return true; 468 } 469 470 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 471 DisasExtend ext, 472 void (*f_tl)(TCGv, TCGv, target_long), 473 void (*f_32)(TCGv, TCGv, target_long)) 474 { 475 int olen = get_olen(ctx); 476 if (olen != TARGET_LONG_BITS) { 477 if (olen == 32) { 478 f_tl = f_32; 479 } else { 480 g_assert_not_reached(); 481 } 482 } 483 return gen_shift_imm_fn(ctx, a, ext, f_tl); 484 } 485 486 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 487 void (*func)(TCGv, TCGv, TCGv)) 488 { 489 TCGv dest, src1, src2; 490 int max_len = get_olen(ctx); 491 492 if (a->shamt >= max_len) { 493 return false; 494 } 495 496 dest = dest_gpr(ctx, a->rd); 497 src1 = get_gpr(ctx, a->rs1, ext); 498 src2 = tcg_constant_tl(a->shamt); 499 500 func(dest, src1, src2); 501 502 gen_set_gpr(ctx, a->rd, dest); 503 return true; 504 } 505 506 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 507 void (*func)(TCGv, TCGv, TCGv)) 508 { 509 TCGv dest = dest_gpr(ctx, a->rd); 510 TCGv src1 = get_gpr(ctx, a->rs1, ext); 511 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 512 TCGv ext2 = tcg_temp_new(); 513 514 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 515 func(dest, src1, ext2); 516 517 gen_set_gpr(ctx, a->rd, dest); 518 tcg_temp_free(ext2); 519 return true; 520 } 521 522 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 523 void (*f_tl)(TCGv, TCGv, TCGv), 524 void (*f_32)(TCGv, TCGv, TCGv)) 525 { 526 int olen = get_olen(ctx); 527 if (olen != TARGET_LONG_BITS) { 528 if (olen == 32) { 529 f_tl = f_32; 530 } else { 531 g_assert_not_reached(); 532 } 533 } 534 return gen_shift(ctx, a, ext, f_tl); 535 } 536 537 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 538 void (*func)(TCGv, TCGv)) 539 { 540 TCGv dest = dest_gpr(ctx, a->rd); 541 TCGv src1 = get_gpr(ctx, a->rs1, ext); 542 543 func(dest, src1); 544 545 gen_set_gpr(ctx, a->rd, dest); 546 return true; 547 } 548 549 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 550 void (*f_tl)(TCGv, TCGv), 551 void (*f_32)(TCGv, TCGv)) 552 { 553 int olen = get_olen(ctx); 554 555 if (olen != TARGET_LONG_BITS) { 556 if (olen == 32) { 557 f_tl = f_32; 558 } else { 559 g_assert_not_reached(); 560 } 561 } 562 return gen_unary(ctx, a, ext, f_tl); 563 } 564 565 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 566 { 567 DisasContext *ctx = container_of(dcbase, DisasContext, base); 568 CPUState *cpu = ctx->cs; 569 CPURISCVState *env = cpu->env_ptr; 570 571 return cpu_ldl_code(env, pc); 572 } 573 574 /* Include insn module translation function */ 575 #include "insn_trans/trans_rvi.c.inc" 576 #include "insn_trans/trans_rvm.c.inc" 577 #include "insn_trans/trans_rva.c.inc" 578 #include "insn_trans/trans_rvf.c.inc" 579 #include "insn_trans/trans_rvd.c.inc" 580 #include "insn_trans/trans_rvh.c.inc" 581 #include "insn_trans/trans_rvv.c.inc" 582 #include "insn_trans/trans_rvb.c.inc" 583 #include "insn_trans/trans_rvzfh.c.inc" 584 #include "insn_trans/trans_privileged.c.inc" 585 586 /* Include the auto-generated decoder for 16 bit insn */ 587 #include "decode-insn16.c.inc" 588 589 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 590 { 591 /* check for compressed insn */ 592 if (extract16(opcode, 0, 2) != 3) { 593 if (!has_ext(ctx, RVC)) { 594 gen_exception_illegal(ctx); 595 } else { 596 ctx->pc_succ_insn = ctx->base.pc_next + 2; 597 if (!decode_insn16(ctx, opcode)) { 598 gen_exception_illegal(ctx); 599 } 600 } 601 } else { 602 uint32_t opcode32 = opcode; 603 opcode32 = deposit32(opcode32, 16, 16, 604 translator_lduw(env, &ctx->base, 605 ctx->base.pc_next + 2)); 606 ctx->pc_succ_insn = ctx->base.pc_next + 4; 607 if (!decode_insn32(ctx, opcode32)) { 608 gen_exception_illegal(ctx); 609 } 610 } 611 } 612 613 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 614 { 615 DisasContext *ctx = container_of(dcbase, DisasContext, base); 616 CPURISCVState *env = cs->env_ptr; 617 RISCVCPU *cpu = RISCV_CPU(cs); 618 uint32_t tb_flags = ctx->base.tb->flags; 619 620 ctx->pc_succ_insn = ctx->base.pc_first; 621 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 622 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 623 ctx->priv_ver = env->priv_ver; 624 #if !defined(CONFIG_USER_ONLY) 625 if (riscv_has_ext(env, RVH)) { 626 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 627 } else { 628 ctx->virt_enabled = false; 629 } 630 #else 631 ctx->virt_enabled = false; 632 #endif 633 ctx->misa_ext = env->misa_ext; 634 ctx->frm = -1; /* unknown rounding mode */ 635 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 636 ctx->ext_zfh = cpu->cfg.ext_zfh; 637 ctx->vlen = cpu->cfg.vlen; 638 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 639 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 640 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 641 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 642 ctx->lmul = FIELD_EX32(tb_flags, TB_FLAGS, LMUL); 643 ctx->mlen = 1 << (ctx->sew + 3 - ctx->lmul); 644 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 645 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 646 ctx->cs = cs; 647 ctx->ntemp = 0; 648 memset(ctx->temp, 0, sizeof(ctx->temp)); 649 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 650 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 651 ctx->pm_mask = pm_mask[priv]; 652 ctx->pm_base = pm_base[priv]; 653 654 ctx->zero = tcg_constant_tl(0); 655 } 656 657 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 658 { 659 } 660 661 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 662 { 663 DisasContext *ctx = container_of(dcbase, DisasContext, base); 664 665 tcg_gen_insn_start(ctx->base.pc_next); 666 } 667 668 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 669 { 670 DisasContext *ctx = container_of(dcbase, DisasContext, base); 671 CPURISCVState *env = cpu->env_ptr; 672 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 673 674 ctx->ol = ctx->xl; 675 decode_opc(env, ctx, opcode16); 676 ctx->base.pc_next = ctx->pc_succ_insn; 677 678 for (int i = ctx->ntemp - 1; i >= 0; --i) { 679 tcg_temp_free(ctx->temp[i]); 680 ctx->temp[i] = NULL; 681 } 682 ctx->ntemp = 0; 683 684 if (ctx->base.is_jmp == DISAS_NEXT) { 685 target_ulong page_start; 686 687 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 688 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 689 ctx->base.is_jmp = DISAS_TOO_MANY; 690 } 691 } 692 } 693 694 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 695 { 696 DisasContext *ctx = container_of(dcbase, DisasContext, base); 697 698 switch (ctx->base.is_jmp) { 699 case DISAS_TOO_MANY: 700 gen_goto_tb(ctx, 0, ctx->base.pc_next); 701 break; 702 case DISAS_NORETURN: 703 break; 704 default: 705 g_assert_not_reached(); 706 } 707 } 708 709 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 710 { 711 #ifndef CONFIG_USER_ONLY 712 RISCVCPU *rvcpu = RISCV_CPU(cpu); 713 CPURISCVState *env = &rvcpu->env; 714 #endif 715 716 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 717 #ifndef CONFIG_USER_ONLY 718 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 719 #endif 720 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 721 } 722 723 static const TranslatorOps riscv_tr_ops = { 724 .init_disas_context = riscv_tr_init_disas_context, 725 .tb_start = riscv_tr_tb_start, 726 .insn_start = riscv_tr_insn_start, 727 .translate_insn = riscv_tr_translate_insn, 728 .tb_stop = riscv_tr_tb_stop, 729 .disas_log = riscv_tr_disas_log, 730 }; 731 732 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 733 { 734 DisasContext ctx; 735 736 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 737 } 738 739 void riscv_translate_init(void) 740 { 741 int i; 742 743 /* 744 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 745 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 746 * unless you specifically block reads/writes to reg 0. 747 */ 748 cpu_gpr[0] = NULL; 749 750 for (i = 1; i < 32; i++) { 751 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 752 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 753 } 754 755 for (i = 0; i < 32; i++) { 756 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 757 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 758 } 759 760 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 761 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 762 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 763 "load_res"); 764 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 765 "load_val"); 766 #ifndef CONFIG_USER_ONLY 767 /* Assign PM CSRs to tcg globals */ 768 pm_mask[PRV_U] = 769 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 770 pm_base[PRV_U] = 771 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 772 pm_mask[PRV_S] = 773 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 774 pm_base[PRV_S] = 775 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 776 pm_mask[PRV_M] = 777 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 778 pm_base[PRV_M] = 779 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 780 #endif 781 } 782