1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exec/helper-gen.h" 26 27 #include "exec/translator.h" 28 #include "exec/log.h" 29 #include "semihosting/semihost.h" 30 31 #include "internals.h" 32 33 #define HELPER_H "helper.h" 34 #include "exec/helper-info.c.inc" 35 #undef HELPER_H 36 37 #include "tcg/tcg-cpu.h" 38 39 /* global register indices */ 40 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 41 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 42 static TCGv load_res; 43 static TCGv load_val; 44 /* globals for PM CSRs */ 45 static TCGv pm_mask; 46 static TCGv pm_base; 47 48 /* 49 * If an operation is being performed on less than TARGET_LONG_BITS, 50 * it may require the inputs to be sign- or zero-extended; which will 51 * depend on the exact operation being performed. 52 */ 53 typedef enum { 54 EXT_NONE, 55 EXT_SIGN, 56 EXT_ZERO, 57 } DisasExtend; 58 59 typedef struct DisasContext { 60 DisasContextBase base; 61 target_ulong cur_insn_len; 62 target_ulong pc_save; 63 target_ulong priv_ver; 64 RISCVMXL misa_mxl_max; 65 RISCVMXL xl; 66 RISCVMXL address_xl; 67 uint32_t misa_ext; 68 uint32_t opcode; 69 RISCVExtStatus mstatus_fs; 70 RISCVExtStatus mstatus_vs; 71 uint32_t mem_idx; 72 uint32_t priv; 73 /* 74 * Remember the rounding mode encoded in the previous fp instruction, 75 * which we have already installed into env->fp_status. Or -1 for 76 * no previous fp instruction. Note that we exit the TB when writing 77 * to any system register, which includes CSR_FRM, so we do not have 78 * to reset this known value. 79 */ 80 int frm; 81 RISCVMXL ol; 82 bool virt_inst_excp; 83 bool virt_enabled; 84 const RISCVCPUConfig *cfg_ptr; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint8_t vta; 102 uint8_t vma; 103 bool cfg_vta_all_1s; 104 bool vstart_eq_zero; 105 bool vl_eq_vlmax; 106 CPUState *cs; 107 TCGv zero; 108 /* PointerMasking extension */ 109 bool pm_mask_enabled; 110 bool pm_base_enabled; 111 /* Ztso */ 112 bool ztso; 113 /* Use icount trigger for native debug */ 114 bool itrigger; 115 /* FRM is known to contain a valid value. */ 116 bool frm_valid; 117 bool insn_start_updated; 118 const GPtrArray *decoders; 119 /* zicfilp extension. fcfi_enabled, lp expected or not */ 120 bool fcfi_enabled; 121 bool fcfi_lp_expected; 122 /* zicfiss extension, if shadow stack was enabled during TB gen */ 123 bool bcfi_enabled; 124 } DisasContext; 125 126 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 127 { 128 return ctx->misa_ext & ext; 129 } 130 131 #ifdef TARGET_RISCV32 132 #define get_xl(ctx) MXL_RV32 133 #elif defined(CONFIG_USER_ONLY) 134 #define get_xl(ctx) MXL_RV64 135 #else 136 #define get_xl(ctx) ((ctx)->xl) 137 #endif 138 139 #ifdef TARGET_RISCV32 140 #define get_address_xl(ctx) MXL_RV32 141 #elif defined(CONFIG_USER_ONLY) 142 #define get_address_xl(ctx) MXL_RV64 143 #else 144 #define get_address_xl(ctx) ((ctx)->address_xl) 145 #endif 146 147 #define mxl_memop(ctx) ((get_xl(ctx) + 1) | MO_TE) 148 149 /* The word size for this machine mode. */ 150 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 151 { 152 return 16 << get_xl(ctx); 153 } 154 155 /* The operation length, as opposed to the xlen. */ 156 #ifdef TARGET_RISCV32 157 #define get_ol(ctx) MXL_RV32 158 #else 159 #define get_ol(ctx) ((ctx)->ol) 160 #endif 161 162 static inline int get_olen(DisasContext *ctx) 163 { 164 return 16 << get_ol(ctx); 165 } 166 167 /* The maximum register length */ 168 #ifdef TARGET_RISCV32 169 #define get_xl_max(ctx) MXL_RV32 170 #else 171 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 172 #endif 173 174 /* 175 * RISC-V requires NaN-boxing of narrower width floating point values. 176 * This applies when a 32-bit value is assigned to a 64-bit FP register. 177 * For consistency and simplicity, we nanbox results even when the RVD 178 * extension is not present. 179 */ 180 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 181 { 182 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 183 } 184 185 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 186 { 187 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 188 } 189 190 /* 191 * A narrow n-bit operation, where n < FLEN, checks that input operands 192 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 193 * If so, the least-significant bits of the input are used, otherwise the 194 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 195 * 196 * Here, the result is always nan-boxed, even the canonical nan. 197 */ 198 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 199 { 200 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 201 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 202 203 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 204 } 205 206 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 207 { 208 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 209 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 210 211 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 212 } 213 214 static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2) 215 { 216 assert(!ctx->insn_start_updated); 217 ctx->insn_start_updated = true; 218 tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); 219 tcg_set_insn_start_param(ctx->base.insn_start, 2, excp_uw2); 220 } 221 222 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 223 target_long diff) 224 { 225 target_ulong dest = ctx->base.pc_next + diff; 226 227 assert(ctx->pc_save != -1); 228 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 229 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 230 if (get_xl(ctx) == MXL_RV32) { 231 tcg_gen_ext32s_tl(target, target); 232 } 233 } else { 234 if (get_xl(ctx) == MXL_RV32) { 235 dest = (int32_t)dest; 236 } 237 tcg_gen_movi_tl(target, dest); 238 } 239 } 240 241 static void gen_update_pc(DisasContext *ctx, target_long diff) 242 { 243 gen_pc_plus_diff(cpu_pc, ctx, diff); 244 ctx->pc_save = ctx->base.pc_next + diff; 245 } 246 247 static void generate_exception(DisasContext *ctx, int excp) 248 { 249 gen_update_pc(ctx, 0); 250 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 251 ctx->base.is_jmp = DISAS_NORETURN; 252 } 253 254 static void gen_exception_illegal(DisasContext *ctx) 255 { 256 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 257 offsetof(CPURISCVState, bins)); 258 if (ctx->virt_inst_excp) { 259 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 260 } else { 261 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 262 } 263 } 264 265 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 266 { 267 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 268 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 269 } 270 271 static void lookup_and_goto_ptr(DisasContext *ctx) 272 { 273 #ifndef CONFIG_USER_ONLY 274 if (ctx->itrigger) { 275 gen_helper_itrigger_match(tcg_env); 276 } 277 #endif 278 tcg_gen_lookup_and_goto_ptr(); 279 } 280 281 static void exit_tb(DisasContext *ctx) 282 { 283 #ifndef CONFIG_USER_ONLY 284 if (ctx->itrigger) { 285 gen_helper_itrigger_match(tcg_env); 286 } 287 #endif 288 tcg_gen_exit_tb(NULL, 0); 289 } 290 291 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 292 { 293 target_ulong dest = ctx->base.pc_next + diff; 294 295 /* 296 * Under itrigger, instruction executes one by one like singlestep, 297 * direct block chain benefits will be small. 298 */ 299 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 300 /* 301 * For pcrel, the pc must always be up-to-date on entry to 302 * the linked TB, so that it can use simple additions for all 303 * further adjustments. For !pcrel, the linked TB is compiled 304 * to know its full virtual address, so we can delay the 305 * update to pc to the unlinked path. A long chain of links 306 * can thus avoid many updates to the PC. 307 */ 308 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 309 gen_update_pc(ctx, diff); 310 tcg_gen_goto_tb(n); 311 } else { 312 tcg_gen_goto_tb(n); 313 gen_update_pc(ctx, diff); 314 } 315 tcg_gen_exit_tb(ctx->base.tb, n); 316 } else { 317 gen_update_pc(ctx, diff); 318 lookup_and_goto_ptr(ctx); 319 } 320 } 321 322 /* 323 * Wrappers for getting reg values. 324 * 325 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 326 * constant zero as a source, and an uninitialized sink as destination. 327 * 328 * Further, we may provide an extension for word operations. 329 */ 330 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 331 { 332 TCGv t; 333 334 if (reg_num == 0) { 335 return ctx->zero; 336 } 337 338 switch (get_ol(ctx)) { 339 case MXL_RV32: 340 switch (ext) { 341 case EXT_NONE: 342 break; 343 case EXT_SIGN: 344 t = tcg_temp_new(); 345 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 346 return t; 347 case EXT_ZERO: 348 t = tcg_temp_new(); 349 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 350 return t; 351 default: 352 g_assert_not_reached(); 353 } 354 break; 355 case MXL_RV64: 356 case MXL_RV128: 357 break; 358 default: 359 g_assert_not_reached(); 360 } 361 return cpu_gpr[reg_num]; 362 } 363 364 static TCGv get_gprh(DisasContext *ctx, int reg_num) 365 { 366 assert(get_xl(ctx) == MXL_RV128); 367 if (reg_num == 0) { 368 return ctx->zero; 369 } 370 return cpu_gprh[reg_num]; 371 } 372 373 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 374 { 375 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 376 return tcg_temp_new(); 377 } 378 return cpu_gpr[reg_num]; 379 } 380 381 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 382 { 383 if (reg_num == 0) { 384 return tcg_temp_new(); 385 } 386 return cpu_gprh[reg_num]; 387 } 388 389 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 390 { 391 if (reg_num != 0) { 392 switch (get_ol(ctx)) { 393 case MXL_RV32: 394 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 395 break; 396 case MXL_RV64: 397 case MXL_RV128: 398 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 399 break; 400 default: 401 g_assert_not_reached(); 402 } 403 404 if (get_xl_max(ctx) == MXL_RV128) { 405 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 406 } 407 } 408 } 409 410 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 411 { 412 if (reg_num != 0) { 413 switch (get_ol(ctx)) { 414 case MXL_RV32: 415 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 416 break; 417 case MXL_RV64: 418 case MXL_RV128: 419 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 420 break; 421 default: 422 g_assert_not_reached(); 423 } 424 425 if (get_xl_max(ctx) == MXL_RV128) { 426 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 427 } 428 } 429 } 430 431 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 432 { 433 assert(get_ol(ctx) == MXL_RV128); 434 if (reg_num != 0) { 435 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 436 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 437 } 438 } 439 440 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 441 { 442 if (!ctx->cfg_ptr->ext_zfinx) { 443 return cpu_fpr[reg_num]; 444 } 445 446 if (reg_num == 0) { 447 return tcg_constant_i64(0); 448 } 449 switch (get_xl(ctx)) { 450 case MXL_RV32: 451 #ifdef TARGET_RISCV32 452 { 453 TCGv_i64 t = tcg_temp_new_i64(); 454 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 455 return t; 456 } 457 #else 458 /* fall through */ 459 case MXL_RV64: 460 return cpu_gpr[reg_num]; 461 #endif 462 default: 463 g_assert_not_reached(); 464 } 465 } 466 467 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 468 { 469 if (!ctx->cfg_ptr->ext_zfinx) { 470 return cpu_fpr[reg_num]; 471 } 472 473 if (reg_num == 0) { 474 return tcg_constant_i64(0); 475 } 476 switch (get_xl(ctx)) { 477 case MXL_RV32: 478 { 479 TCGv_i64 t = tcg_temp_new_i64(); 480 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 481 return t; 482 } 483 #ifdef TARGET_RISCV64 484 case MXL_RV64: 485 return cpu_gpr[reg_num]; 486 #endif 487 default: 488 g_assert_not_reached(); 489 } 490 } 491 492 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 493 { 494 if (!ctx->cfg_ptr->ext_zfinx) { 495 return cpu_fpr[reg_num]; 496 } 497 498 if (reg_num == 0) { 499 return tcg_temp_new_i64(); 500 } 501 502 switch (get_xl(ctx)) { 503 case MXL_RV32: 504 return tcg_temp_new_i64(); 505 #ifdef TARGET_RISCV64 506 case MXL_RV64: 507 return cpu_gpr[reg_num]; 508 #endif 509 default: 510 g_assert_not_reached(); 511 } 512 } 513 514 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 515 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 516 { 517 if (!ctx->cfg_ptr->ext_zfinx) { 518 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 519 return; 520 } 521 if (reg_num != 0) { 522 switch (get_xl(ctx)) { 523 case MXL_RV32: 524 #ifdef TARGET_RISCV32 525 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 526 break; 527 #else 528 /* fall through */ 529 case MXL_RV64: 530 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 531 break; 532 #endif 533 default: 534 g_assert_not_reached(); 535 } 536 } 537 } 538 539 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 540 { 541 if (!ctx->cfg_ptr->ext_zfinx) { 542 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 543 return; 544 } 545 546 if (reg_num != 0) { 547 switch (get_xl(ctx)) { 548 case MXL_RV32: 549 #ifdef TARGET_RISCV32 550 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 551 break; 552 #else 553 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 554 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 555 break; 556 case MXL_RV64: 557 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 558 break; 559 #endif 560 default: 561 g_assert_not_reached(); 562 } 563 } 564 } 565 566 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 567 { 568 TCGv succ_pc = dest_gpr(ctx, rd); 569 570 /* check misaligned: */ 571 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 572 if ((imm & 0x3) != 0) { 573 TCGv target_pc = tcg_temp_new(); 574 gen_pc_plus_diff(target_pc, ctx, imm); 575 gen_exception_inst_addr_mis(ctx, target_pc); 576 return; 577 } 578 } 579 580 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 581 gen_set_gpr(ctx, rd, succ_pc); 582 583 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 584 ctx->base.is_jmp = DISAS_NORETURN; 585 } 586 587 /* Compute a canonical address from a register plus offset. */ 588 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 589 { 590 TCGv addr = tcg_temp_new(); 591 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 592 593 tcg_gen_addi_tl(addr, src1, imm); 594 if (ctx->pm_mask_enabled) { 595 tcg_gen_andc_tl(addr, addr, pm_mask); 596 } else if (get_address_xl(ctx) == MXL_RV32) { 597 tcg_gen_ext32u_tl(addr, addr); 598 } 599 if (ctx->pm_base_enabled) { 600 tcg_gen_or_tl(addr, addr, pm_base); 601 } 602 603 return addr; 604 } 605 606 /* Compute a canonical address from a register plus reg offset. */ 607 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 608 { 609 TCGv addr = tcg_temp_new(); 610 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 611 612 tcg_gen_add_tl(addr, src1, offs); 613 if (ctx->pm_mask_enabled) { 614 tcg_gen_andc_tl(addr, addr, pm_mask); 615 } else if (get_xl(ctx) == MXL_RV32) { 616 tcg_gen_ext32u_tl(addr, addr); 617 } 618 if (ctx->pm_base_enabled) { 619 tcg_gen_or_tl(addr, addr, pm_base); 620 } 621 return addr; 622 } 623 624 #ifndef CONFIG_USER_ONLY 625 /* 626 * We will have already diagnosed disabled state, 627 * and need to turn initial/clean into dirty. 628 */ 629 static void mark_fs_dirty(DisasContext *ctx) 630 { 631 TCGv tmp; 632 633 if (!has_ext(ctx, RVF)) { 634 return; 635 } 636 637 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 638 /* Remember the state change for the rest of the TB. */ 639 ctx->mstatus_fs = EXT_STATUS_DIRTY; 640 641 tmp = tcg_temp_new(); 642 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 643 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 644 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 645 646 if (ctx->virt_enabled) { 647 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 648 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 649 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 650 } 651 } 652 } 653 #else 654 static inline void mark_fs_dirty(DisasContext *ctx) { } 655 #endif 656 657 #ifndef CONFIG_USER_ONLY 658 /* 659 * We will have already diagnosed disabled state, 660 * and need to turn initial/clean into dirty. 661 */ 662 static void mark_vs_dirty(DisasContext *ctx) 663 { 664 TCGv tmp; 665 666 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 667 /* Remember the state change for the rest of the TB. */ 668 ctx->mstatus_vs = EXT_STATUS_DIRTY; 669 670 tmp = tcg_temp_new(); 671 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 672 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 673 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 674 675 if (ctx->virt_enabled) { 676 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 677 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 678 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 679 } 680 } 681 } 682 #else 683 static inline void mark_vs_dirty(DisasContext *ctx) { } 684 #endif 685 686 static void finalize_rvv_inst(DisasContext *ctx) 687 { 688 mark_vs_dirty(ctx); 689 ctx->vstart_eq_zero = true; 690 } 691 692 static void gen_set_rm(DisasContext *ctx, int rm) 693 { 694 if (ctx->frm == rm) { 695 return; 696 } 697 ctx->frm = rm; 698 699 if (rm == RISCV_FRM_DYN) { 700 /* The helper will return only if frm valid. */ 701 ctx->frm_valid = true; 702 } 703 704 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 705 decode_save_opc(ctx, 0); 706 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 707 } 708 709 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 710 { 711 if (ctx->frm == rm && ctx->frm_valid) { 712 return; 713 } 714 ctx->frm = rm; 715 ctx->frm_valid = true; 716 717 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 718 decode_save_opc(ctx, 0); 719 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 720 } 721 722 static int ex_plus_1(DisasContext *ctx, int nf) 723 { 724 return nf + 1; 725 } 726 727 #define EX_SH(amount) \ 728 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 729 { \ 730 return imm << amount; \ 731 } 732 EX_SH(1) 733 EX_SH(2) 734 EX_SH(3) 735 EX_SH(4) 736 EX_SH(12) 737 738 #define REQUIRE_EXT(ctx, ext) do { \ 739 if (!has_ext(ctx, ext)) { \ 740 return false; \ 741 } \ 742 } while (0) 743 744 #define REQUIRE_32BIT(ctx) do { \ 745 if (get_xl(ctx) != MXL_RV32) { \ 746 return false; \ 747 } \ 748 } while (0) 749 750 #define REQUIRE_64BIT(ctx) do { \ 751 if (get_xl(ctx) != MXL_RV64) { \ 752 return false; \ 753 } \ 754 } while (0) 755 756 #define REQUIRE_128BIT(ctx) do { \ 757 if (get_xl(ctx) != MXL_RV128) { \ 758 return false; \ 759 } \ 760 } while (0) 761 762 #define REQUIRE_64_OR_128BIT(ctx) do { \ 763 if (get_xl(ctx) == MXL_RV32) { \ 764 return false; \ 765 } \ 766 } while (0) 767 768 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 769 if (!ctx->cfg_ptr->ext_##A && \ 770 !ctx->cfg_ptr->ext_##B) { \ 771 return false; \ 772 } \ 773 } while (0) 774 775 static int ex_rvc_register(DisasContext *ctx, int reg) 776 { 777 return 8 + reg; 778 } 779 780 static int ex_sreg_register(DisasContext *ctx, int reg) 781 { 782 return reg < 2 ? reg + 8 : reg + 16; 783 } 784 785 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 786 { 787 /* For RV128 a shamt of 0 means a shift by 64. */ 788 if (get_ol(ctx) == MXL_RV128) { 789 imm = imm ? imm : 64; 790 } 791 return imm; 792 } 793 794 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 795 { 796 /* 797 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 798 * shifts, the shamt is sign-extended. 799 */ 800 if (get_ol(ctx) == MXL_RV128) { 801 imm = imm | (imm & 32) << 1; 802 imm = imm ? imm : 64; 803 } 804 return imm; 805 } 806 807 /* Include the auto-generated decoder for 32 bit insn */ 808 #include "decode-insn32.c.inc" 809 810 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 811 void (*func)(TCGv, TCGv, target_long)) 812 { 813 TCGv dest = dest_gpr(ctx, a->rd); 814 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 815 816 func(dest, src1, a->imm); 817 818 if (get_xl(ctx) == MXL_RV128) { 819 TCGv src1h = get_gprh(ctx, a->rs1); 820 TCGv desth = dest_gprh(ctx, a->rd); 821 822 func(desth, src1h, -(a->imm < 0)); 823 gen_set_gpr128(ctx, a->rd, dest, desth); 824 } else { 825 gen_set_gpr(ctx, a->rd, dest); 826 } 827 828 return true; 829 } 830 831 static bool gen_logic(DisasContext *ctx, arg_r *a, 832 void (*func)(TCGv, TCGv, TCGv)) 833 { 834 TCGv dest = dest_gpr(ctx, a->rd); 835 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 836 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 837 838 func(dest, src1, src2); 839 840 if (get_xl(ctx) == MXL_RV128) { 841 TCGv src1h = get_gprh(ctx, a->rs1); 842 TCGv src2h = get_gprh(ctx, a->rs2); 843 TCGv desth = dest_gprh(ctx, a->rd); 844 845 func(desth, src1h, src2h); 846 gen_set_gpr128(ctx, a->rd, dest, desth); 847 } else { 848 gen_set_gpr(ctx, a->rd, dest); 849 } 850 851 return true; 852 } 853 854 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 855 void (*func)(TCGv, TCGv, target_long), 856 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 857 { 858 TCGv dest = dest_gpr(ctx, a->rd); 859 TCGv src1 = get_gpr(ctx, a->rs1, ext); 860 861 if (get_ol(ctx) < MXL_RV128) { 862 func(dest, src1, a->imm); 863 gen_set_gpr(ctx, a->rd, dest); 864 } else { 865 if (f128 == NULL) { 866 return false; 867 } 868 869 TCGv src1h = get_gprh(ctx, a->rs1); 870 TCGv desth = dest_gprh(ctx, a->rd); 871 872 f128(dest, desth, src1, src1h, a->imm); 873 gen_set_gpr128(ctx, a->rd, dest, desth); 874 } 875 return true; 876 } 877 878 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 879 void (*func)(TCGv, TCGv, TCGv), 880 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 881 { 882 TCGv dest = dest_gpr(ctx, a->rd); 883 TCGv src1 = get_gpr(ctx, a->rs1, ext); 884 TCGv src2 = tcg_constant_tl(a->imm); 885 886 if (get_ol(ctx) < MXL_RV128) { 887 func(dest, src1, src2); 888 gen_set_gpr(ctx, a->rd, dest); 889 } else { 890 if (f128 == NULL) { 891 return false; 892 } 893 894 TCGv src1h = get_gprh(ctx, a->rs1); 895 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 896 TCGv desth = dest_gprh(ctx, a->rd); 897 898 f128(dest, desth, src1, src1h, src2, src2h); 899 gen_set_gpr128(ctx, a->rd, dest, desth); 900 } 901 return true; 902 } 903 904 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 905 void (*func)(TCGv, TCGv, TCGv), 906 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 907 { 908 TCGv dest = dest_gpr(ctx, a->rd); 909 TCGv src1 = get_gpr(ctx, a->rs1, ext); 910 TCGv src2 = get_gpr(ctx, a->rs2, ext); 911 912 if (get_ol(ctx) < MXL_RV128) { 913 func(dest, src1, src2); 914 gen_set_gpr(ctx, a->rd, dest); 915 } else { 916 if (f128 == NULL) { 917 return false; 918 } 919 920 TCGv src1h = get_gprh(ctx, a->rs1); 921 TCGv src2h = get_gprh(ctx, a->rs2); 922 TCGv desth = dest_gprh(ctx, a->rd); 923 924 f128(dest, desth, src1, src1h, src2, src2h); 925 gen_set_gpr128(ctx, a->rd, dest, desth); 926 } 927 return true; 928 } 929 930 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 931 void (*f_tl)(TCGv, TCGv, TCGv), 932 void (*f_32)(TCGv, TCGv, TCGv), 933 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 934 { 935 int olen = get_olen(ctx); 936 937 if (olen != TARGET_LONG_BITS) { 938 if (olen == 32) { 939 f_tl = f_32; 940 } else if (olen != 128) { 941 g_assert_not_reached(); 942 } 943 } 944 return gen_arith(ctx, a, ext, f_tl, f_128); 945 } 946 947 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 948 void (*func)(TCGv, TCGv, target_long), 949 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 950 { 951 TCGv dest, src1; 952 int max_len = get_olen(ctx); 953 954 if (a->shamt >= max_len) { 955 return false; 956 } 957 958 dest = dest_gpr(ctx, a->rd); 959 src1 = get_gpr(ctx, a->rs1, ext); 960 961 if (max_len < 128) { 962 func(dest, src1, a->shamt); 963 gen_set_gpr(ctx, a->rd, dest); 964 } else { 965 TCGv src1h = get_gprh(ctx, a->rs1); 966 TCGv desth = dest_gprh(ctx, a->rd); 967 968 if (f128 == NULL) { 969 return false; 970 } 971 f128(dest, desth, src1, src1h, a->shamt); 972 gen_set_gpr128(ctx, a->rd, dest, desth); 973 } 974 return true; 975 } 976 977 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 978 DisasExtend ext, 979 void (*f_tl)(TCGv, TCGv, target_long), 980 void (*f_32)(TCGv, TCGv, target_long), 981 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 982 target_long)) 983 { 984 int olen = get_olen(ctx); 985 if (olen != TARGET_LONG_BITS) { 986 if (olen == 32) { 987 f_tl = f_32; 988 } else if (olen != 128) { 989 g_assert_not_reached(); 990 } 991 } 992 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 993 } 994 995 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 996 void (*func)(TCGv, TCGv, TCGv)) 997 { 998 TCGv dest, src1, src2; 999 int max_len = get_olen(ctx); 1000 1001 if (a->shamt >= max_len) { 1002 return false; 1003 } 1004 1005 dest = dest_gpr(ctx, a->rd); 1006 src1 = get_gpr(ctx, a->rs1, ext); 1007 src2 = tcg_constant_tl(a->shamt); 1008 1009 func(dest, src1, src2); 1010 1011 gen_set_gpr(ctx, a->rd, dest); 1012 return true; 1013 } 1014 1015 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1016 void (*func)(TCGv, TCGv, TCGv), 1017 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1018 { 1019 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1020 TCGv ext2 = tcg_temp_new(); 1021 int max_len = get_olen(ctx); 1022 1023 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1024 1025 TCGv dest = dest_gpr(ctx, a->rd); 1026 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1027 1028 if (max_len < 128) { 1029 func(dest, src1, ext2); 1030 gen_set_gpr(ctx, a->rd, dest); 1031 } else { 1032 TCGv src1h = get_gprh(ctx, a->rs1); 1033 TCGv desth = dest_gprh(ctx, a->rd); 1034 1035 if (f128 == NULL) { 1036 return false; 1037 } 1038 f128(dest, desth, src1, src1h, ext2); 1039 gen_set_gpr128(ctx, a->rd, dest, desth); 1040 } 1041 return true; 1042 } 1043 1044 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1045 void (*f_tl)(TCGv, TCGv, TCGv), 1046 void (*f_32)(TCGv, TCGv, TCGv), 1047 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1048 { 1049 int olen = get_olen(ctx); 1050 if (olen != TARGET_LONG_BITS) { 1051 if (olen == 32) { 1052 f_tl = f_32; 1053 } else if (olen != 128) { 1054 g_assert_not_reached(); 1055 } 1056 } 1057 return gen_shift(ctx, a, ext, f_tl, f_128); 1058 } 1059 1060 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1061 void (*func)(TCGv, TCGv)) 1062 { 1063 TCGv dest = dest_gpr(ctx, a->rd); 1064 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1065 1066 func(dest, src1); 1067 1068 gen_set_gpr(ctx, a->rd, dest); 1069 return true; 1070 } 1071 1072 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1073 void (*f_tl)(TCGv, TCGv), 1074 void (*f_32)(TCGv, TCGv)) 1075 { 1076 int olen = get_olen(ctx); 1077 1078 if (olen != TARGET_LONG_BITS) { 1079 if (olen == 32) { 1080 f_tl = f_32; 1081 } else { 1082 g_assert_not_reached(); 1083 } 1084 } 1085 return gen_unary(ctx, a, ext, f_tl); 1086 } 1087 1088 static bool gen_amo(DisasContext *ctx, arg_atomic *a, 1089 void(*func)(TCGv, TCGv, TCGv, TCGArg, MemOp), 1090 MemOp mop) 1091 { 1092 TCGv dest = dest_gpr(ctx, a->rd); 1093 TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1094 MemOp size = mop & MO_SIZE; 1095 1096 if (ctx->cfg_ptr->ext_zama16b && size >= MO_32) { 1097 mop |= MO_ATOM_WITHIN16; 1098 } else { 1099 mop |= MO_ALIGN; 1100 } 1101 1102 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1103 src1 = get_address(ctx, a->rs1, 0); 1104 func(dest, src1, src2, ctx->mem_idx, mop); 1105 1106 gen_set_gpr(ctx, a->rd, dest); 1107 return true; 1108 } 1109 1110 static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop) 1111 { 1112 TCGv dest = get_gpr(ctx, a->rd, EXT_NONE); 1113 TCGv src1 = get_address(ctx, a->rs1, 0); 1114 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1115 1116 decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO); 1117 tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop); 1118 1119 gen_set_gpr(ctx, a->rd, dest); 1120 return true; 1121 } 1122 1123 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1124 { 1125 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1126 CPUState *cpu = ctx->cs; 1127 CPURISCVState *env = cpu_env(cpu); 1128 1129 return translator_ldl(env, &ctx->base, pc); 1130 } 1131 1132 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE) 1133 1134 /* Include insn module translation function */ 1135 #include "insn_trans/trans_rvi.c.inc" 1136 #include "insn_trans/trans_rvm.c.inc" 1137 #include "insn_trans/trans_rva.c.inc" 1138 #include "insn_trans/trans_rvf.c.inc" 1139 #include "insn_trans/trans_rvd.c.inc" 1140 #include "insn_trans/trans_rvh.c.inc" 1141 #include "insn_trans/trans_rvv.c.inc" 1142 #include "insn_trans/trans_rvb.c.inc" 1143 #include "insn_trans/trans_rvzicond.c.inc" 1144 #include "insn_trans/trans_rvzacas.c.inc" 1145 #include "insn_trans/trans_rvzabha.c.inc" 1146 #include "insn_trans/trans_rvzawrs.c.inc" 1147 #include "insn_trans/trans_rvzicbo.c.inc" 1148 #include "insn_trans/trans_rvzimop.c.inc" 1149 #include "insn_trans/trans_rvzfa.c.inc" 1150 #include "insn_trans/trans_rvzfh.c.inc" 1151 #include "insn_trans/trans_rvk.c.inc" 1152 #include "insn_trans/trans_rvvk.c.inc" 1153 #include "insn_trans/trans_privileged.c.inc" 1154 #include "insn_trans/trans_svinval.c.inc" 1155 #include "insn_trans/trans_rvbf16.c.inc" 1156 #include "decode-xthead.c.inc" 1157 #include "insn_trans/trans_xthead.c.inc" 1158 #include "insn_trans/trans_xventanacondops.c.inc" 1159 1160 /* Include the auto-generated decoder for 16 bit insn */ 1161 #include "decode-insn16.c.inc" 1162 #include "insn_trans/trans_rvzce.c.inc" 1163 #include "insn_trans/trans_rvzcmop.c.inc" 1164 #include "insn_trans/trans_rvzicfiss.c.inc" 1165 1166 /* Include decoders for factored-out extensions */ 1167 #include "decode-XVentanaCondOps.c.inc" 1168 1169 /* The specification allows for longer insns, but not supported by qemu. */ 1170 #define MAX_INSN_LEN 4 1171 1172 static inline int insn_len(uint16_t first_word) 1173 { 1174 return (first_word & 3) == 3 ? 4 : 2; 1175 } 1176 1177 const RISCVDecoder decoder_table[] = { 1178 { always_true_p, decode_insn32 }, 1179 { has_xthead_p, decode_xthead}, 1180 { has_XVentanaCondOps_p, decode_XVentanaCodeOps}, 1181 }; 1182 1183 const size_t decoder_table_size = ARRAY_SIZE(decoder_table); 1184 1185 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1186 { 1187 ctx->virt_inst_excp = false; 1188 ctx->cur_insn_len = insn_len(opcode); 1189 /* Check for compressed insn */ 1190 if (ctx->cur_insn_len == 2) { 1191 ctx->opcode = opcode; 1192 /* 1193 * The Zca extension is added as way to refer to instructions in the C 1194 * extension that do not include the floating-point loads and stores 1195 */ 1196 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1197 decode_insn16(ctx, opcode)) { 1198 return; 1199 } 1200 } else { 1201 uint32_t opcode32 = opcode; 1202 opcode32 = deposit32(opcode32, 16, 16, 1203 translator_lduw(env, &ctx->base, 1204 ctx->base.pc_next + 2)); 1205 ctx->opcode = opcode32; 1206 1207 for (guint i = 0; i < ctx->decoders->len; ++i) { 1208 riscv_cpu_decode_fn func = g_ptr_array_index(ctx->decoders, i); 1209 if (func(ctx, opcode32)) { 1210 return; 1211 } 1212 } 1213 } 1214 1215 gen_exception_illegal(ctx); 1216 } 1217 1218 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1219 { 1220 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1221 CPURISCVState *env = cpu_env(cs); 1222 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1223 RISCVCPU *cpu = RISCV_CPU(cs); 1224 uint32_t tb_flags = ctx->base.tb->flags; 1225 1226 ctx->pc_save = ctx->base.pc_first; 1227 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1228 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1229 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1230 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1231 ctx->priv_ver = env->priv_ver; 1232 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1233 ctx->misa_ext = env->misa_ext; 1234 ctx->frm = -1; /* unknown rounding mode */ 1235 ctx->cfg_ptr = &(cpu->cfg); 1236 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1237 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1238 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1239 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1240 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1241 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1242 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1243 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1244 ctx->misa_mxl_max = mcc->misa_mxl_max; 1245 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1246 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1247 ctx->cs = cs; 1248 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1249 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1250 ctx->ztso = cpu->cfg.ext_ztso; 1251 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1252 ctx->bcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, BCFI_ENABLED); 1253 ctx->fcfi_lp_expected = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_LP_EXPECTED); 1254 ctx->fcfi_enabled = FIELD_EX32(tb_flags, TB_FLAGS, FCFI_ENABLED); 1255 ctx->zero = tcg_constant_tl(0); 1256 ctx->virt_inst_excp = false; 1257 ctx->decoders = cpu->decoders; 1258 } 1259 1260 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1261 { 1262 } 1263 1264 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1265 { 1266 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1267 target_ulong pc_next = ctx->base.pc_next; 1268 1269 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1270 pc_next &= ~TARGET_PAGE_MASK; 1271 } 1272 1273 tcg_gen_insn_start(pc_next, 0, 0); 1274 ctx->insn_start_updated = false; 1275 } 1276 1277 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1278 { 1279 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1280 CPURISCVState *env = cpu_env(cpu); 1281 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1282 1283 ctx->ol = ctx->xl; 1284 decode_opc(env, ctx, opcode16); 1285 ctx->base.pc_next += ctx->cur_insn_len; 1286 1287 /* 1288 * If 'fcfi_lp_expected' is still true after processing the instruction, 1289 * then we did not see an 'lpad' instruction, and must raise an exception. 1290 * Insert code to raise the exception at the start of the insn; any other 1291 * code the insn may have emitted will be deleted as dead code following 1292 * the noreturn exception 1293 */ 1294 if (ctx->fcfi_lp_expected) { 1295 /* Emit after insn_start, i.e. before the op following insn_start. */ 1296 tcg_ctx->emit_before_op = QTAILQ_NEXT(ctx->base.insn_start, link); 1297 tcg_gen_st_tl(tcg_constant_tl(RISCV_EXCP_SW_CHECK_FCFI_TVAL), 1298 tcg_env, offsetof(CPURISCVState, sw_check_code)); 1299 gen_helper_raise_exception(tcg_env, 1300 tcg_constant_i32(RISCV_EXCP_SW_CHECK)); 1301 tcg_ctx->emit_before_op = NULL; 1302 ctx->base.is_jmp = DISAS_NORETURN; 1303 } 1304 1305 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1306 if (ctx->base.is_jmp == DISAS_NEXT) { 1307 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1308 ctx->base.is_jmp = DISAS_TOO_MANY; 1309 } else { 1310 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1311 1312 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1313 uint16_t next_insn = 1314 translator_lduw(env, &ctx->base, ctx->base.pc_next); 1315 int len = insn_len(next_insn); 1316 1317 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1318 ctx->base.is_jmp = DISAS_TOO_MANY; 1319 } 1320 } 1321 } 1322 } 1323 } 1324 1325 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1326 { 1327 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1328 1329 switch (ctx->base.is_jmp) { 1330 case DISAS_TOO_MANY: 1331 gen_goto_tb(ctx, 0, 0); 1332 break; 1333 case DISAS_NORETURN: 1334 break; 1335 default: 1336 g_assert_not_reached(); 1337 } 1338 } 1339 1340 static const TranslatorOps riscv_tr_ops = { 1341 .init_disas_context = riscv_tr_init_disas_context, 1342 .tb_start = riscv_tr_tb_start, 1343 .insn_start = riscv_tr_insn_start, 1344 .translate_insn = riscv_tr_translate_insn, 1345 .tb_stop = riscv_tr_tb_stop, 1346 }; 1347 1348 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1349 vaddr pc, void *host_pc) 1350 { 1351 DisasContext ctx; 1352 1353 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1354 } 1355 1356 void riscv_translate_init(void) 1357 { 1358 int i; 1359 1360 /* 1361 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1362 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1363 * unless you specifically block reads/writes to reg 0. 1364 */ 1365 cpu_gpr[0] = NULL; 1366 cpu_gprh[0] = NULL; 1367 1368 for (i = 1; i < 32; i++) { 1369 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1370 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1371 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1372 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1373 } 1374 1375 for (i = 0; i < 32; i++) { 1376 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1377 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1378 } 1379 1380 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1381 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1382 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1383 "vstart"); 1384 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1385 "load_res"); 1386 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1387 "load_val"); 1388 /* Assign PM CSRs to tcg globals */ 1389 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1390 "pmmask"); 1391 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1392 "pmbase"); 1393 } 1394