1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* PointerMasking extension */ 105 bool pm_mask_enabled; 106 bool pm_base_enabled; 107 } DisasContext; 108 109 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 110 { 111 return ctx->misa_ext & ext; 112 } 113 114 #ifdef TARGET_RISCV32 115 #define get_xl(ctx) MXL_RV32 116 #elif defined(CONFIG_USER_ONLY) 117 #define get_xl(ctx) MXL_RV64 118 #else 119 #define get_xl(ctx) ((ctx)->xl) 120 #endif 121 122 /* The word size for this machine mode. */ 123 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 124 { 125 return 16 << get_xl(ctx); 126 } 127 128 /* The operation length, as opposed to the xlen. */ 129 #ifdef TARGET_RISCV32 130 #define get_ol(ctx) MXL_RV32 131 #else 132 #define get_ol(ctx) ((ctx)->ol) 133 #endif 134 135 static inline int get_olen(DisasContext *ctx) 136 { 137 return 16 << get_ol(ctx); 138 } 139 140 /* The maximum register length */ 141 #ifdef TARGET_RISCV32 142 #define get_xl_max(ctx) MXL_RV32 143 #else 144 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 145 #endif 146 147 /* 148 * RISC-V requires NaN-boxing of narrower width floating point values. 149 * This applies when a 32-bit value is assigned to a 64-bit FP register. 150 * For consistency and simplicity, we nanbox results even when the RVD 151 * extension is not present. 152 */ 153 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 154 { 155 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 156 } 157 158 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 161 } 162 163 /* 164 * A narrow n-bit operation, where n < FLEN, checks that input operands 165 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 166 * If so, the least-significant bits of the input are used, otherwise the 167 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 168 * 169 * Here, the result is always nan-boxed, even the canonical nan. 170 */ 171 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 172 { 173 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 174 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 175 176 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 177 tcg_temp_free_i64(t_max); 178 tcg_temp_free_i64(t_nan); 179 } 180 181 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 182 { 183 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 184 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 185 186 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 187 } 188 189 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 190 { 191 if (get_xl(ctx) == MXL_RV32) { 192 dest = (int32_t)dest; 193 } 194 tcg_gen_movi_tl(cpu_pc, dest); 195 } 196 197 static void gen_set_pc(DisasContext *ctx, TCGv dest) 198 { 199 if (get_xl(ctx) == MXL_RV32) { 200 tcg_gen_ext32s_tl(cpu_pc, dest); 201 } else { 202 tcg_gen_mov_tl(cpu_pc, dest); 203 } 204 } 205 206 static void generate_exception(DisasContext *ctx, int excp) 207 { 208 gen_set_pc_imm(ctx, ctx->base.pc_next); 209 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 210 ctx->base.is_jmp = DISAS_NORETURN; 211 } 212 213 static void generate_exception_mtval(DisasContext *ctx, int excp) 214 { 215 gen_set_pc_imm(ctx, ctx->base.pc_next); 216 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 217 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 218 ctx->base.is_jmp = DISAS_NORETURN; 219 } 220 221 static void gen_exception_illegal(DisasContext *ctx) 222 { 223 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 224 offsetof(CPURISCVState, bins)); 225 226 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 227 } 228 229 static void gen_exception_inst_addr_mis(DisasContext *ctx) 230 { 231 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 232 } 233 234 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 235 { 236 if (translator_use_goto_tb(&ctx->base, dest)) { 237 tcg_gen_goto_tb(n); 238 gen_set_pc_imm(ctx, dest); 239 tcg_gen_exit_tb(ctx->base.tb, n); 240 } else { 241 gen_set_pc_imm(ctx, dest); 242 tcg_gen_lookup_and_goto_ptr(); 243 } 244 } 245 246 /* 247 * Wrappers for getting reg values. 248 * 249 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 250 * constant zero as a source, and an uninitialized sink as destination. 251 * 252 * Further, we may provide an extension for word operations. 253 */ 254 static TCGv temp_new(DisasContext *ctx) 255 { 256 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 257 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 258 } 259 260 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 261 { 262 TCGv t; 263 264 if (reg_num == 0) { 265 return ctx->zero; 266 } 267 268 switch (get_ol(ctx)) { 269 case MXL_RV32: 270 switch (ext) { 271 case EXT_NONE: 272 break; 273 case EXT_SIGN: 274 t = temp_new(ctx); 275 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 276 return t; 277 case EXT_ZERO: 278 t = temp_new(ctx); 279 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 280 return t; 281 default: 282 g_assert_not_reached(); 283 } 284 break; 285 case MXL_RV64: 286 case MXL_RV128: 287 break; 288 default: 289 g_assert_not_reached(); 290 } 291 return cpu_gpr[reg_num]; 292 } 293 294 static TCGv get_gprh(DisasContext *ctx, int reg_num) 295 { 296 assert(get_xl(ctx) == MXL_RV128); 297 if (reg_num == 0) { 298 return ctx->zero; 299 } 300 return cpu_gprh[reg_num]; 301 } 302 303 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 304 { 305 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 306 return temp_new(ctx); 307 } 308 return cpu_gpr[reg_num]; 309 } 310 311 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 312 { 313 if (reg_num == 0) { 314 return temp_new(ctx); 315 } 316 return cpu_gprh[reg_num]; 317 } 318 319 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 320 { 321 if (reg_num != 0) { 322 switch (get_ol(ctx)) { 323 case MXL_RV32: 324 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 325 break; 326 case MXL_RV64: 327 case MXL_RV128: 328 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 329 break; 330 default: 331 g_assert_not_reached(); 332 } 333 334 if (get_xl_max(ctx) == MXL_RV128) { 335 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 336 } 337 } 338 } 339 340 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 341 { 342 if (reg_num != 0) { 343 switch (get_ol(ctx)) { 344 case MXL_RV32: 345 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 346 break; 347 case MXL_RV64: 348 case MXL_RV128: 349 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 350 break; 351 default: 352 g_assert_not_reached(); 353 } 354 355 if (get_xl_max(ctx) == MXL_RV128) { 356 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 357 } 358 } 359 } 360 361 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 362 { 363 assert(get_ol(ctx) == MXL_RV128); 364 if (reg_num != 0) { 365 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 366 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 367 } 368 } 369 370 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 371 { 372 target_ulong next_pc; 373 374 /* check misaligned: */ 375 next_pc = ctx->base.pc_next + imm; 376 if (!has_ext(ctx, RVC)) { 377 if ((next_pc & 0x3) != 0) { 378 gen_exception_inst_addr_mis(ctx); 379 return; 380 } 381 } 382 383 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 384 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 385 ctx->base.is_jmp = DISAS_NORETURN; 386 } 387 388 /* Compute a canonical address from a register plus offset. */ 389 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 390 { 391 TCGv addr = temp_new(ctx); 392 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 393 394 tcg_gen_addi_tl(addr, src1, imm); 395 if (ctx->pm_mask_enabled) { 396 tcg_gen_and_tl(addr, addr, pm_mask); 397 } else if (get_xl(ctx) == MXL_RV32) { 398 tcg_gen_ext32u_tl(addr, addr); 399 } 400 if (ctx->pm_base_enabled) { 401 tcg_gen_or_tl(addr, addr, pm_base); 402 } 403 return addr; 404 } 405 406 #ifndef CONFIG_USER_ONLY 407 /* The states of mstatus_fs are: 408 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 409 * We will have already diagnosed disabled state, 410 * and need to turn initial/clean into dirty. 411 */ 412 static void mark_fs_dirty(DisasContext *ctx) 413 { 414 TCGv tmp; 415 416 if (ctx->mstatus_fs != MSTATUS_FS) { 417 /* Remember the state change for the rest of the TB. */ 418 ctx->mstatus_fs = MSTATUS_FS; 419 420 tmp = tcg_temp_new(); 421 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 422 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 423 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 424 tcg_temp_free(tmp); 425 } 426 427 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 428 /* Remember the stage change for the rest of the TB. */ 429 ctx->mstatus_hs_fs = MSTATUS_FS; 430 431 tmp = tcg_temp_new(); 432 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 433 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 434 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 435 tcg_temp_free(tmp); 436 } 437 } 438 #else 439 static inline void mark_fs_dirty(DisasContext *ctx) { } 440 #endif 441 442 #ifndef CONFIG_USER_ONLY 443 /* The states of mstatus_vs are: 444 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 445 * We will have already diagnosed disabled state, 446 * and need to turn initial/clean into dirty. 447 */ 448 static void mark_vs_dirty(DisasContext *ctx) 449 { 450 TCGv tmp; 451 452 if (ctx->mstatus_vs != MSTATUS_VS) { 453 /* Remember the state change for the rest of the TB. */ 454 ctx->mstatus_vs = MSTATUS_VS; 455 456 tmp = tcg_temp_new(); 457 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 458 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 459 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 460 tcg_temp_free(tmp); 461 } 462 463 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 464 /* Remember the stage change for the rest of the TB. */ 465 ctx->mstatus_hs_vs = MSTATUS_VS; 466 467 tmp = tcg_temp_new(); 468 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 469 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 470 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 471 tcg_temp_free(tmp); 472 } 473 } 474 #else 475 static inline void mark_vs_dirty(DisasContext *ctx) { } 476 #endif 477 478 static void gen_set_rm(DisasContext *ctx, int rm) 479 { 480 if (ctx->frm == rm) { 481 return; 482 } 483 ctx->frm = rm; 484 485 if (rm == RISCV_FRM_ROD) { 486 gen_helper_set_rod_rounding_mode(cpu_env); 487 return; 488 } 489 490 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 491 } 492 493 static int ex_plus_1(DisasContext *ctx, int nf) 494 { 495 return nf + 1; 496 } 497 498 #define EX_SH(amount) \ 499 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 500 { \ 501 return imm << amount; \ 502 } 503 EX_SH(1) 504 EX_SH(2) 505 EX_SH(3) 506 EX_SH(4) 507 EX_SH(12) 508 509 #define REQUIRE_EXT(ctx, ext) do { \ 510 if (!has_ext(ctx, ext)) { \ 511 return false; \ 512 } \ 513 } while (0) 514 515 #define REQUIRE_32BIT(ctx) do { \ 516 if (get_xl(ctx) != MXL_RV32) { \ 517 return false; \ 518 } \ 519 } while (0) 520 521 #define REQUIRE_64BIT(ctx) do { \ 522 if (get_xl(ctx) != MXL_RV64) { \ 523 return false; \ 524 } \ 525 } while (0) 526 527 #define REQUIRE_128BIT(ctx) do { \ 528 if (get_xl(ctx) != MXL_RV128) { \ 529 return false; \ 530 } \ 531 } while (0) 532 533 #define REQUIRE_64_OR_128BIT(ctx) do { \ 534 if (get_xl(ctx) == MXL_RV32) { \ 535 return false; \ 536 } \ 537 } while (0) 538 539 static int ex_rvc_register(DisasContext *ctx, int reg) 540 { 541 return 8 + reg; 542 } 543 544 static int ex_rvc_shifti(DisasContext *ctx, int imm) 545 { 546 /* For RV128 a shamt of 0 means a shift by 64. */ 547 return imm ? imm : 64; 548 } 549 550 /* Include the auto-generated decoder for 32 bit insn */ 551 #include "decode-insn32.c.inc" 552 553 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 554 void (*func)(TCGv, TCGv, target_long)) 555 { 556 TCGv dest = dest_gpr(ctx, a->rd); 557 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 558 559 func(dest, src1, a->imm); 560 561 if (get_xl(ctx) == MXL_RV128) { 562 TCGv src1h = get_gprh(ctx, a->rs1); 563 TCGv desth = dest_gprh(ctx, a->rd); 564 565 func(desth, src1h, -(a->imm < 0)); 566 gen_set_gpr128(ctx, a->rd, dest, desth); 567 } else { 568 gen_set_gpr(ctx, a->rd, dest); 569 } 570 571 return true; 572 } 573 574 static bool gen_logic(DisasContext *ctx, arg_r *a, 575 void (*func)(TCGv, TCGv, TCGv)) 576 { 577 TCGv dest = dest_gpr(ctx, a->rd); 578 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 579 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 580 581 func(dest, src1, src2); 582 583 if (get_xl(ctx) == MXL_RV128) { 584 TCGv src1h = get_gprh(ctx, a->rs1); 585 TCGv src2h = get_gprh(ctx, a->rs2); 586 TCGv desth = dest_gprh(ctx, a->rd); 587 588 func(desth, src1h, src2h); 589 gen_set_gpr128(ctx, a->rd, dest, desth); 590 } else { 591 gen_set_gpr(ctx, a->rd, dest); 592 } 593 594 return true; 595 } 596 597 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 598 void (*func)(TCGv, TCGv, target_long), 599 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 600 { 601 TCGv dest = dest_gpr(ctx, a->rd); 602 TCGv src1 = get_gpr(ctx, a->rs1, ext); 603 604 if (get_ol(ctx) < MXL_RV128) { 605 func(dest, src1, a->imm); 606 gen_set_gpr(ctx, a->rd, dest); 607 } else { 608 if (f128 == NULL) { 609 return false; 610 } 611 612 TCGv src1h = get_gprh(ctx, a->rs1); 613 TCGv desth = dest_gprh(ctx, a->rd); 614 615 f128(dest, desth, src1, src1h, a->imm); 616 gen_set_gpr128(ctx, a->rd, dest, desth); 617 } 618 return true; 619 } 620 621 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 622 void (*func)(TCGv, TCGv, TCGv), 623 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 624 { 625 TCGv dest = dest_gpr(ctx, a->rd); 626 TCGv src1 = get_gpr(ctx, a->rs1, ext); 627 TCGv src2 = tcg_constant_tl(a->imm); 628 629 if (get_ol(ctx) < MXL_RV128) { 630 func(dest, src1, src2); 631 gen_set_gpr(ctx, a->rd, dest); 632 } else { 633 if (f128 == NULL) { 634 return false; 635 } 636 637 TCGv src1h = get_gprh(ctx, a->rs1); 638 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 639 TCGv desth = dest_gprh(ctx, a->rd); 640 641 f128(dest, desth, src1, src1h, src2, src2h); 642 gen_set_gpr128(ctx, a->rd, dest, desth); 643 } 644 return true; 645 } 646 647 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 648 void (*func)(TCGv, TCGv, TCGv), 649 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 650 { 651 TCGv dest = dest_gpr(ctx, a->rd); 652 TCGv src1 = get_gpr(ctx, a->rs1, ext); 653 TCGv src2 = get_gpr(ctx, a->rs2, ext); 654 655 if (get_ol(ctx) < MXL_RV128) { 656 func(dest, src1, src2); 657 gen_set_gpr(ctx, a->rd, dest); 658 } else { 659 if (f128 == NULL) { 660 return false; 661 } 662 663 TCGv src1h = get_gprh(ctx, a->rs1); 664 TCGv src2h = get_gprh(ctx, a->rs2); 665 TCGv desth = dest_gprh(ctx, a->rd); 666 667 f128(dest, desth, src1, src1h, src2, src2h); 668 gen_set_gpr128(ctx, a->rd, dest, desth); 669 } 670 return true; 671 } 672 673 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 674 void (*f_tl)(TCGv, TCGv, TCGv), 675 void (*f_32)(TCGv, TCGv, TCGv), 676 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 677 { 678 int olen = get_olen(ctx); 679 680 if (olen != TARGET_LONG_BITS) { 681 if (olen == 32) { 682 f_tl = f_32; 683 } else if (olen != 128) { 684 g_assert_not_reached(); 685 } 686 } 687 return gen_arith(ctx, a, ext, f_tl, f_128); 688 } 689 690 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 691 void (*func)(TCGv, TCGv, target_long), 692 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 693 { 694 TCGv dest, src1; 695 int max_len = get_olen(ctx); 696 697 if (a->shamt >= max_len) { 698 return false; 699 } 700 701 dest = dest_gpr(ctx, a->rd); 702 src1 = get_gpr(ctx, a->rs1, ext); 703 704 if (max_len < 128) { 705 func(dest, src1, a->shamt); 706 gen_set_gpr(ctx, a->rd, dest); 707 } else { 708 TCGv src1h = get_gprh(ctx, a->rs1); 709 TCGv desth = dest_gprh(ctx, a->rd); 710 711 if (f128 == NULL) { 712 return false; 713 } 714 f128(dest, desth, src1, src1h, a->shamt); 715 gen_set_gpr128(ctx, a->rd, dest, desth); 716 } 717 return true; 718 } 719 720 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 721 DisasExtend ext, 722 void (*f_tl)(TCGv, TCGv, target_long), 723 void (*f_32)(TCGv, TCGv, target_long), 724 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 725 target_long)) 726 { 727 int olen = get_olen(ctx); 728 if (olen != TARGET_LONG_BITS) { 729 if (olen == 32) { 730 f_tl = f_32; 731 } else if (olen != 128) { 732 g_assert_not_reached(); 733 } 734 } 735 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 736 } 737 738 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 739 void (*func)(TCGv, TCGv, TCGv)) 740 { 741 TCGv dest, src1, src2; 742 int max_len = get_olen(ctx); 743 744 if (a->shamt >= max_len) { 745 return false; 746 } 747 748 dest = dest_gpr(ctx, a->rd); 749 src1 = get_gpr(ctx, a->rs1, ext); 750 src2 = tcg_constant_tl(a->shamt); 751 752 func(dest, src1, src2); 753 754 gen_set_gpr(ctx, a->rd, dest); 755 return true; 756 } 757 758 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 759 void (*func)(TCGv, TCGv, TCGv), 760 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 761 { 762 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 763 TCGv ext2 = tcg_temp_new(); 764 int max_len = get_olen(ctx); 765 766 tcg_gen_andi_tl(ext2, src2, max_len - 1); 767 768 TCGv dest = dest_gpr(ctx, a->rd); 769 TCGv src1 = get_gpr(ctx, a->rs1, ext); 770 771 if (max_len < 128) { 772 func(dest, src1, ext2); 773 gen_set_gpr(ctx, a->rd, dest); 774 } else { 775 TCGv src1h = get_gprh(ctx, a->rs1); 776 TCGv desth = dest_gprh(ctx, a->rd); 777 778 if (f128 == NULL) { 779 return false; 780 } 781 f128(dest, desth, src1, src1h, ext2); 782 gen_set_gpr128(ctx, a->rd, dest, desth); 783 } 784 tcg_temp_free(ext2); 785 return true; 786 } 787 788 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 789 void (*f_tl)(TCGv, TCGv, TCGv), 790 void (*f_32)(TCGv, TCGv, TCGv), 791 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 792 { 793 int olen = get_olen(ctx); 794 if (olen != TARGET_LONG_BITS) { 795 if (olen == 32) { 796 f_tl = f_32; 797 } else if (olen != 128) { 798 g_assert_not_reached(); 799 } 800 } 801 return gen_shift(ctx, a, ext, f_tl, f_128); 802 } 803 804 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 805 void (*func)(TCGv, TCGv)) 806 { 807 TCGv dest = dest_gpr(ctx, a->rd); 808 TCGv src1 = get_gpr(ctx, a->rs1, ext); 809 810 func(dest, src1); 811 812 gen_set_gpr(ctx, a->rd, dest); 813 return true; 814 } 815 816 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 817 void (*f_tl)(TCGv, TCGv), 818 void (*f_32)(TCGv, TCGv)) 819 { 820 int olen = get_olen(ctx); 821 822 if (olen != TARGET_LONG_BITS) { 823 if (olen == 32) { 824 f_tl = f_32; 825 } else { 826 g_assert_not_reached(); 827 } 828 } 829 return gen_unary(ctx, a, ext, f_tl); 830 } 831 832 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 833 { 834 DisasContext *ctx = container_of(dcbase, DisasContext, base); 835 CPUState *cpu = ctx->cs; 836 CPURISCVState *env = cpu->env_ptr; 837 838 return cpu_ldl_code(env, pc); 839 } 840 841 /* Include insn module translation function */ 842 #include "insn_trans/trans_rvi.c.inc" 843 #include "insn_trans/trans_rvm.c.inc" 844 #include "insn_trans/trans_rva.c.inc" 845 #include "insn_trans/trans_rvf.c.inc" 846 #include "insn_trans/trans_rvd.c.inc" 847 #include "insn_trans/trans_rvh.c.inc" 848 #include "insn_trans/trans_rvv.c.inc" 849 #include "insn_trans/trans_rvb.c.inc" 850 #include "insn_trans/trans_rvzfh.c.inc" 851 #include "insn_trans/trans_privileged.c.inc" 852 853 /* Include the auto-generated decoder for 16 bit insn */ 854 #include "decode-insn16.c.inc" 855 856 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 857 { 858 /* check for compressed insn */ 859 if (extract16(opcode, 0, 2) != 3) { 860 if (!has_ext(ctx, RVC)) { 861 gen_exception_illegal(ctx); 862 } else { 863 ctx->opcode = opcode; 864 ctx->pc_succ_insn = ctx->base.pc_next + 2; 865 if (!decode_insn16(ctx, opcode)) { 866 gen_exception_illegal(ctx); 867 } 868 } 869 } else { 870 uint32_t opcode32 = opcode; 871 opcode32 = deposit32(opcode32, 16, 16, 872 translator_lduw(env, &ctx->base, 873 ctx->base.pc_next + 2)); 874 ctx->opcode = opcode32; 875 ctx->pc_succ_insn = ctx->base.pc_next + 4; 876 if (!decode_insn32(ctx, opcode32)) { 877 gen_exception_illegal(ctx); 878 } 879 } 880 } 881 882 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 883 { 884 DisasContext *ctx = container_of(dcbase, DisasContext, base); 885 CPURISCVState *env = cs->env_ptr; 886 RISCVCPU *cpu = RISCV_CPU(cs); 887 uint32_t tb_flags = ctx->base.tb->flags; 888 889 ctx->pc_succ_insn = ctx->base.pc_first; 890 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 891 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 892 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 893 ctx->priv_ver = env->priv_ver; 894 #if !defined(CONFIG_USER_ONLY) 895 if (riscv_has_ext(env, RVH)) { 896 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 897 } else { 898 ctx->virt_enabled = false; 899 } 900 #else 901 ctx->virt_enabled = false; 902 #endif 903 ctx->misa_ext = env->misa_ext; 904 ctx->frm = -1; /* unknown rounding mode */ 905 ctx->cfg_ptr = &(cpu->cfg); 906 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 907 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 908 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 909 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 910 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 911 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 912 ctx->vstart = env->vstart; 913 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 914 ctx->misa_mxl_max = env->misa_mxl_max; 915 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 916 ctx->cs = cs; 917 ctx->ntemp = 0; 918 memset(ctx->temp, 0, sizeof(ctx->temp)); 919 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 920 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 921 ctx->zero = tcg_constant_tl(0); 922 } 923 924 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 925 { 926 } 927 928 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 929 { 930 DisasContext *ctx = container_of(dcbase, DisasContext, base); 931 932 tcg_gen_insn_start(ctx->base.pc_next); 933 } 934 935 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 936 { 937 DisasContext *ctx = container_of(dcbase, DisasContext, base); 938 CPURISCVState *env = cpu->env_ptr; 939 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 940 941 ctx->ol = ctx->xl; 942 decode_opc(env, ctx, opcode16); 943 ctx->base.pc_next = ctx->pc_succ_insn; 944 945 for (int i = ctx->ntemp - 1; i >= 0; --i) { 946 tcg_temp_free(ctx->temp[i]); 947 ctx->temp[i] = NULL; 948 } 949 ctx->ntemp = 0; 950 951 if (ctx->base.is_jmp == DISAS_NEXT) { 952 target_ulong page_start; 953 954 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 955 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 956 ctx->base.is_jmp = DISAS_TOO_MANY; 957 } 958 } 959 } 960 961 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 962 { 963 DisasContext *ctx = container_of(dcbase, DisasContext, base); 964 965 switch (ctx->base.is_jmp) { 966 case DISAS_TOO_MANY: 967 gen_goto_tb(ctx, 0, ctx->base.pc_next); 968 break; 969 case DISAS_NORETURN: 970 break; 971 default: 972 g_assert_not_reached(); 973 } 974 } 975 976 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 977 { 978 #ifndef CONFIG_USER_ONLY 979 RISCVCPU *rvcpu = RISCV_CPU(cpu); 980 CPURISCVState *env = &rvcpu->env; 981 #endif 982 983 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 984 #ifndef CONFIG_USER_ONLY 985 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 986 #endif 987 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 988 } 989 990 static const TranslatorOps riscv_tr_ops = { 991 .init_disas_context = riscv_tr_init_disas_context, 992 .tb_start = riscv_tr_tb_start, 993 .insn_start = riscv_tr_insn_start, 994 .translate_insn = riscv_tr_translate_insn, 995 .tb_stop = riscv_tr_tb_stop, 996 .disas_log = riscv_tr_disas_log, 997 }; 998 999 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1000 { 1001 DisasContext ctx; 1002 1003 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1004 } 1005 1006 void riscv_translate_init(void) 1007 { 1008 int i; 1009 1010 /* 1011 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1012 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1013 * unless you specifically block reads/writes to reg 0. 1014 */ 1015 cpu_gpr[0] = NULL; 1016 cpu_gprh[0] = NULL; 1017 1018 for (i = 1; i < 32; i++) { 1019 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1020 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1021 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1022 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1023 } 1024 1025 for (i = 0; i < 32; i++) { 1026 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1027 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1028 } 1029 1030 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1031 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1032 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1033 "vstart"); 1034 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1035 "load_res"); 1036 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1037 "load_val"); 1038 /* Assign PM CSRs to tcg globals */ 1039 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1040 "pmmask"); 1041 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1042 "pmbase"); 1043 } 1044