1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 uint8_t vta; 98 bool cfg_vta_all_1s; 99 target_ulong vstart; 100 bool vl_eq_vlmax; 101 uint8_t ntemp; 102 CPUState *cs; 103 TCGv zero; 104 /* Space for 3 operands plus 1 extra for address computation. */ 105 TCGv temp[4]; 106 /* Space for 4 operands(1 dest and <=3 src) for float point computation */ 107 TCGv_i64 ftemp[4]; 108 uint8_t nftemp; 109 /* PointerMasking extension */ 110 bool pm_mask_enabled; 111 bool pm_base_enabled; 112 /* TCG of the current insn_start */ 113 TCGOp *insn_start; 114 } DisasContext; 115 116 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 117 { 118 return ctx->misa_ext & ext; 119 } 120 121 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 122 { 123 return true; 124 } 125 126 #define MATERIALISE_EXT_PREDICATE(ext) \ 127 static bool has_ ## ext ## _p(DisasContext *ctx) \ 128 { \ 129 return ctx->cfg_ptr->ext_ ## ext ; \ 130 } 131 132 MATERIALISE_EXT_PREDICATE(XVentanaCondOps); 133 134 #ifdef TARGET_RISCV32 135 #define get_xl(ctx) MXL_RV32 136 #elif defined(CONFIG_USER_ONLY) 137 #define get_xl(ctx) MXL_RV64 138 #else 139 #define get_xl(ctx) ((ctx)->xl) 140 #endif 141 142 /* The word size for this machine mode. */ 143 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 144 { 145 return 16 << get_xl(ctx); 146 } 147 148 /* The operation length, as opposed to the xlen. */ 149 #ifdef TARGET_RISCV32 150 #define get_ol(ctx) MXL_RV32 151 #else 152 #define get_ol(ctx) ((ctx)->ol) 153 #endif 154 155 static inline int get_olen(DisasContext *ctx) 156 { 157 return 16 << get_ol(ctx); 158 } 159 160 /* The maximum register length */ 161 #ifdef TARGET_RISCV32 162 #define get_xl_max(ctx) MXL_RV32 163 #else 164 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 165 #endif 166 167 /* 168 * RISC-V requires NaN-boxing of narrower width floating point values. 169 * This applies when a 32-bit value is assigned to a 64-bit FP register. 170 * For consistency and simplicity, we nanbox results even when the RVD 171 * extension is not present. 172 */ 173 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 174 { 175 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 176 } 177 178 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 179 { 180 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 181 } 182 183 /* 184 * A narrow n-bit operation, where n < FLEN, checks that input operands 185 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 186 * If so, the least-significant bits of the input are used, otherwise the 187 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 188 * 189 * Here, the result is always nan-boxed, even the canonical nan. 190 */ 191 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 192 { 193 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 194 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 195 196 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 197 tcg_temp_free_i64(t_max); 198 tcg_temp_free_i64(t_nan); 199 } 200 201 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 202 { 203 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 204 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 205 206 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 207 } 208 209 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 210 { 211 if (get_xl(ctx) == MXL_RV32) { 212 dest = (int32_t)dest; 213 } 214 tcg_gen_movi_tl(cpu_pc, dest); 215 } 216 217 static void gen_set_pc(DisasContext *ctx, TCGv dest) 218 { 219 if (get_xl(ctx) == MXL_RV32) { 220 tcg_gen_ext32s_tl(cpu_pc, dest); 221 } else { 222 tcg_gen_mov_tl(cpu_pc, dest); 223 } 224 } 225 226 static void generate_exception(DisasContext *ctx, int excp) 227 { 228 gen_set_pc_imm(ctx, ctx->base.pc_next); 229 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 230 ctx->base.is_jmp = DISAS_NORETURN; 231 } 232 233 static void generate_exception_mtval(DisasContext *ctx, int excp) 234 { 235 gen_set_pc_imm(ctx, ctx->base.pc_next); 236 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 237 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 238 ctx->base.is_jmp = DISAS_NORETURN; 239 } 240 241 static void gen_exception_illegal(DisasContext *ctx) 242 { 243 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 244 } 245 246 static void gen_exception_inst_addr_mis(DisasContext *ctx) 247 { 248 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 249 } 250 251 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 252 { 253 if (translator_use_goto_tb(&ctx->base, dest)) { 254 tcg_gen_goto_tb(n); 255 gen_set_pc_imm(ctx, dest); 256 tcg_gen_exit_tb(ctx->base.tb, n); 257 } else { 258 gen_set_pc_imm(ctx, dest); 259 tcg_gen_lookup_and_goto_ptr(); 260 } 261 } 262 263 /* 264 * Wrappers for getting reg values. 265 * 266 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 267 * constant zero as a source, and an uninitialized sink as destination. 268 * 269 * Further, we may provide an extension for word operations. 270 */ 271 static TCGv temp_new(DisasContext *ctx) 272 { 273 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 274 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 275 } 276 277 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 278 { 279 TCGv t; 280 281 if (reg_num == 0) { 282 return ctx->zero; 283 } 284 285 switch (get_ol(ctx)) { 286 case MXL_RV32: 287 switch (ext) { 288 case EXT_NONE: 289 break; 290 case EXT_SIGN: 291 t = temp_new(ctx); 292 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 293 return t; 294 case EXT_ZERO: 295 t = temp_new(ctx); 296 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 297 return t; 298 default: 299 g_assert_not_reached(); 300 } 301 break; 302 case MXL_RV64: 303 case MXL_RV128: 304 break; 305 default: 306 g_assert_not_reached(); 307 } 308 return cpu_gpr[reg_num]; 309 } 310 311 static TCGv get_gprh(DisasContext *ctx, int reg_num) 312 { 313 assert(get_xl(ctx) == MXL_RV128); 314 if (reg_num == 0) { 315 return ctx->zero; 316 } 317 return cpu_gprh[reg_num]; 318 } 319 320 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 321 { 322 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 323 return temp_new(ctx); 324 } 325 return cpu_gpr[reg_num]; 326 } 327 328 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 329 { 330 if (reg_num == 0) { 331 return temp_new(ctx); 332 } 333 return cpu_gprh[reg_num]; 334 } 335 336 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 337 { 338 if (reg_num != 0) { 339 switch (get_ol(ctx)) { 340 case MXL_RV32: 341 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 342 break; 343 case MXL_RV64: 344 case MXL_RV128: 345 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 346 break; 347 default: 348 g_assert_not_reached(); 349 } 350 351 if (get_xl_max(ctx) == MXL_RV128) { 352 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 353 } 354 } 355 } 356 357 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 358 { 359 if (reg_num != 0) { 360 switch (get_ol(ctx)) { 361 case MXL_RV32: 362 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 363 break; 364 case MXL_RV64: 365 case MXL_RV128: 366 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 367 break; 368 default: 369 g_assert_not_reached(); 370 } 371 372 if (get_xl_max(ctx) == MXL_RV128) { 373 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 374 } 375 } 376 } 377 378 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 379 { 380 assert(get_ol(ctx) == MXL_RV128); 381 if (reg_num != 0) { 382 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 383 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 384 } 385 } 386 387 static TCGv_i64 ftemp_new(DisasContext *ctx) 388 { 389 assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); 390 return ctx->ftemp[ctx->nftemp++] = tcg_temp_new_i64(); 391 } 392 393 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 394 { 395 if (!ctx->cfg_ptr->ext_zfinx) { 396 return cpu_fpr[reg_num]; 397 } 398 399 if (reg_num == 0) { 400 return tcg_constant_i64(0); 401 } 402 switch (get_xl(ctx)) { 403 case MXL_RV32: 404 #ifdef TARGET_RISCV32 405 { 406 TCGv_i64 t = ftemp_new(ctx); 407 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 408 return t; 409 } 410 #else 411 /* fall through */ 412 case MXL_RV64: 413 return cpu_gpr[reg_num]; 414 #endif 415 default: 416 g_assert_not_reached(); 417 } 418 } 419 420 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 421 { 422 if (!ctx->cfg_ptr->ext_zfinx) { 423 return cpu_fpr[reg_num]; 424 } 425 426 if (reg_num == 0) { 427 return tcg_constant_i64(0); 428 } 429 switch (get_xl(ctx)) { 430 case MXL_RV32: 431 { 432 TCGv_i64 t = ftemp_new(ctx); 433 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 434 return t; 435 } 436 #ifdef TARGET_RISCV64 437 case MXL_RV64: 438 return cpu_gpr[reg_num]; 439 #endif 440 default: 441 g_assert_not_reached(); 442 } 443 } 444 445 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 446 { 447 if (!ctx->cfg_ptr->ext_zfinx) { 448 return cpu_fpr[reg_num]; 449 } 450 451 if (reg_num == 0) { 452 return ftemp_new(ctx); 453 } 454 455 switch (get_xl(ctx)) { 456 case MXL_RV32: 457 return ftemp_new(ctx); 458 #ifdef TARGET_RISCV64 459 case MXL_RV64: 460 return cpu_gpr[reg_num]; 461 #endif 462 default: 463 g_assert_not_reached(); 464 } 465 } 466 467 /* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ 468 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 469 { 470 if (!ctx->cfg_ptr->ext_zfinx) { 471 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 472 return; 473 } 474 if (reg_num != 0) { 475 switch (get_xl(ctx)) { 476 case MXL_RV32: 477 #ifdef TARGET_RISCV32 478 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 479 break; 480 #else 481 /* fall through */ 482 case MXL_RV64: 483 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 484 break; 485 #endif 486 default: 487 g_assert_not_reached(); 488 } 489 } 490 } 491 492 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 493 { 494 if (!ctx->cfg_ptr->ext_zfinx) { 495 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 496 return; 497 } 498 499 if (reg_num != 0) { 500 switch (get_xl(ctx)) { 501 case MXL_RV32: 502 #ifdef TARGET_RISCV32 503 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 504 break; 505 #else 506 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 507 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 508 break; 509 case MXL_RV64: 510 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 511 break; 512 #endif 513 default: 514 g_assert_not_reached(); 515 } 516 } 517 } 518 519 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 520 { 521 target_ulong next_pc; 522 523 /* check misaligned: */ 524 next_pc = ctx->base.pc_next + imm; 525 if (!has_ext(ctx, RVC)) { 526 if ((next_pc & 0x3) != 0) { 527 gen_exception_inst_addr_mis(ctx); 528 return; 529 } 530 } 531 532 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 533 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 534 ctx->base.is_jmp = DISAS_NORETURN; 535 } 536 537 /* Compute a canonical address from a register plus offset. */ 538 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 539 { 540 TCGv addr = temp_new(ctx); 541 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 542 543 tcg_gen_addi_tl(addr, src1, imm); 544 if (ctx->pm_mask_enabled) { 545 tcg_gen_and_tl(addr, addr, pm_mask); 546 } else if (get_xl(ctx) == MXL_RV32) { 547 tcg_gen_ext32u_tl(addr, addr); 548 } 549 if (ctx->pm_base_enabled) { 550 tcg_gen_or_tl(addr, addr, pm_base); 551 } 552 return addr; 553 } 554 555 #ifndef CONFIG_USER_ONLY 556 /* The states of mstatus_fs are: 557 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 558 * We will have already diagnosed disabled state, 559 * and need to turn initial/clean into dirty. 560 */ 561 static void mark_fs_dirty(DisasContext *ctx) 562 { 563 TCGv tmp; 564 565 if (!has_ext(ctx, RVF)) { 566 return; 567 } 568 569 if (ctx->mstatus_fs != MSTATUS_FS) { 570 /* Remember the state change for the rest of the TB. */ 571 ctx->mstatus_fs = MSTATUS_FS; 572 573 tmp = tcg_temp_new(); 574 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 575 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 576 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 577 tcg_temp_free(tmp); 578 } 579 580 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 581 /* Remember the stage change for the rest of the TB. */ 582 ctx->mstatus_hs_fs = MSTATUS_FS; 583 584 tmp = tcg_temp_new(); 585 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 586 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 587 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 588 tcg_temp_free(tmp); 589 } 590 } 591 #else 592 static inline void mark_fs_dirty(DisasContext *ctx) { } 593 #endif 594 595 #ifndef CONFIG_USER_ONLY 596 /* The states of mstatus_vs are: 597 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 598 * We will have already diagnosed disabled state, 599 * and need to turn initial/clean into dirty. 600 */ 601 static void mark_vs_dirty(DisasContext *ctx) 602 { 603 TCGv tmp; 604 605 if (ctx->mstatus_vs != MSTATUS_VS) { 606 /* Remember the state change for the rest of the TB. */ 607 ctx->mstatus_vs = MSTATUS_VS; 608 609 tmp = tcg_temp_new(); 610 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 611 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 612 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 613 tcg_temp_free(tmp); 614 } 615 616 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 617 /* Remember the stage change for the rest of the TB. */ 618 ctx->mstatus_hs_vs = MSTATUS_VS; 619 620 tmp = tcg_temp_new(); 621 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 622 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 623 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 624 tcg_temp_free(tmp); 625 } 626 } 627 #else 628 static inline void mark_vs_dirty(DisasContext *ctx) { } 629 #endif 630 631 static void gen_set_rm(DisasContext *ctx, int rm) 632 { 633 if (ctx->frm == rm) { 634 return; 635 } 636 ctx->frm = rm; 637 638 if (rm == RISCV_FRM_ROD) { 639 gen_helper_set_rod_rounding_mode(cpu_env); 640 return; 641 } 642 643 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 644 } 645 646 static int ex_plus_1(DisasContext *ctx, int nf) 647 { 648 return nf + 1; 649 } 650 651 #define EX_SH(amount) \ 652 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 653 { \ 654 return imm << amount; \ 655 } 656 EX_SH(1) 657 EX_SH(2) 658 EX_SH(3) 659 EX_SH(4) 660 EX_SH(12) 661 662 #define REQUIRE_EXT(ctx, ext) do { \ 663 if (!has_ext(ctx, ext)) { \ 664 return false; \ 665 } \ 666 } while (0) 667 668 #define REQUIRE_32BIT(ctx) do { \ 669 if (get_xl(ctx) != MXL_RV32) { \ 670 return false; \ 671 } \ 672 } while (0) 673 674 #define REQUIRE_64BIT(ctx) do { \ 675 if (get_xl(ctx) != MXL_RV64) { \ 676 return false; \ 677 } \ 678 } while (0) 679 680 #define REQUIRE_128BIT(ctx) do { \ 681 if (get_xl(ctx) != MXL_RV128) { \ 682 return false; \ 683 } \ 684 } while (0) 685 686 #define REQUIRE_64_OR_128BIT(ctx) do { \ 687 if (get_xl(ctx) == MXL_RV32) { \ 688 return false; \ 689 } \ 690 } while (0) 691 692 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 693 if (!ctx->cfg_ptr->ext_##A && \ 694 !ctx->cfg_ptr->ext_##B) { \ 695 return false; \ 696 } \ 697 } while (0) 698 699 static int ex_rvc_register(DisasContext *ctx, int reg) 700 { 701 return 8 + reg; 702 } 703 704 static int ex_rvc_shifti(DisasContext *ctx, int imm) 705 { 706 /* For RV128 a shamt of 0 means a shift by 64. */ 707 return imm ? imm : 64; 708 } 709 710 /* Include the auto-generated decoder for 32 bit insn */ 711 #include "decode-insn32.c.inc" 712 713 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 714 void (*func)(TCGv, TCGv, target_long)) 715 { 716 TCGv dest = dest_gpr(ctx, a->rd); 717 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 718 719 func(dest, src1, a->imm); 720 721 if (get_xl(ctx) == MXL_RV128) { 722 TCGv src1h = get_gprh(ctx, a->rs1); 723 TCGv desth = dest_gprh(ctx, a->rd); 724 725 func(desth, src1h, -(a->imm < 0)); 726 gen_set_gpr128(ctx, a->rd, dest, desth); 727 } else { 728 gen_set_gpr(ctx, a->rd, dest); 729 } 730 731 return true; 732 } 733 734 static bool gen_logic(DisasContext *ctx, arg_r *a, 735 void (*func)(TCGv, TCGv, TCGv)) 736 { 737 TCGv dest = dest_gpr(ctx, a->rd); 738 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 739 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 740 741 func(dest, src1, src2); 742 743 if (get_xl(ctx) == MXL_RV128) { 744 TCGv src1h = get_gprh(ctx, a->rs1); 745 TCGv src2h = get_gprh(ctx, a->rs2); 746 TCGv desth = dest_gprh(ctx, a->rd); 747 748 func(desth, src1h, src2h); 749 gen_set_gpr128(ctx, a->rd, dest, desth); 750 } else { 751 gen_set_gpr(ctx, a->rd, dest); 752 } 753 754 return true; 755 } 756 757 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 758 void (*func)(TCGv, TCGv, target_long), 759 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 760 { 761 TCGv dest = dest_gpr(ctx, a->rd); 762 TCGv src1 = get_gpr(ctx, a->rs1, ext); 763 764 if (get_ol(ctx) < MXL_RV128) { 765 func(dest, src1, a->imm); 766 gen_set_gpr(ctx, a->rd, dest); 767 } else { 768 if (f128 == NULL) { 769 return false; 770 } 771 772 TCGv src1h = get_gprh(ctx, a->rs1); 773 TCGv desth = dest_gprh(ctx, a->rd); 774 775 f128(dest, desth, src1, src1h, a->imm); 776 gen_set_gpr128(ctx, a->rd, dest, desth); 777 } 778 return true; 779 } 780 781 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 782 void (*func)(TCGv, TCGv, TCGv), 783 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 784 { 785 TCGv dest = dest_gpr(ctx, a->rd); 786 TCGv src1 = get_gpr(ctx, a->rs1, ext); 787 TCGv src2 = tcg_constant_tl(a->imm); 788 789 if (get_ol(ctx) < MXL_RV128) { 790 func(dest, src1, src2); 791 gen_set_gpr(ctx, a->rd, dest); 792 } else { 793 if (f128 == NULL) { 794 return false; 795 } 796 797 TCGv src1h = get_gprh(ctx, a->rs1); 798 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 799 TCGv desth = dest_gprh(ctx, a->rd); 800 801 f128(dest, desth, src1, src1h, src2, src2h); 802 gen_set_gpr128(ctx, a->rd, dest, desth); 803 } 804 return true; 805 } 806 807 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 808 void (*func)(TCGv, TCGv, TCGv), 809 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 810 { 811 TCGv dest = dest_gpr(ctx, a->rd); 812 TCGv src1 = get_gpr(ctx, a->rs1, ext); 813 TCGv src2 = get_gpr(ctx, a->rs2, ext); 814 815 if (get_ol(ctx) < MXL_RV128) { 816 func(dest, src1, src2); 817 gen_set_gpr(ctx, a->rd, dest); 818 } else { 819 if (f128 == NULL) { 820 return false; 821 } 822 823 TCGv src1h = get_gprh(ctx, a->rs1); 824 TCGv src2h = get_gprh(ctx, a->rs2); 825 TCGv desth = dest_gprh(ctx, a->rd); 826 827 f128(dest, desth, src1, src1h, src2, src2h); 828 gen_set_gpr128(ctx, a->rd, dest, desth); 829 } 830 return true; 831 } 832 833 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 834 void (*f_tl)(TCGv, TCGv, TCGv), 835 void (*f_32)(TCGv, TCGv, TCGv), 836 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 837 { 838 int olen = get_olen(ctx); 839 840 if (olen != TARGET_LONG_BITS) { 841 if (olen == 32) { 842 f_tl = f_32; 843 } else if (olen != 128) { 844 g_assert_not_reached(); 845 } 846 } 847 return gen_arith(ctx, a, ext, f_tl, f_128); 848 } 849 850 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 851 void (*func)(TCGv, TCGv, target_long), 852 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 853 { 854 TCGv dest, src1; 855 int max_len = get_olen(ctx); 856 857 if (a->shamt >= max_len) { 858 return false; 859 } 860 861 dest = dest_gpr(ctx, a->rd); 862 src1 = get_gpr(ctx, a->rs1, ext); 863 864 if (max_len < 128) { 865 func(dest, src1, a->shamt); 866 gen_set_gpr(ctx, a->rd, dest); 867 } else { 868 TCGv src1h = get_gprh(ctx, a->rs1); 869 TCGv desth = dest_gprh(ctx, a->rd); 870 871 if (f128 == NULL) { 872 return false; 873 } 874 f128(dest, desth, src1, src1h, a->shamt); 875 gen_set_gpr128(ctx, a->rd, dest, desth); 876 } 877 return true; 878 } 879 880 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 881 DisasExtend ext, 882 void (*f_tl)(TCGv, TCGv, target_long), 883 void (*f_32)(TCGv, TCGv, target_long), 884 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 885 target_long)) 886 { 887 int olen = get_olen(ctx); 888 if (olen != TARGET_LONG_BITS) { 889 if (olen == 32) { 890 f_tl = f_32; 891 } else if (olen != 128) { 892 g_assert_not_reached(); 893 } 894 } 895 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 896 } 897 898 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 899 void (*func)(TCGv, TCGv, TCGv)) 900 { 901 TCGv dest, src1, src2; 902 int max_len = get_olen(ctx); 903 904 if (a->shamt >= max_len) { 905 return false; 906 } 907 908 dest = dest_gpr(ctx, a->rd); 909 src1 = get_gpr(ctx, a->rs1, ext); 910 src2 = tcg_constant_tl(a->shamt); 911 912 func(dest, src1, src2); 913 914 gen_set_gpr(ctx, a->rd, dest); 915 return true; 916 } 917 918 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 919 void (*func)(TCGv, TCGv, TCGv), 920 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 921 { 922 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 923 TCGv ext2 = tcg_temp_new(); 924 int max_len = get_olen(ctx); 925 926 tcg_gen_andi_tl(ext2, src2, max_len - 1); 927 928 TCGv dest = dest_gpr(ctx, a->rd); 929 TCGv src1 = get_gpr(ctx, a->rs1, ext); 930 931 if (max_len < 128) { 932 func(dest, src1, ext2); 933 gen_set_gpr(ctx, a->rd, dest); 934 } else { 935 TCGv src1h = get_gprh(ctx, a->rs1); 936 TCGv desth = dest_gprh(ctx, a->rd); 937 938 if (f128 == NULL) { 939 return false; 940 } 941 f128(dest, desth, src1, src1h, ext2); 942 gen_set_gpr128(ctx, a->rd, dest, desth); 943 } 944 tcg_temp_free(ext2); 945 return true; 946 } 947 948 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 949 void (*f_tl)(TCGv, TCGv, TCGv), 950 void (*f_32)(TCGv, TCGv, TCGv), 951 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 952 { 953 int olen = get_olen(ctx); 954 if (olen != TARGET_LONG_BITS) { 955 if (olen == 32) { 956 f_tl = f_32; 957 } else if (olen != 128) { 958 g_assert_not_reached(); 959 } 960 } 961 return gen_shift(ctx, a, ext, f_tl, f_128); 962 } 963 964 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 965 void (*func)(TCGv, TCGv)) 966 { 967 TCGv dest = dest_gpr(ctx, a->rd); 968 TCGv src1 = get_gpr(ctx, a->rs1, ext); 969 970 func(dest, src1); 971 972 gen_set_gpr(ctx, a->rd, dest); 973 return true; 974 } 975 976 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 977 void (*f_tl)(TCGv, TCGv), 978 void (*f_32)(TCGv, TCGv)) 979 { 980 int olen = get_olen(ctx); 981 982 if (olen != TARGET_LONG_BITS) { 983 if (olen == 32) { 984 f_tl = f_32; 985 } else { 986 g_assert_not_reached(); 987 } 988 } 989 return gen_unary(ctx, a, ext, f_tl); 990 } 991 992 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 993 { 994 DisasContext *ctx = container_of(dcbase, DisasContext, base); 995 CPUState *cpu = ctx->cs; 996 CPURISCVState *env = cpu->env_ptr; 997 998 return cpu_ldl_code(env, pc); 999 } 1000 1001 /* Include insn module translation function */ 1002 #include "insn_trans/trans_rvi.c.inc" 1003 #include "insn_trans/trans_rvm.c.inc" 1004 #include "insn_trans/trans_rva.c.inc" 1005 #include "insn_trans/trans_rvf.c.inc" 1006 #include "insn_trans/trans_rvd.c.inc" 1007 #include "insn_trans/trans_rvh.c.inc" 1008 #include "insn_trans/trans_rvv.c.inc" 1009 #include "insn_trans/trans_rvb.c.inc" 1010 #include "insn_trans/trans_rvzfh.c.inc" 1011 #include "insn_trans/trans_rvk.c.inc" 1012 #include "insn_trans/trans_privileged.c.inc" 1013 #include "insn_trans/trans_svinval.c.inc" 1014 #include "insn_trans/trans_xventanacondops.c.inc" 1015 1016 /* Include the auto-generated decoder for 16 bit insn */ 1017 #include "decode-insn16.c.inc" 1018 /* Include decoders for factored-out extensions */ 1019 #include "decode-XVentanaCondOps.c.inc" 1020 1021 static inline void decode_save_opc(DisasContext *ctx, target_ulong opc) 1022 { 1023 assert(ctx->insn_start != NULL); 1024 tcg_set_insn_start_param(ctx->insn_start, 1, opc); 1025 ctx->insn_start = NULL; 1026 } 1027 1028 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1029 { 1030 /* 1031 * A table with predicate (i.e., guard) functions and decoder functions 1032 * that are tested in-order until a decoder matches onto the opcode. 1033 */ 1034 static const struct { 1035 bool (*guard_func)(DisasContext *); 1036 bool (*decode_func)(DisasContext *, uint32_t); 1037 } decoders[] = { 1038 { always_true_p, decode_insn32 }, 1039 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1040 }; 1041 1042 /* Check for compressed insn */ 1043 if (extract16(opcode, 0, 2) != 3) { 1044 decode_save_opc(ctx, opcode); 1045 if (!has_ext(ctx, RVC)) { 1046 gen_exception_illegal(ctx); 1047 } else { 1048 ctx->opcode = opcode; 1049 ctx->pc_succ_insn = ctx->base.pc_next + 2; 1050 if (decode_insn16(ctx, opcode)) { 1051 return; 1052 } 1053 } 1054 } else { 1055 uint32_t opcode32 = opcode; 1056 opcode32 = deposit32(opcode32, 16, 16, 1057 translator_lduw(env, &ctx->base, 1058 ctx->base.pc_next + 2)); 1059 decode_save_opc(ctx, opcode32); 1060 ctx->opcode = opcode32; 1061 ctx->pc_succ_insn = ctx->base.pc_next + 4; 1062 1063 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1064 if (decoders[i].guard_func(ctx) && 1065 decoders[i].decode_func(ctx, opcode32)) { 1066 return; 1067 } 1068 } 1069 } 1070 1071 gen_exception_illegal(ctx); 1072 } 1073 1074 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1075 { 1076 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1077 CPURISCVState *env = cs->env_ptr; 1078 RISCVCPU *cpu = RISCV_CPU(cs); 1079 uint32_t tb_flags = ctx->base.tb->flags; 1080 1081 ctx->pc_succ_insn = ctx->base.pc_first; 1082 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1083 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 1084 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 1085 ctx->priv_ver = env->priv_ver; 1086 #if !defined(CONFIG_USER_ONLY) 1087 if (riscv_has_ext(env, RVH)) { 1088 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 1089 } else { 1090 ctx->virt_enabled = false; 1091 } 1092 #else 1093 ctx->virt_enabled = false; 1094 #endif 1095 ctx->misa_ext = env->misa_ext; 1096 ctx->frm = -1; /* unknown rounding mode */ 1097 ctx->cfg_ptr = &(cpu->cfg); 1098 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 1099 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 1100 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 1101 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1102 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1103 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1104 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1105 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1106 ctx->vstart = env->vstart; 1107 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1108 ctx->misa_mxl_max = env->misa_mxl_max; 1109 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1110 ctx->cs = cs; 1111 ctx->ntemp = 0; 1112 memset(ctx->temp, 0, sizeof(ctx->temp)); 1113 ctx->nftemp = 0; 1114 memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); 1115 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1116 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1117 ctx->zero = tcg_constant_tl(0); 1118 } 1119 1120 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1121 { 1122 } 1123 1124 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1125 { 1126 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1127 1128 tcg_gen_insn_start(ctx->base.pc_next, 0); 1129 ctx->insn_start = tcg_last_op(); 1130 } 1131 1132 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1133 { 1134 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1135 CPURISCVState *env = cpu->env_ptr; 1136 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1137 int i; 1138 1139 ctx->ol = ctx->xl; 1140 decode_opc(env, ctx, opcode16); 1141 ctx->base.pc_next = ctx->pc_succ_insn; 1142 1143 for (i = ctx->ntemp - 1; i >= 0; --i) { 1144 tcg_temp_free(ctx->temp[i]); 1145 ctx->temp[i] = NULL; 1146 } 1147 ctx->ntemp = 0; 1148 for (i = ctx->nftemp - 1; i >= 0; --i) { 1149 tcg_temp_free_i64(ctx->ftemp[i]); 1150 ctx->ftemp[i] = NULL; 1151 } 1152 ctx->nftemp = 0; 1153 1154 if (ctx->base.is_jmp == DISAS_NEXT) { 1155 target_ulong page_start; 1156 1157 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 1158 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 1159 ctx->base.is_jmp = DISAS_TOO_MANY; 1160 } 1161 } 1162 } 1163 1164 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1165 { 1166 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1167 1168 switch (ctx->base.is_jmp) { 1169 case DISAS_TOO_MANY: 1170 gen_goto_tb(ctx, 0, ctx->base.pc_next); 1171 break; 1172 case DISAS_NORETURN: 1173 break; 1174 default: 1175 g_assert_not_reached(); 1176 } 1177 } 1178 1179 static void riscv_tr_disas_log(const DisasContextBase *dcbase, 1180 CPUState *cpu, FILE *logfile) 1181 { 1182 #ifndef CONFIG_USER_ONLY 1183 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1184 CPURISCVState *env = &rvcpu->env; 1185 #endif 1186 1187 fprintf(logfile, "IN: %s\n", lookup_symbol(dcbase->pc_first)); 1188 #ifndef CONFIG_USER_ONLY 1189 fprintf(logfile, "Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", 1190 env->priv, env->virt); 1191 #endif 1192 target_disas(logfile, cpu, dcbase->pc_first, dcbase->tb->size); 1193 } 1194 1195 static const TranslatorOps riscv_tr_ops = { 1196 .init_disas_context = riscv_tr_init_disas_context, 1197 .tb_start = riscv_tr_tb_start, 1198 .insn_start = riscv_tr_insn_start, 1199 .translate_insn = riscv_tr_translate_insn, 1200 .tb_stop = riscv_tr_tb_stop, 1201 .disas_log = riscv_tr_disas_log, 1202 }; 1203 1204 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1205 { 1206 DisasContext ctx; 1207 1208 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1209 } 1210 1211 void riscv_translate_init(void) 1212 { 1213 int i; 1214 1215 /* 1216 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1217 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1218 * unless you specifically block reads/writes to reg 0. 1219 */ 1220 cpu_gpr[0] = NULL; 1221 cpu_gprh[0] = NULL; 1222 1223 for (i = 1; i < 32; i++) { 1224 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1225 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1226 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1227 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1228 } 1229 1230 for (i = 0; i < 32; i++) { 1231 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1232 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1233 } 1234 1235 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1236 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1237 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1238 "vstart"); 1239 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1240 "load_res"); 1241 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1242 "load_val"); 1243 /* Assign PM CSRs to tcg globals */ 1244 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1245 "pmmask"); 1246 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1247 "pmbase"); 1248 } 1249