1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "exec/exec-all.h" 24 #include "exec/helper-proto.h" 25 #include "exec/helper-gen.h" 26 27 #include "exec/translator.h" 28 #include "exec/log.h" 29 #include "semihosting/semihost.h" 30 31 #include "internals.h" 32 33 #define HELPER_H "helper.h" 34 #include "exec/helper-info.c.inc" 35 #undef HELPER_H 36 37 /* global register indices */ 38 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 39 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 40 static TCGv load_res; 41 static TCGv load_val; 42 /* globals for PM CSRs */ 43 static TCGv pm_mask; 44 static TCGv pm_base; 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 target_ulong cur_insn_len; 60 target_ulong pc_save; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 RISCVMXL address_xl; 65 uint32_t misa_ext; 66 uint32_t opcode; 67 RISCVExtStatus mstatus_fs; 68 RISCVExtStatus mstatus_vs; 69 uint32_t mem_idx; 70 uint32_t priv; 71 /* 72 * Remember the rounding mode encoded in the previous fp instruction, 73 * which we have already installed into env->fp_status. Or -1 for 74 * no previous fp instruction. Note that we exit the TB when writing 75 * to any system register, which includes CSR_FRM, so we do not have 76 * to reset this known value. 77 */ 78 int frm; 79 RISCVMXL ol; 80 bool virt_inst_excp; 81 bool virt_enabled; 82 const RISCVCPUConfig *cfg_ptr; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint8_t vta; 100 uint8_t vma; 101 bool cfg_vta_all_1s; 102 bool vstart_eq_zero; 103 bool vl_eq_vlmax; 104 CPUState *cs; 105 TCGv zero; 106 /* PointerMasking extension */ 107 bool pm_mask_enabled; 108 bool pm_base_enabled; 109 /* Ztso */ 110 bool ztso; 111 /* Use icount trigger for native debug */ 112 bool itrigger; 113 /* FRM is known to contain a valid value. */ 114 bool frm_valid; 115 bool insn_start_updated; 116 } DisasContext; 117 118 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 119 { 120 return ctx->misa_ext & ext; 121 } 122 123 #ifdef TARGET_RISCV32 124 #define get_xl(ctx) MXL_RV32 125 #elif defined(CONFIG_USER_ONLY) 126 #define get_xl(ctx) MXL_RV64 127 #else 128 #define get_xl(ctx) ((ctx)->xl) 129 #endif 130 131 #ifdef TARGET_RISCV32 132 #define get_address_xl(ctx) MXL_RV32 133 #elif defined(CONFIG_USER_ONLY) 134 #define get_address_xl(ctx) MXL_RV64 135 #else 136 #define get_address_xl(ctx) ((ctx)->address_xl) 137 #endif 138 139 /* The word size for this machine mode. */ 140 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 141 { 142 return 16 << get_xl(ctx); 143 } 144 145 /* The operation length, as opposed to the xlen. */ 146 #ifdef TARGET_RISCV32 147 #define get_ol(ctx) MXL_RV32 148 #else 149 #define get_ol(ctx) ((ctx)->ol) 150 #endif 151 152 static inline int get_olen(DisasContext *ctx) 153 { 154 return 16 << get_ol(ctx); 155 } 156 157 /* The maximum register length */ 158 #ifdef TARGET_RISCV32 159 #define get_xl_max(ctx) MXL_RV32 160 #else 161 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 162 #endif 163 164 /* 165 * RISC-V requires NaN-boxing of narrower width floating point values. 166 * This applies when a 32-bit value is assigned to a 64-bit FP register. 167 * For consistency and simplicity, we nanbox results even when the RVD 168 * extension is not present. 169 */ 170 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 171 { 172 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 173 } 174 175 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 176 { 177 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 178 } 179 180 /* 181 * A narrow n-bit operation, where n < FLEN, checks that input operands 182 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 183 * If so, the least-significant bits of the input are used, otherwise the 184 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 185 * 186 * Here, the result is always nan-boxed, even the canonical nan. 187 */ 188 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 189 { 190 TCGv_i64 t_max = tcg_constant_i64(0xffffffffffff0000ull); 191 TCGv_i64 t_nan = tcg_constant_i64(0xffffffffffff7e00ull); 192 193 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 194 } 195 196 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 197 { 198 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 199 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 200 201 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 202 } 203 204 static void decode_save_opc(DisasContext *ctx) 205 { 206 assert(!ctx->insn_start_updated); 207 ctx->insn_start_updated = true; 208 tcg_set_insn_start_param(ctx->base.insn_start, 1, ctx->opcode); 209 } 210 211 static void gen_pc_plus_diff(TCGv target, DisasContext *ctx, 212 target_long diff) 213 { 214 target_ulong dest = ctx->base.pc_next + diff; 215 216 assert(ctx->pc_save != -1); 217 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 218 tcg_gen_addi_tl(target, cpu_pc, dest - ctx->pc_save); 219 if (get_xl(ctx) == MXL_RV32) { 220 tcg_gen_ext32s_tl(target, target); 221 } 222 } else { 223 if (get_xl(ctx) == MXL_RV32) { 224 dest = (int32_t)dest; 225 } 226 tcg_gen_movi_tl(target, dest); 227 } 228 } 229 230 static void gen_update_pc(DisasContext *ctx, target_long diff) 231 { 232 gen_pc_plus_diff(cpu_pc, ctx, diff); 233 ctx->pc_save = ctx->base.pc_next + diff; 234 } 235 236 static void generate_exception(DisasContext *ctx, int excp) 237 { 238 gen_update_pc(ctx, 0); 239 gen_helper_raise_exception(tcg_env, tcg_constant_i32(excp)); 240 ctx->base.is_jmp = DISAS_NORETURN; 241 } 242 243 static void gen_exception_illegal(DisasContext *ctx) 244 { 245 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), tcg_env, 246 offsetof(CPURISCVState, bins)); 247 if (ctx->virt_inst_excp) { 248 generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT); 249 } else { 250 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 251 } 252 } 253 254 static void gen_exception_inst_addr_mis(DisasContext *ctx, TCGv target) 255 { 256 tcg_gen_st_tl(target, tcg_env, offsetof(CPURISCVState, badaddr)); 257 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); 258 } 259 260 static void lookup_and_goto_ptr(DisasContext *ctx) 261 { 262 #ifndef CONFIG_USER_ONLY 263 if (ctx->itrigger) { 264 gen_helper_itrigger_match(tcg_env); 265 } 266 #endif 267 tcg_gen_lookup_and_goto_ptr(); 268 } 269 270 static void exit_tb(DisasContext *ctx) 271 { 272 #ifndef CONFIG_USER_ONLY 273 if (ctx->itrigger) { 274 gen_helper_itrigger_match(tcg_env); 275 } 276 #endif 277 tcg_gen_exit_tb(NULL, 0); 278 } 279 280 static void gen_goto_tb(DisasContext *ctx, int n, target_long diff) 281 { 282 target_ulong dest = ctx->base.pc_next + diff; 283 284 /* 285 * Under itrigger, instruction executes one by one like singlestep, 286 * direct block chain benefits will be small. 287 */ 288 if (translator_use_goto_tb(&ctx->base, dest) && !ctx->itrigger) { 289 /* 290 * For pcrel, the pc must always be up-to-date on entry to 291 * the linked TB, so that it can use simple additions for all 292 * further adjustments. For !pcrel, the linked TB is compiled 293 * to know its full virtual address, so we can delay the 294 * update to pc to the unlinked path. A long chain of links 295 * can thus avoid many updates to the PC. 296 */ 297 if (tb_cflags(ctx->base.tb) & CF_PCREL) { 298 gen_update_pc(ctx, diff); 299 tcg_gen_goto_tb(n); 300 } else { 301 tcg_gen_goto_tb(n); 302 gen_update_pc(ctx, diff); 303 } 304 tcg_gen_exit_tb(ctx->base.tb, n); 305 } else { 306 gen_update_pc(ctx, diff); 307 lookup_and_goto_ptr(ctx); 308 } 309 } 310 311 /* 312 * Wrappers for getting reg values. 313 * 314 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 315 * constant zero as a source, and an uninitialized sink as destination. 316 * 317 * Further, we may provide an extension for word operations. 318 */ 319 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 320 { 321 TCGv t; 322 323 if (reg_num == 0) { 324 return ctx->zero; 325 } 326 327 switch (get_ol(ctx)) { 328 case MXL_RV32: 329 switch (ext) { 330 case EXT_NONE: 331 break; 332 case EXT_SIGN: 333 t = tcg_temp_new(); 334 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 335 return t; 336 case EXT_ZERO: 337 t = tcg_temp_new(); 338 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 339 return t; 340 default: 341 g_assert_not_reached(); 342 } 343 break; 344 case MXL_RV64: 345 case MXL_RV128: 346 break; 347 default: 348 g_assert_not_reached(); 349 } 350 return cpu_gpr[reg_num]; 351 } 352 353 static TCGv get_gprh(DisasContext *ctx, int reg_num) 354 { 355 assert(get_xl(ctx) == MXL_RV128); 356 if (reg_num == 0) { 357 return ctx->zero; 358 } 359 return cpu_gprh[reg_num]; 360 } 361 362 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 363 { 364 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 365 return tcg_temp_new(); 366 } 367 return cpu_gpr[reg_num]; 368 } 369 370 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 371 { 372 if (reg_num == 0) { 373 return tcg_temp_new(); 374 } 375 return cpu_gprh[reg_num]; 376 } 377 378 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 379 { 380 if (reg_num != 0) { 381 switch (get_ol(ctx)) { 382 case MXL_RV32: 383 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 384 break; 385 case MXL_RV64: 386 case MXL_RV128: 387 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 388 break; 389 default: 390 g_assert_not_reached(); 391 } 392 393 if (get_xl_max(ctx) == MXL_RV128) { 394 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 395 } 396 } 397 } 398 399 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 400 { 401 if (reg_num != 0) { 402 switch (get_ol(ctx)) { 403 case MXL_RV32: 404 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 405 break; 406 case MXL_RV64: 407 case MXL_RV128: 408 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 409 break; 410 default: 411 g_assert_not_reached(); 412 } 413 414 if (get_xl_max(ctx) == MXL_RV128) { 415 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 416 } 417 } 418 } 419 420 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 421 { 422 assert(get_ol(ctx) == MXL_RV128); 423 if (reg_num != 0) { 424 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 425 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 426 } 427 } 428 429 static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) 430 { 431 if (!ctx->cfg_ptr->ext_zfinx) { 432 return cpu_fpr[reg_num]; 433 } 434 435 if (reg_num == 0) { 436 return tcg_constant_i64(0); 437 } 438 switch (get_xl(ctx)) { 439 case MXL_RV32: 440 #ifdef TARGET_RISCV32 441 { 442 TCGv_i64 t = tcg_temp_new_i64(); 443 tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); 444 return t; 445 } 446 #else 447 /* fall through */ 448 case MXL_RV64: 449 return cpu_gpr[reg_num]; 450 #endif 451 default: 452 g_assert_not_reached(); 453 } 454 } 455 456 static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) 457 { 458 if (!ctx->cfg_ptr->ext_zfinx) { 459 return cpu_fpr[reg_num]; 460 } 461 462 if (reg_num == 0) { 463 return tcg_constant_i64(0); 464 } 465 switch (get_xl(ctx)) { 466 case MXL_RV32: 467 { 468 TCGv_i64 t = tcg_temp_new_i64(); 469 tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); 470 return t; 471 } 472 #ifdef TARGET_RISCV64 473 case MXL_RV64: 474 return cpu_gpr[reg_num]; 475 #endif 476 default: 477 g_assert_not_reached(); 478 } 479 } 480 481 static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) 482 { 483 if (!ctx->cfg_ptr->ext_zfinx) { 484 return cpu_fpr[reg_num]; 485 } 486 487 if (reg_num == 0) { 488 return tcg_temp_new_i64(); 489 } 490 491 switch (get_xl(ctx)) { 492 case MXL_RV32: 493 return tcg_temp_new_i64(); 494 #ifdef TARGET_RISCV64 495 case MXL_RV64: 496 return cpu_gpr[reg_num]; 497 #endif 498 default: 499 g_assert_not_reached(); 500 } 501 } 502 503 /* assume it is nanboxing (for normal) or sign-extended (for zfinx) */ 504 static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) 505 { 506 if (!ctx->cfg_ptr->ext_zfinx) { 507 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 508 return; 509 } 510 if (reg_num != 0) { 511 switch (get_xl(ctx)) { 512 case MXL_RV32: 513 #ifdef TARGET_RISCV32 514 tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); 515 break; 516 #else 517 /* fall through */ 518 case MXL_RV64: 519 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 520 break; 521 #endif 522 default: 523 g_assert_not_reached(); 524 } 525 } 526 } 527 528 static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) 529 { 530 if (!ctx->cfg_ptr->ext_zfinx) { 531 tcg_gen_mov_i64(cpu_fpr[reg_num], t); 532 return; 533 } 534 535 if (reg_num != 0) { 536 switch (get_xl(ctx)) { 537 case MXL_RV32: 538 #ifdef TARGET_RISCV32 539 tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t); 540 break; 541 #else 542 tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); 543 tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); 544 break; 545 case MXL_RV64: 546 tcg_gen_mov_i64(cpu_gpr[reg_num], t); 547 break; 548 #endif 549 default: 550 g_assert_not_reached(); 551 } 552 } 553 } 554 555 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 556 { 557 TCGv succ_pc = dest_gpr(ctx, rd); 558 559 /* check misaligned: */ 560 if (!has_ext(ctx, RVC) && !ctx->cfg_ptr->ext_zca) { 561 if ((imm & 0x3) != 0) { 562 TCGv target_pc = tcg_temp_new(); 563 gen_pc_plus_diff(target_pc, ctx, imm); 564 gen_exception_inst_addr_mis(ctx, target_pc); 565 return; 566 } 567 } 568 569 gen_pc_plus_diff(succ_pc, ctx, ctx->cur_insn_len); 570 gen_set_gpr(ctx, rd, succ_pc); 571 572 gen_goto_tb(ctx, 0, imm); /* must use this for safety */ 573 ctx->base.is_jmp = DISAS_NORETURN; 574 } 575 576 /* Compute a canonical address from a register plus offset. */ 577 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 578 { 579 TCGv addr = tcg_temp_new(); 580 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 581 582 tcg_gen_addi_tl(addr, src1, imm); 583 if (ctx->pm_mask_enabled) { 584 tcg_gen_andc_tl(addr, addr, pm_mask); 585 } else if (get_address_xl(ctx) == MXL_RV32) { 586 tcg_gen_ext32u_tl(addr, addr); 587 } 588 if (ctx->pm_base_enabled) { 589 tcg_gen_or_tl(addr, addr, pm_base); 590 } 591 592 return addr; 593 } 594 595 /* Compute a canonical address from a register plus reg offset. */ 596 static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) 597 { 598 TCGv addr = tcg_temp_new(); 599 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 600 601 tcg_gen_add_tl(addr, src1, offs); 602 if (ctx->pm_mask_enabled) { 603 tcg_gen_andc_tl(addr, addr, pm_mask); 604 } else if (get_xl(ctx) == MXL_RV32) { 605 tcg_gen_ext32u_tl(addr, addr); 606 } 607 if (ctx->pm_base_enabled) { 608 tcg_gen_or_tl(addr, addr, pm_base); 609 } 610 return addr; 611 } 612 613 #ifndef CONFIG_USER_ONLY 614 /* 615 * We will have already diagnosed disabled state, 616 * and need to turn initial/clean into dirty. 617 */ 618 static void mark_fs_dirty(DisasContext *ctx) 619 { 620 TCGv tmp; 621 622 if (!has_ext(ctx, RVF)) { 623 return; 624 } 625 626 if (ctx->mstatus_fs != EXT_STATUS_DIRTY) { 627 /* Remember the state change for the rest of the TB. */ 628 ctx->mstatus_fs = EXT_STATUS_DIRTY; 629 630 tmp = tcg_temp_new(); 631 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 632 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 633 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 634 635 if (ctx->virt_enabled) { 636 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 637 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 638 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 639 } 640 } 641 } 642 #else 643 static inline void mark_fs_dirty(DisasContext *ctx) { } 644 #endif 645 646 #ifndef CONFIG_USER_ONLY 647 /* 648 * We will have already diagnosed disabled state, 649 * and need to turn initial/clean into dirty. 650 */ 651 static void mark_vs_dirty(DisasContext *ctx) 652 { 653 TCGv tmp; 654 655 if (ctx->mstatus_vs != EXT_STATUS_DIRTY) { 656 /* Remember the state change for the rest of the TB. */ 657 ctx->mstatus_vs = EXT_STATUS_DIRTY; 658 659 tmp = tcg_temp_new(); 660 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 661 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 662 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus)); 663 664 if (ctx->virt_enabled) { 665 tcg_gen_ld_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 666 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 667 tcg_gen_st_tl(tmp, tcg_env, offsetof(CPURISCVState, mstatus_hs)); 668 } 669 } 670 } 671 #else 672 static inline void mark_vs_dirty(DisasContext *ctx) { } 673 #endif 674 675 static void finalize_rvv_inst(DisasContext *ctx) 676 { 677 mark_vs_dirty(ctx); 678 ctx->vstart_eq_zero = true; 679 } 680 681 static void gen_set_rm(DisasContext *ctx, int rm) 682 { 683 if (ctx->frm == rm) { 684 return; 685 } 686 ctx->frm = rm; 687 688 if (rm == RISCV_FRM_DYN) { 689 /* The helper will return only if frm valid. */ 690 ctx->frm_valid = true; 691 } 692 693 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 694 decode_save_opc(ctx); 695 gen_helper_set_rounding_mode(tcg_env, tcg_constant_i32(rm)); 696 } 697 698 static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) 699 { 700 if (ctx->frm == rm && ctx->frm_valid) { 701 return; 702 } 703 ctx->frm = rm; 704 ctx->frm_valid = true; 705 706 /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ 707 decode_save_opc(ctx); 708 gen_helper_set_rounding_mode_chkfrm(tcg_env, tcg_constant_i32(rm)); 709 } 710 711 static int ex_plus_1(DisasContext *ctx, int nf) 712 { 713 return nf + 1; 714 } 715 716 #define EX_SH(amount) \ 717 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 718 { \ 719 return imm << amount; \ 720 } 721 EX_SH(1) 722 EX_SH(2) 723 EX_SH(3) 724 EX_SH(4) 725 EX_SH(12) 726 727 #define REQUIRE_EXT(ctx, ext) do { \ 728 if (!has_ext(ctx, ext)) { \ 729 return false; \ 730 } \ 731 } while (0) 732 733 #define REQUIRE_32BIT(ctx) do { \ 734 if (get_xl(ctx) != MXL_RV32) { \ 735 return false; \ 736 } \ 737 } while (0) 738 739 #define REQUIRE_64BIT(ctx) do { \ 740 if (get_xl(ctx) != MXL_RV64) { \ 741 return false; \ 742 } \ 743 } while (0) 744 745 #define REQUIRE_128BIT(ctx) do { \ 746 if (get_xl(ctx) != MXL_RV128) { \ 747 return false; \ 748 } \ 749 } while (0) 750 751 #define REQUIRE_64_OR_128BIT(ctx) do { \ 752 if (get_xl(ctx) == MXL_RV32) { \ 753 return false; \ 754 } \ 755 } while (0) 756 757 #define REQUIRE_EITHER_EXT(ctx, A, B) do { \ 758 if (!ctx->cfg_ptr->ext_##A && \ 759 !ctx->cfg_ptr->ext_##B) { \ 760 return false; \ 761 } \ 762 } while (0) 763 764 static int ex_rvc_register(DisasContext *ctx, int reg) 765 { 766 return 8 + reg; 767 } 768 769 static int ex_sreg_register(DisasContext *ctx, int reg) 770 { 771 return reg < 2 ? reg + 8 : reg + 16; 772 } 773 774 static int ex_rvc_shiftli(DisasContext *ctx, int imm) 775 { 776 /* For RV128 a shamt of 0 means a shift by 64. */ 777 if (get_ol(ctx) == MXL_RV128) { 778 imm = imm ? imm : 64; 779 } 780 return imm; 781 } 782 783 static int ex_rvc_shiftri(DisasContext *ctx, int imm) 784 { 785 /* 786 * For RV128 a shamt of 0 means a shift by 64, furthermore, for right 787 * shifts, the shamt is sign-extended. 788 */ 789 if (get_ol(ctx) == MXL_RV128) { 790 imm = imm | (imm & 32) << 1; 791 imm = imm ? imm : 64; 792 } 793 return imm; 794 } 795 796 /* Include the auto-generated decoder for 32 bit insn */ 797 #include "decode-insn32.c.inc" 798 799 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 800 void (*func)(TCGv, TCGv, target_long)) 801 { 802 TCGv dest = dest_gpr(ctx, a->rd); 803 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 804 805 func(dest, src1, a->imm); 806 807 if (get_xl(ctx) == MXL_RV128) { 808 TCGv src1h = get_gprh(ctx, a->rs1); 809 TCGv desth = dest_gprh(ctx, a->rd); 810 811 func(desth, src1h, -(a->imm < 0)); 812 gen_set_gpr128(ctx, a->rd, dest, desth); 813 } else { 814 gen_set_gpr(ctx, a->rd, dest); 815 } 816 817 return true; 818 } 819 820 static bool gen_logic(DisasContext *ctx, arg_r *a, 821 void (*func)(TCGv, TCGv, TCGv)) 822 { 823 TCGv dest = dest_gpr(ctx, a->rd); 824 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 825 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 826 827 func(dest, src1, src2); 828 829 if (get_xl(ctx) == MXL_RV128) { 830 TCGv src1h = get_gprh(ctx, a->rs1); 831 TCGv src2h = get_gprh(ctx, a->rs2); 832 TCGv desth = dest_gprh(ctx, a->rd); 833 834 func(desth, src1h, src2h); 835 gen_set_gpr128(ctx, a->rd, dest, desth); 836 } else { 837 gen_set_gpr(ctx, a->rd, dest); 838 } 839 840 return true; 841 } 842 843 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 844 void (*func)(TCGv, TCGv, target_long), 845 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 846 { 847 TCGv dest = dest_gpr(ctx, a->rd); 848 TCGv src1 = get_gpr(ctx, a->rs1, ext); 849 850 if (get_ol(ctx) < MXL_RV128) { 851 func(dest, src1, a->imm); 852 gen_set_gpr(ctx, a->rd, dest); 853 } else { 854 if (f128 == NULL) { 855 return false; 856 } 857 858 TCGv src1h = get_gprh(ctx, a->rs1); 859 TCGv desth = dest_gprh(ctx, a->rd); 860 861 f128(dest, desth, src1, src1h, a->imm); 862 gen_set_gpr128(ctx, a->rd, dest, desth); 863 } 864 return true; 865 } 866 867 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 868 void (*func)(TCGv, TCGv, TCGv), 869 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 870 { 871 TCGv dest = dest_gpr(ctx, a->rd); 872 TCGv src1 = get_gpr(ctx, a->rs1, ext); 873 TCGv src2 = tcg_constant_tl(a->imm); 874 875 if (get_ol(ctx) < MXL_RV128) { 876 func(dest, src1, src2); 877 gen_set_gpr(ctx, a->rd, dest); 878 } else { 879 if (f128 == NULL) { 880 return false; 881 } 882 883 TCGv src1h = get_gprh(ctx, a->rs1); 884 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 885 TCGv desth = dest_gprh(ctx, a->rd); 886 887 f128(dest, desth, src1, src1h, src2, src2h); 888 gen_set_gpr128(ctx, a->rd, dest, desth); 889 } 890 return true; 891 } 892 893 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 894 void (*func)(TCGv, TCGv, TCGv), 895 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 896 { 897 TCGv dest = dest_gpr(ctx, a->rd); 898 TCGv src1 = get_gpr(ctx, a->rs1, ext); 899 TCGv src2 = get_gpr(ctx, a->rs2, ext); 900 901 if (get_ol(ctx) < MXL_RV128) { 902 func(dest, src1, src2); 903 gen_set_gpr(ctx, a->rd, dest); 904 } else { 905 if (f128 == NULL) { 906 return false; 907 } 908 909 TCGv src1h = get_gprh(ctx, a->rs1); 910 TCGv src2h = get_gprh(ctx, a->rs2); 911 TCGv desth = dest_gprh(ctx, a->rd); 912 913 f128(dest, desth, src1, src1h, src2, src2h); 914 gen_set_gpr128(ctx, a->rd, dest, desth); 915 } 916 return true; 917 } 918 919 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 920 void (*f_tl)(TCGv, TCGv, TCGv), 921 void (*f_32)(TCGv, TCGv, TCGv), 922 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 923 { 924 int olen = get_olen(ctx); 925 926 if (olen != TARGET_LONG_BITS) { 927 if (olen == 32) { 928 f_tl = f_32; 929 } else if (olen != 128) { 930 g_assert_not_reached(); 931 } 932 } 933 return gen_arith(ctx, a, ext, f_tl, f_128); 934 } 935 936 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 937 void (*func)(TCGv, TCGv, target_long), 938 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 939 { 940 TCGv dest, src1; 941 int max_len = get_olen(ctx); 942 943 if (a->shamt >= max_len) { 944 return false; 945 } 946 947 dest = dest_gpr(ctx, a->rd); 948 src1 = get_gpr(ctx, a->rs1, ext); 949 950 if (max_len < 128) { 951 func(dest, src1, a->shamt); 952 gen_set_gpr(ctx, a->rd, dest); 953 } else { 954 TCGv src1h = get_gprh(ctx, a->rs1); 955 TCGv desth = dest_gprh(ctx, a->rd); 956 957 if (f128 == NULL) { 958 return false; 959 } 960 f128(dest, desth, src1, src1h, a->shamt); 961 gen_set_gpr128(ctx, a->rd, dest, desth); 962 } 963 return true; 964 } 965 966 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 967 DisasExtend ext, 968 void (*f_tl)(TCGv, TCGv, target_long), 969 void (*f_32)(TCGv, TCGv, target_long), 970 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 971 target_long)) 972 { 973 int olen = get_olen(ctx); 974 if (olen != TARGET_LONG_BITS) { 975 if (olen == 32) { 976 f_tl = f_32; 977 } else if (olen != 128) { 978 g_assert_not_reached(); 979 } 980 } 981 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 982 } 983 984 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 985 void (*func)(TCGv, TCGv, TCGv)) 986 { 987 TCGv dest, src1, src2; 988 int max_len = get_olen(ctx); 989 990 if (a->shamt >= max_len) { 991 return false; 992 } 993 994 dest = dest_gpr(ctx, a->rd); 995 src1 = get_gpr(ctx, a->rs1, ext); 996 src2 = tcg_constant_tl(a->shamt); 997 998 func(dest, src1, src2); 999 1000 gen_set_gpr(ctx, a->rd, dest); 1001 return true; 1002 } 1003 1004 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 1005 void (*func)(TCGv, TCGv, TCGv), 1006 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1007 { 1008 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 1009 TCGv ext2 = tcg_temp_new(); 1010 int max_len = get_olen(ctx); 1011 1012 tcg_gen_andi_tl(ext2, src2, max_len - 1); 1013 1014 TCGv dest = dest_gpr(ctx, a->rd); 1015 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1016 1017 if (max_len < 128) { 1018 func(dest, src1, ext2); 1019 gen_set_gpr(ctx, a->rd, dest); 1020 } else { 1021 TCGv src1h = get_gprh(ctx, a->rs1); 1022 TCGv desth = dest_gprh(ctx, a->rd); 1023 1024 if (f128 == NULL) { 1025 return false; 1026 } 1027 f128(dest, desth, src1, src1h, ext2); 1028 gen_set_gpr128(ctx, a->rd, dest, desth); 1029 } 1030 return true; 1031 } 1032 1033 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 1034 void (*f_tl)(TCGv, TCGv, TCGv), 1035 void (*f_32)(TCGv, TCGv, TCGv), 1036 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 1037 { 1038 int olen = get_olen(ctx); 1039 if (olen != TARGET_LONG_BITS) { 1040 if (olen == 32) { 1041 f_tl = f_32; 1042 } else if (olen != 128) { 1043 g_assert_not_reached(); 1044 } 1045 } 1046 return gen_shift(ctx, a, ext, f_tl, f_128); 1047 } 1048 1049 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1050 void (*func)(TCGv, TCGv)) 1051 { 1052 TCGv dest = dest_gpr(ctx, a->rd); 1053 TCGv src1 = get_gpr(ctx, a->rs1, ext); 1054 1055 func(dest, src1); 1056 1057 gen_set_gpr(ctx, a->rd, dest); 1058 return true; 1059 } 1060 1061 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 1062 void (*f_tl)(TCGv, TCGv), 1063 void (*f_32)(TCGv, TCGv)) 1064 { 1065 int olen = get_olen(ctx); 1066 1067 if (olen != TARGET_LONG_BITS) { 1068 if (olen == 32) { 1069 f_tl = f_32; 1070 } else { 1071 g_assert_not_reached(); 1072 } 1073 } 1074 return gen_unary(ctx, a, ext, f_tl); 1075 } 1076 1077 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 1078 { 1079 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1080 CPUState *cpu = ctx->cs; 1081 CPURISCVState *env = cpu_env(cpu); 1082 1083 return translator_ldl(env, &ctx->base, pc); 1084 } 1085 1086 /* Include insn module translation function */ 1087 #include "insn_trans/trans_rvi.c.inc" 1088 #include "insn_trans/trans_rvm.c.inc" 1089 #include "insn_trans/trans_rva.c.inc" 1090 #include "insn_trans/trans_rvf.c.inc" 1091 #include "insn_trans/trans_rvd.c.inc" 1092 #include "insn_trans/trans_rvh.c.inc" 1093 #include "insn_trans/trans_rvv.c.inc" 1094 #include "insn_trans/trans_rvb.c.inc" 1095 #include "insn_trans/trans_rvzicond.c.inc" 1096 #include "insn_trans/trans_rvzacas.c.inc" 1097 #include "insn_trans/trans_rvzawrs.c.inc" 1098 #include "insn_trans/trans_rvzicbo.c.inc" 1099 #include "insn_trans/trans_rvzfa.c.inc" 1100 #include "insn_trans/trans_rvzfh.c.inc" 1101 #include "insn_trans/trans_rvk.c.inc" 1102 #include "insn_trans/trans_rvvk.c.inc" 1103 #include "insn_trans/trans_privileged.c.inc" 1104 #include "insn_trans/trans_svinval.c.inc" 1105 #include "insn_trans/trans_rvbf16.c.inc" 1106 #include "decode-xthead.c.inc" 1107 #include "insn_trans/trans_xthead.c.inc" 1108 #include "insn_trans/trans_xventanacondops.c.inc" 1109 1110 /* Include the auto-generated decoder for 16 bit insn */ 1111 #include "decode-insn16.c.inc" 1112 #include "insn_trans/trans_rvzce.c.inc" 1113 1114 /* Include decoders for factored-out extensions */ 1115 #include "decode-XVentanaCondOps.c.inc" 1116 1117 /* The specification allows for longer insns, but not supported by qemu. */ 1118 #define MAX_INSN_LEN 4 1119 1120 static inline int insn_len(uint16_t first_word) 1121 { 1122 return (first_word & 3) == 3 ? 4 : 2; 1123 } 1124 1125 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 1126 { 1127 /* 1128 * A table with predicate (i.e., guard) functions and decoder functions 1129 * that are tested in-order until a decoder matches onto the opcode. 1130 */ 1131 static const struct { 1132 bool (*guard_func)(const RISCVCPUConfig *); 1133 bool (*decode_func)(DisasContext *, uint32_t); 1134 } decoders[] = { 1135 { always_true_p, decode_insn32 }, 1136 { has_xthead_p, decode_xthead }, 1137 { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, 1138 }; 1139 1140 ctx->virt_inst_excp = false; 1141 ctx->cur_insn_len = insn_len(opcode); 1142 /* Check for compressed insn */ 1143 if (ctx->cur_insn_len == 2) { 1144 ctx->opcode = opcode; 1145 /* 1146 * The Zca extension is added as way to refer to instructions in the C 1147 * extension that do not include the floating-point loads and stores 1148 */ 1149 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && 1150 decode_insn16(ctx, opcode)) { 1151 return; 1152 } 1153 } else { 1154 uint32_t opcode32 = opcode; 1155 opcode32 = deposit32(opcode32, 16, 16, 1156 translator_lduw(env, &ctx->base, 1157 ctx->base.pc_next + 2)); 1158 ctx->opcode = opcode32; 1159 1160 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 1161 if (decoders[i].guard_func(ctx->cfg_ptr) && 1162 decoders[i].decode_func(ctx, opcode32)) { 1163 return; 1164 } 1165 } 1166 } 1167 1168 gen_exception_illegal(ctx); 1169 } 1170 1171 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 1172 { 1173 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1174 CPURISCVState *env = cpu_env(cs); 1175 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs); 1176 RISCVCPU *cpu = RISCV_CPU(cs); 1177 uint32_t tb_flags = ctx->base.tb->flags; 1178 1179 ctx->pc_save = ctx->base.pc_first; 1180 ctx->priv = FIELD_EX32(tb_flags, TB_FLAGS, PRIV); 1181 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 1182 ctx->mstatus_fs = FIELD_EX32(tb_flags, TB_FLAGS, FS); 1183 ctx->mstatus_vs = FIELD_EX32(tb_flags, TB_FLAGS, VS); 1184 ctx->priv_ver = env->priv_ver; 1185 ctx->virt_enabled = FIELD_EX32(tb_flags, TB_FLAGS, VIRT_ENABLED); 1186 ctx->misa_ext = env->misa_ext; 1187 ctx->frm = -1; /* unknown rounding mode */ 1188 ctx->cfg_ptr = &(cpu->cfg); 1189 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 1190 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 1191 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 1192 ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; 1193 ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; 1194 ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; 1195 ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); 1196 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 1197 ctx->misa_mxl_max = mcc->misa_mxl_max; 1198 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 1199 ctx->address_xl = FIELD_EX32(tb_flags, TB_FLAGS, AXL); 1200 ctx->cs = cs; 1201 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 1202 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 1203 ctx->ztso = cpu->cfg.ext_ztso; 1204 ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); 1205 ctx->zero = tcg_constant_tl(0); 1206 ctx->virt_inst_excp = false; 1207 } 1208 1209 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 1210 { 1211 } 1212 1213 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 1214 { 1215 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1216 target_ulong pc_next = ctx->base.pc_next; 1217 1218 if (tb_cflags(dcbase->tb) & CF_PCREL) { 1219 pc_next &= ~TARGET_PAGE_MASK; 1220 } 1221 1222 tcg_gen_insn_start(pc_next, 0); 1223 ctx->insn_start_updated = false; 1224 } 1225 1226 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 1227 { 1228 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1229 CPURISCVState *env = cpu_env(cpu); 1230 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 1231 1232 ctx->ol = ctx->xl; 1233 decode_opc(env, ctx, opcode16); 1234 ctx->base.pc_next += ctx->cur_insn_len; 1235 1236 /* Only the first insn within a TB is allowed to cross a page boundary. */ 1237 if (ctx->base.is_jmp == DISAS_NEXT) { 1238 if (ctx->itrigger || !is_same_page(&ctx->base, ctx->base.pc_next)) { 1239 ctx->base.is_jmp = DISAS_TOO_MANY; 1240 } else { 1241 unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK; 1242 1243 if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) { 1244 uint16_t next_insn = 1245 translator_lduw(env, &ctx->base, ctx->base.pc_next); 1246 int len = insn_len(next_insn); 1247 1248 if (!is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) { 1249 ctx->base.is_jmp = DISAS_TOO_MANY; 1250 } 1251 } 1252 } 1253 } 1254 } 1255 1256 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 1257 { 1258 DisasContext *ctx = container_of(dcbase, DisasContext, base); 1259 1260 switch (ctx->base.is_jmp) { 1261 case DISAS_TOO_MANY: 1262 gen_goto_tb(ctx, 0, 0); 1263 break; 1264 case DISAS_NORETURN: 1265 break; 1266 default: 1267 g_assert_not_reached(); 1268 } 1269 } 1270 1271 static const TranslatorOps riscv_tr_ops = { 1272 .init_disas_context = riscv_tr_init_disas_context, 1273 .tb_start = riscv_tr_tb_start, 1274 .insn_start = riscv_tr_insn_start, 1275 .translate_insn = riscv_tr_translate_insn, 1276 .tb_stop = riscv_tr_tb_stop, 1277 }; 1278 1279 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, 1280 vaddr pc, void *host_pc) 1281 { 1282 DisasContext ctx; 1283 1284 translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base); 1285 } 1286 1287 void riscv_translate_init(void) 1288 { 1289 int i; 1290 1291 /* 1292 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1293 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1294 * unless you specifically block reads/writes to reg 0. 1295 */ 1296 cpu_gpr[0] = NULL; 1297 cpu_gprh[0] = NULL; 1298 1299 for (i = 1; i < 32; i++) { 1300 cpu_gpr[i] = tcg_global_mem_new(tcg_env, 1301 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1302 cpu_gprh[i] = tcg_global_mem_new(tcg_env, 1303 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1304 } 1305 1306 for (i = 0; i < 32; i++) { 1307 cpu_fpr[i] = tcg_global_mem_new_i64(tcg_env, 1308 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1309 } 1310 1311 cpu_pc = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, pc), "pc"); 1312 cpu_vl = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vl), "vl"); 1313 cpu_vstart = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, vstart), 1314 "vstart"); 1315 load_res = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_res), 1316 "load_res"); 1317 load_val = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, load_val), 1318 "load_val"); 1319 /* Assign PM CSRs to tcg globals */ 1320 pm_mask = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmmask), 1321 "pmmask"); 1322 pm_base = tcg_global_mem_new(tcg_env, offsetof(CPURISCVState, cur_pmbase), 1323 "pmbase"); 1324 } 1325