1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 const RISCVCPUConfig *cfg_ptr; 80 bool hlsx; 81 /* vector extension */ 82 bool vill; 83 /* 84 * Encode LMUL to lmul as follows: 85 * LMUL vlmul lmul 86 * 1 000 0 87 * 2 001 1 88 * 4 010 2 89 * 8 011 3 90 * - 100 - 91 * 1/8 101 -3 92 * 1/4 110 -2 93 * 1/2 111 -1 94 */ 95 int8_t lmul; 96 uint8_t sew; 97 target_ulong vstart; 98 bool vl_eq_vlmax; 99 uint8_t ntemp; 100 CPUState *cs; 101 TCGv zero; 102 /* Space for 3 operands plus 1 extra for address computation. */ 103 TCGv temp[4]; 104 /* PointerMasking extension */ 105 bool pm_mask_enabled; 106 bool pm_base_enabled; 107 } DisasContext; 108 109 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 110 { 111 return ctx->misa_ext & ext; 112 } 113 114 static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) 115 { 116 return true; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 195 { 196 if (get_xl(ctx) == MXL_RV32) { 197 dest = (int32_t)dest; 198 } 199 tcg_gen_movi_tl(cpu_pc, dest); 200 } 201 202 static void gen_set_pc(DisasContext *ctx, TCGv dest) 203 { 204 if (get_xl(ctx) == MXL_RV32) { 205 tcg_gen_ext32s_tl(cpu_pc, dest); 206 } else { 207 tcg_gen_mov_tl(cpu_pc, dest); 208 } 209 } 210 211 static void generate_exception(DisasContext *ctx, int excp) 212 { 213 gen_set_pc_imm(ctx, ctx->base.pc_next); 214 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 215 ctx->base.is_jmp = DISAS_NORETURN; 216 } 217 218 static void generate_exception_mtval(DisasContext *ctx, int excp) 219 { 220 gen_set_pc_imm(ctx, ctx->base.pc_next); 221 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 222 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 223 ctx->base.is_jmp = DISAS_NORETURN; 224 } 225 226 static void gen_exception_illegal(DisasContext *ctx) 227 { 228 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 229 offsetof(CPURISCVState, bins)); 230 231 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 232 } 233 234 static void gen_exception_inst_addr_mis(DisasContext *ctx) 235 { 236 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 237 } 238 239 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 240 { 241 if (translator_use_goto_tb(&ctx->base, dest)) { 242 tcg_gen_goto_tb(n); 243 gen_set_pc_imm(ctx, dest); 244 tcg_gen_exit_tb(ctx->base.tb, n); 245 } else { 246 gen_set_pc_imm(ctx, dest); 247 tcg_gen_lookup_and_goto_ptr(); 248 } 249 } 250 251 /* 252 * Wrappers for getting reg values. 253 * 254 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 255 * constant zero as a source, and an uninitialized sink as destination. 256 * 257 * Further, we may provide an extension for word operations. 258 */ 259 static TCGv temp_new(DisasContext *ctx) 260 { 261 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 262 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 263 } 264 265 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 266 { 267 TCGv t; 268 269 if (reg_num == 0) { 270 return ctx->zero; 271 } 272 273 switch (get_ol(ctx)) { 274 case MXL_RV32: 275 switch (ext) { 276 case EXT_NONE: 277 break; 278 case EXT_SIGN: 279 t = temp_new(ctx); 280 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 281 return t; 282 case EXT_ZERO: 283 t = temp_new(ctx); 284 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 285 return t; 286 default: 287 g_assert_not_reached(); 288 } 289 break; 290 case MXL_RV64: 291 case MXL_RV128: 292 break; 293 default: 294 g_assert_not_reached(); 295 } 296 return cpu_gpr[reg_num]; 297 } 298 299 static TCGv get_gprh(DisasContext *ctx, int reg_num) 300 { 301 assert(get_xl(ctx) == MXL_RV128); 302 if (reg_num == 0) { 303 return ctx->zero; 304 } 305 return cpu_gprh[reg_num]; 306 } 307 308 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 309 { 310 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 311 return temp_new(ctx); 312 } 313 return cpu_gpr[reg_num]; 314 } 315 316 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 317 { 318 if (reg_num == 0) { 319 return temp_new(ctx); 320 } 321 return cpu_gprh[reg_num]; 322 } 323 324 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 325 { 326 if (reg_num != 0) { 327 switch (get_ol(ctx)) { 328 case MXL_RV32: 329 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 330 break; 331 case MXL_RV64: 332 case MXL_RV128: 333 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 334 break; 335 default: 336 g_assert_not_reached(); 337 } 338 339 if (get_xl_max(ctx) == MXL_RV128) { 340 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 341 } 342 } 343 } 344 345 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 346 { 347 if (reg_num != 0) { 348 switch (get_ol(ctx)) { 349 case MXL_RV32: 350 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 351 break; 352 case MXL_RV64: 353 case MXL_RV128: 354 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 360 if (get_xl_max(ctx) == MXL_RV128) { 361 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 362 } 363 } 364 } 365 366 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 367 { 368 assert(get_ol(ctx) == MXL_RV128); 369 if (reg_num != 0) { 370 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 371 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 372 } 373 } 374 375 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 376 { 377 target_ulong next_pc; 378 379 /* check misaligned: */ 380 next_pc = ctx->base.pc_next + imm; 381 if (!has_ext(ctx, RVC)) { 382 if ((next_pc & 0x3) != 0) { 383 gen_exception_inst_addr_mis(ctx); 384 return; 385 } 386 } 387 388 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 389 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 390 ctx->base.is_jmp = DISAS_NORETURN; 391 } 392 393 /* Compute a canonical address from a register plus offset. */ 394 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 395 { 396 TCGv addr = temp_new(ctx); 397 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 398 399 tcg_gen_addi_tl(addr, src1, imm); 400 if (ctx->pm_mask_enabled) { 401 tcg_gen_and_tl(addr, addr, pm_mask); 402 } else if (get_xl(ctx) == MXL_RV32) { 403 tcg_gen_ext32u_tl(addr, addr); 404 } 405 if (ctx->pm_base_enabled) { 406 tcg_gen_or_tl(addr, addr, pm_base); 407 } 408 return addr; 409 } 410 411 #ifndef CONFIG_USER_ONLY 412 /* The states of mstatus_fs are: 413 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 414 * We will have already diagnosed disabled state, 415 * and need to turn initial/clean into dirty. 416 */ 417 static void mark_fs_dirty(DisasContext *ctx) 418 { 419 TCGv tmp; 420 421 if (ctx->mstatus_fs != MSTATUS_FS) { 422 /* Remember the state change for the rest of the TB. */ 423 ctx->mstatus_fs = MSTATUS_FS; 424 425 tmp = tcg_temp_new(); 426 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 427 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 428 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 429 tcg_temp_free(tmp); 430 } 431 432 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 433 /* Remember the stage change for the rest of the TB. */ 434 ctx->mstatus_hs_fs = MSTATUS_FS; 435 436 tmp = tcg_temp_new(); 437 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 438 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 439 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 440 tcg_temp_free(tmp); 441 } 442 } 443 #else 444 static inline void mark_fs_dirty(DisasContext *ctx) { } 445 #endif 446 447 #ifndef CONFIG_USER_ONLY 448 /* The states of mstatus_vs are: 449 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 450 * We will have already diagnosed disabled state, 451 * and need to turn initial/clean into dirty. 452 */ 453 static void mark_vs_dirty(DisasContext *ctx) 454 { 455 TCGv tmp; 456 457 if (ctx->mstatus_vs != MSTATUS_VS) { 458 /* Remember the state change for the rest of the TB. */ 459 ctx->mstatus_vs = MSTATUS_VS; 460 461 tmp = tcg_temp_new(); 462 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 463 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 464 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 465 tcg_temp_free(tmp); 466 } 467 468 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 469 /* Remember the stage change for the rest of the TB. */ 470 ctx->mstatus_hs_vs = MSTATUS_VS; 471 472 tmp = tcg_temp_new(); 473 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 474 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 475 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 476 tcg_temp_free(tmp); 477 } 478 } 479 #else 480 static inline void mark_vs_dirty(DisasContext *ctx) { } 481 #endif 482 483 static void gen_set_rm(DisasContext *ctx, int rm) 484 { 485 if (ctx->frm == rm) { 486 return; 487 } 488 ctx->frm = rm; 489 490 if (rm == RISCV_FRM_ROD) { 491 gen_helper_set_rod_rounding_mode(cpu_env); 492 return; 493 } 494 495 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 496 } 497 498 static int ex_plus_1(DisasContext *ctx, int nf) 499 { 500 return nf + 1; 501 } 502 503 #define EX_SH(amount) \ 504 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 505 { \ 506 return imm << amount; \ 507 } 508 EX_SH(1) 509 EX_SH(2) 510 EX_SH(3) 511 EX_SH(4) 512 EX_SH(12) 513 514 #define REQUIRE_EXT(ctx, ext) do { \ 515 if (!has_ext(ctx, ext)) { \ 516 return false; \ 517 } \ 518 } while (0) 519 520 #define REQUIRE_32BIT(ctx) do { \ 521 if (get_xl(ctx) != MXL_RV32) { \ 522 return false; \ 523 } \ 524 } while (0) 525 526 #define REQUIRE_64BIT(ctx) do { \ 527 if (get_xl(ctx) != MXL_RV64) { \ 528 return false; \ 529 } \ 530 } while (0) 531 532 #define REQUIRE_128BIT(ctx) do { \ 533 if (get_xl(ctx) != MXL_RV128) { \ 534 return false; \ 535 } \ 536 } while (0) 537 538 #define REQUIRE_64_OR_128BIT(ctx) do { \ 539 if (get_xl(ctx) == MXL_RV32) { \ 540 return false; \ 541 } \ 542 } while (0) 543 544 static int ex_rvc_register(DisasContext *ctx, int reg) 545 { 546 return 8 + reg; 547 } 548 549 static int ex_rvc_shifti(DisasContext *ctx, int imm) 550 { 551 /* For RV128 a shamt of 0 means a shift by 64. */ 552 return imm ? imm : 64; 553 } 554 555 /* Include the auto-generated decoder for 32 bit insn */ 556 #include "decode-insn32.c.inc" 557 558 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 559 void (*func)(TCGv, TCGv, target_long)) 560 { 561 TCGv dest = dest_gpr(ctx, a->rd); 562 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 563 564 func(dest, src1, a->imm); 565 566 if (get_xl(ctx) == MXL_RV128) { 567 TCGv src1h = get_gprh(ctx, a->rs1); 568 TCGv desth = dest_gprh(ctx, a->rd); 569 570 func(desth, src1h, -(a->imm < 0)); 571 gen_set_gpr128(ctx, a->rd, dest, desth); 572 } else { 573 gen_set_gpr(ctx, a->rd, dest); 574 } 575 576 return true; 577 } 578 579 static bool gen_logic(DisasContext *ctx, arg_r *a, 580 void (*func)(TCGv, TCGv, TCGv)) 581 { 582 TCGv dest = dest_gpr(ctx, a->rd); 583 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 584 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 585 586 func(dest, src1, src2); 587 588 if (get_xl(ctx) == MXL_RV128) { 589 TCGv src1h = get_gprh(ctx, a->rs1); 590 TCGv src2h = get_gprh(ctx, a->rs2); 591 TCGv desth = dest_gprh(ctx, a->rd); 592 593 func(desth, src1h, src2h); 594 gen_set_gpr128(ctx, a->rd, dest, desth); 595 } else { 596 gen_set_gpr(ctx, a->rd, dest); 597 } 598 599 return true; 600 } 601 602 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 603 void (*func)(TCGv, TCGv, target_long), 604 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 605 { 606 TCGv dest = dest_gpr(ctx, a->rd); 607 TCGv src1 = get_gpr(ctx, a->rs1, ext); 608 609 if (get_ol(ctx) < MXL_RV128) { 610 func(dest, src1, a->imm); 611 gen_set_gpr(ctx, a->rd, dest); 612 } else { 613 if (f128 == NULL) { 614 return false; 615 } 616 617 TCGv src1h = get_gprh(ctx, a->rs1); 618 TCGv desth = dest_gprh(ctx, a->rd); 619 620 f128(dest, desth, src1, src1h, a->imm); 621 gen_set_gpr128(ctx, a->rd, dest, desth); 622 } 623 return true; 624 } 625 626 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 627 void (*func)(TCGv, TCGv, TCGv), 628 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 629 { 630 TCGv dest = dest_gpr(ctx, a->rd); 631 TCGv src1 = get_gpr(ctx, a->rs1, ext); 632 TCGv src2 = tcg_constant_tl(a->imm); 633 634 if (get_ol(ctx) < MXL_RV128) { 635 func(dest, src1, src2); 636 gen_set_gpr(ctx, a->rd, dest); 637 } else { 638 if (f128 == NULL) { 639 return false; 640 } 641 642 TCGv src1h = get_gprh(ctx, a->rs1); 643 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 644 TCGv desth = dest_gprh(ctx, a->rd); 645 646 f128(dest, desth, src1, src1h, src2, src2h); 647 gen_set_gpr128(ctx, a->rd, dest, desth); 648 } 649 return true; 650 } 651 652 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 653 void (*func)(TCGv, TCGv, TCGv), 654 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 655 { 656 TCGv dest = dest_gpr(ctx, a->rd); 657 TCGv src1 = get_gpr(ctx, a->rs1, ext); 658 TCGv src2 = get_gpr(ctx, a->rs2, ext); 659 660 if (get_ol(ctx) < MXL_RV128) { 661 func(dest, src1, src2); 662 gen_set_gpr(ctx, a->rd, dest); 663 } else { 664 if (f128 == NULL) { 665 return false; 666 } 667 668 TCGv src1h = get_gprh(ctx, a->rs1); 669 TCGv src2h = get_gprh(ctx, a->rs2); 670 TCGv desth = dest_gprh(ctx, a->rd); 671 672 f128(dest, desth, src1, src1h, src2, src2h); 673 gen_set_gpr128(ctx, a->rd, dest, desth); 674 } 675 return true; 676 } 677 678 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 679 void (*f_tl)(TCGv, TCGv, TCGv), 680 void (*f_32)(TCGv, TCGv, TCGv), 681 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 682 { 683 int olen = get_olen(ctx); 684 685 if (olen != TARGET_LONG_BITS) { 686 if (olen == 32) { 687 f_tl = f_32; 688 } else if (olen != 128) { 689 g_assert_not_reached(); 690 } 691 } 692 return gen_arith(ctx, a, ext, f_tl, f_128); 693 } 694 695 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 696 void (*func)(TCGv, TCGv, target_long), 697 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 698 { 699 TCGv dest, src1; 700 int max_len = get_olen(ctx); 701 702 if (a->shamt >= max_len) { 703 return false; 704 } 705 706 dest = dest_gpr(ctx, a->rd); 707 src1 = get_gpr(ctx, a->rs1, ext); 708 709 if (max_len < 128) { 710 func(dest, src1, a->shamt); 711 gen_set_gpr(ctx, a->rd, dest); 712 } else { 713 TCGv src1h = get_gprh(ctx, a->rs1); 714 TCGv desth = dest_gprh(ctx, a->rd); 715 716 if (f128 == NULL) { 717 return false; 718 } 719 f128(dest, desth, src1, src1h, a->shamt); 720 gen_set_gpr128(ctx, a->rd, dest, desth); 721 } 722 return true; 723 } 724 725 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 726 DisasExtend ext, 727 void (*f_tl)(TCGv, TCGv, target_long), 728 void (*f_32)(TCGv, TCGv, target_long), 729 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 730 target_long)) 731 { 732 int olen = get_olen(ctx); 733 if (olen != TARGET_LONG_BITS) { 734 if (olen == 32) { 735 f_tl = f_32; 736 } else if (olen != 128) { 737 g_assert_not_reached(); 738 } 739 } 740 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 741 } 742 743 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 744 void (*func)(TCGv, TCGv, TCGv)) 745 { 746 TCGv dest, src1, src2; 747 int max_len = get_olen(ctx); 748 749 if (a->shamt >= max_len) { 750 return false; 751 } 752 753 dest = dest_gpr(ctx, a->rd); 754 src1 = get_gpr(ctx, a->rs1, ext); 755 src2 = tcg_constant_tl(a->shamt); 756 757 func(dest, src1, src2); 758 759 gen_set_gpr(ctx, a->rd, dest); 760 return true; 761 } 762 763 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 764 void (*func)(TCGv, TCGv, TCGv), 765 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 766 { 767 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 768 TCGv ext2 = tcg_temp_new(); 769 int max_len = get_olen(ctx); 770 771 tcg_gen_andi_tl(ext2, src2, max_len - 1); 772 773 TCGv dest = dest_gpr(ctx, a->rd); 774 TCGv src1 = get_gpr(ctx, a->rs1, ext); 775 776 if (max_len < 128) { 777 func(dest, src1, ext2); 778 gen_set_gpr(ctx, a->rd, dest); 779 } else { 780 TCGv src1h = get_gprh(ctx, a->rs1); 781 TCGv desth = dest_gprh(ctx, a->rd); 782 783 if (f128 == NULL) { 784 return false; 785 } 786 f128(dest, desth, src1, src1h, ext2); 787 gen_set_gpr128(ctx, a->rd, dest, desth); 788 } 789 tcg_temp_free(ext2); 790 return true; 791 } 792 793 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 794 void (*f_tl)(TCGv, TCGv, TCGv), 795 void (*f_32)(TCGv, TCGv, TCGv), 796 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 797 { 798 int olen = get_olen(ctx); 799 if (olen != TARGET_LONG_BITS) { 800 if (olen == 32) { 801 f_tl = f_32; 802 } else if (olen != 128) { 803 g_assert_not_reached(); 804 } 805 } 806 return gen_shift(ctx, a, ext, f_tl, f_128); 807 } 808 809 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 810 void (*func)(TCGv, TCGv)) 811 { 812 TCGv dest = dest_gpr(ctx, a->rd); 813 TCGv src1 = get_gpr(ctx, a->rs1, ext); 814 815 func(dest, src1); 816 817 gen_set_gpr(ctx, a->rd, dest); 818 return true; 819 } 820 821 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 822 void (*f_tl)(TCGv, TCGv), 823 void (*f_32)(TCGv, TCGv)) 824 { 825 int olen = get_olen(ctx); 826 827 if (olen != TARGET_LONG_BITS) { 828 if (olen == 32) { 829 f_tl = f_32; 830 } else { 831 g_assert_not_reached(); 832 } 833 } 834 return gen_unary(ctx, a, ext, f_tl); 835 } 836 837 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 838 { 839 DisasContext *ctx = container_of(dcbase, DisasContext, base); 840 CPUState *cpu = ctx->cs; 841 CPURISCVState *env = cpu->env_ptr; 842 843 return cpu_ldl_code(env, pc); 844 } 845 846 /* Include insn module translation function */ 847 #include "insn_trans/trans_rvi.c.inc" 848 #include "insn_trans/trans_rvm.c.inc" 849 #include "insn_trans/trans_rva.c.inc" 850 #include "insn_trans/trans_rvf.c.inc" 851 #include "insn_trans/trans_rvd.c.inc" 852 #include "insn_trans/trans_rvh.c.inc" 853 #include "insn_trans/trans_rvv.c.inc" 854 #include "insn_trans/trans_rvb.c.inc" 855 #include "insn_trans/trans_rvzfh.c.inc" 856 #include "insn_trans/trans_privileged.c.inc" 857 858 /* Include the auto-generated decoder for 16 bit insn */ 859 #include "decode-insn16.c.inc" 860 861 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 862 { 863 /* 864 * A table with predicate (i.e., guard) functions and decoder functions 865 * that are tested in-order until a decoder matches onto the opcode. 866 */ 867 static const struct { 868 bool (*guard_func)(DisasContext *); 869 bool (*decode_func)(DisasContext *, uint32_t); 870 } decoders[] = { 871 { always_true_p, decode_insn32 }, 872 }; 873 874 /* Check for compressed insn */ 875 if (extract16(opcode, 0, 2) != 3) { 876 if (!has_ext(ctx, RVC)) { 877 gen_exception_illegal(ctx); 878 } else { 879 ctx->opcode = opcode; 880 ctx->pc_succ_insn = ctx->base.pc_next + 2; 881 if (decode_insn16(ctx, opcode)) { 882 return; 883 } 884 } 885 } else { 886 uint32_t opcode32 = opcode; 887 opcode32 = deposit32(opcode32, 16, 16, 888 translator_lduw(env, &ctx->base, 889 ctx->base.pc_next + 2)); 890 ctx->opcode = opcode32; 891 ctx->pc_succ_insn = ctx->base.pc_next + 4; 892 893 for (size_t i = 0; i < ARRAY_SIZE(decoders); ++i) { 894 if (decoders[i].guard_func(ctx) && 895 decoders[i].decode_func(ctx, opcode32)) { 896 return; 897 } 898 } 899 } 900 901 gen_exception_illegal(ctx); 902 } 903 904 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 905 { 906 DisasContext *ctx = container_of(dcbase, DisasContext, base); 907 CPURISCVState *env = cs->env_ptr; 908 RISCVCPU *cpu = RISCV_CPU(cs); 909 uint32_t tb_flags = ctx->base.tb->flags; 910 911 ctx->pc_succ_insn = ctx->base.pc_first; 912 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 913 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 914 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 915 ctx->priv_ver = env->priv_ver; 916 #if !defined(CONFIG_USER_ONLY) 917 if (riscv_has_ext(env, RVH)) { 918 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 919 } else { 920 ctx->virt_enabled = false; 921 } 922 #else 923 ctx->virt_enabled = false; 924 #endif 925 ctx->misa_ext = env->misa_ext; 926 ctx->frm = -1; /* unknown rounding mode */ 927 ctx->cfg_ptr = &(cpu->cfg); 928 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 929 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 930 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 931 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 932 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 933 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 934 ctx->vstart = env->vstart; 935 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 936 ctx->misa_mxl_max = env->misa_mxl_max; 937 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 938 ctx->cs = cs; 939 ctx->ntemp = 0; 940 memset(ctx->temp, 0, sizeof(ctx->temp)); 941 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 942 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 943 ctx->zero = tcg_constant_tl(0); 944 } 945 946 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 947 { 948 } 949 950 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 951 { 952 DisasContext *ctx = container_of(dcbase, DisasContext, base); 953 954 tcg_gen_insn_start(ctx->base.pc_next); 955 } 956 957 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 958 { 959 DisasContext *ctx = container_of(dcbase, DisasContext, base); 960 CPURISCVState *env = cpu->env_ptr; 961 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 962 963 ctx->ol = ctx->xl; 964 decode_opc(env, ctx, opcode16); 965 ctx->base.pc_next = ctx->pc_succ_insn; 966 967 for (int i = ctx->ntemp - 1; i >= 0; --i) { 968 tcg_temp_free(ctx->temp[i]); 969 ctx->temp[i] = NULL; 970 } 971 ctx->ntemp = 0; 972 973 if (ctx->base.is_jmp == DISAS_NEXT) { 974 target_ulong page_start; 975 976 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 977 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 978 ctx->base.is_jmp = DISAS_TOO_MANY; 979 } 980 } 981 } 982 983 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 984 { 985 DisasContext *ctx = container_of(dcbase, DisasContext, base); 986 987 switch (ctx->base.is_jmp) { 988 case DISAS_TOO_MANY: 989 gen_goto_tb(ctx, 0, ctx->base.pc_next); 990 break; 991 case DISAS_NORETURN: 992 break; 993 default: 994 g_assert_not_reached(); 995 } 996 } 997 998 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 999 { 1000 #ifndef CONFIG_USER_ONLY 1001 RISCVCPU *rvcpu = RISCV_CPU(cpu); 1002 CPURISCVState *env = &rvcpu->env; 1003 #endif 1004 1005 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 1006 #ifndef CONFIG_USER_ONLY 1007 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 1008 #endif 1009 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1010 } 1011 1012 static const TranslatorOps riscv_tr_ops = { 1013 .init_disas_context = riscv_tr_init_disas_context, 1014 .tb_start = riscv_tr_tb_start, 1015 .insn_start = riscv_tr_insn_start, 1016 .translate_insn = riscv_tr_translate_insn, 1017 .tb_stop = riscv_tr_tb_stop, 1018 .disas_log = riscv_tr_disas_log, 1019 }; 1020 1021 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1022 { 1023 DisasContext ctx; 1024 1025 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1026 } 1027 1028 void riscv_translate_init(void) 1029 { 1030 int i; 1031 1032 /* 1033 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1034 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1035 * unless you specifically block reads/writes to reg 0. 1036 */ 1037 cpu_gpr[0] = NULL; 1038 cpu_gprh[0] = NULL; 1039 1040 for (i = 1; i < 32; i++) { 1041 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1042 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1043 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1044 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1045 } 1046 1047 for (i = 0; i < 32; i++) { 1048 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1049 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1050 } 1051 1052 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1053 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1054 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1055 "vstart"); 1056 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1057 "load_res"); 1058 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1059 "load_val"); 1060 /* Assign PM CSRs to tcg globals */ 1061 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1062 "pmmask"); 1063 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1064 "pmbase"); 1065 } 1066