1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint16_t vlen; 100 uint16_t elen; 101 target_ulong vstart; 102 bool vl_eq_vlmax; 103 uint8_t ntemp; 104 CPUState *cs; 105 TCGv zero; 106 /* Space for 3 operands plus 1 extra for address computation. */ 107 TCGv temp[4]; 108 /* PointerMasking extension */ 109 bool pm_enabled; 110 TCGv pm_mask; 111 TCGv pm_base; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void generate_exception(DisasContext *ctx, int excp) 195 { 196 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 198 ctx->base.is_jmp = DISAS_NORETURN; 199 } 200 201 static void generate_exception_mtval(DisasContext *ctx, int excp) 202 { 203 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 204 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 205 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 206 ctx->base.is_jmp = DISAS_NORETURN; 207 } 208 209 static void gen_exception_illegal(DisasContext *ctx) 210 { 211 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 212 } 213 214 static void gen_exception_inst_addr_mis(DisasContext *ctx) 215 { 216 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 217 } 218 219 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 220 { 221 if (translator_use_goto_tb(&ctx->base, dest)) { 222 tcg_gen_goto_tb(n); 223 tcg_gen_movi_tl(cpu_pc, dest); 224 tcg_gen_exit_tb(ctx->base.tb, n); 225 } else { 226 tcg_gen_movi_tl(cpu_pc, dest); 227 tcg_gen_lookup_and_goto_ptr(); 228 } 229 } 230 231 /* 232 * Wrappers for getting reg values. 233 * 234 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 235 * constant zero as a source, and an uninitialized sink as destination. 236 * 237 * Further, we may provide an extension for word operations. 238 */ 239 static TCGv temp_new(DisasContext *ctx) 240 { 241 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 242 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 243 } 244 245 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 246 { 247 TCGv t; 248 249 if (reg_num == 0) { 250 return ctx->zero; 251 } 252 253 switch (get_ol(ctx)) { 254 case MXL_RV32: 255 switch (ext) { 256 case EXT_NONE: 257 break; 258 case EXT_SIGN: 259 t = temp_new(ctx); 260 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 261 return t; 262 case EXT_ZERO: 263 t = temp_new(ctx); 264 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 265 return t; 266 default: 267 g_assert_not_reached(); 268 } 269 break; 270 case MXL_RV64: 271 case MXL_RV128: 272 break; 273 default: 274 g_assert_not_reached(); 275 } 276 return cpu_gpr[reg_num]; 277 } 278 279 static TCGv get_gprh(DisasContext *ctx, int reg_num) 280 { 281 assert(get_xl(ctx) == MXL_RV128); 282 if (reg_num == 0) { 283 return ctx->zero; 284 } 285 return cpu_gprh[reg_num]; 286 } 287 288 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 289 { 290 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 291 return temp_new(ctx); 292 } 293 return cpu_gpr[reg_num]; 294 } 295 296 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 297 { 298 if (reg_num == 0) { 299 return temp_new(ctx); 300 } 301 return cpu_gprh[reg_num]; 302 } 303 304 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 305 { 306 if (reg_num != 0) { 307 switch (get_ol(ctx)) { 308 case MXL_RV32: 309 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 310 break; 311 case MXL_RV64: 312 case MXL_RV128: 313 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 314 break; 315 default: 316 g_assert_not_reached(); 317 } 318 319 if (get_xl_max(ctx) == MXL_RV128) { 320 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 321 } 322 } 323 } 324 325 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 326 { 327 if (reg_num != 0) { 328 switch (get_ol(ctx)) { 329 case MXL_RV32: 330 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 331 break; 332 case MXL_RV64: 333 case MXL_RV128: 334 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 335 break; 336 default: 337 g_assert_not_reached(); 338 } 339 340 if (get_xl_max(ctx) == MXL_RV128) { 341 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 342 } 343 } 344 } 345 346 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 347 { 348 assert(get_ol(ctx) == MXL_RV128); 349 if (reg_num != 0) { 350 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 351 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 352 } 353 } 354 355 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 356 { 357 target_ulong next_pc; 358 359 /* check misaligned: */ 360 next_pc = ctx->base.pc_next + imm; 361 if (!has_ext(ctx, RVC)) { 362 if ((next_pc & 0x3) != 0) { 363 gen_exception_inst_addr_mis(ctx); 364 return; 365 } 366 } 367 if (rd != 0) { 368 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 369 } 370 371 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 372 ctx->base.is_jmp = DISAS_NORETURN; 373 } 374 375 /* 376 * Generates address adjustment for PointerMasking 377 */ 378 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 379 { 380 TCGv temp; 381 if (!s->pm_enabled) { 382 /* Load unmodified address */ 383 return src; 384 } else { 385 temp = temp_new(s); 386 tcg_gen_andc_tl(temp, src, s->pm_mask); 387 tcg_gen_or_tl(temp, temp, s->pm_base); 388 return temp; 389 } 390 } 391 392 #ifndef CONFIG_USER_ONLY 393 /* The states of mstatus_fs are: 394 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 395 * We will have already diagnosed disabled state, 396 * and need to turn initial/clean into dirty. 397 */ 398 static void mark_fs_dirty(DisasContext *ctx) 399 { 400 TCGv tmp; 401 402 if (ctx->mstatus_fs != MSTATUS_FS) { 403 /* Remember the state change for the rest of the TB. */ 404 ctx->mstatus_fs = MSTATUS_FS; 405 406 tmp = tcg_temp_new(); 407 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 408 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 409 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 410 tcg_temp_free(tmp); 411 } 412 413 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 414 /* Remember the stage change for the rest of the TB. */ 415 ctx->mstatus_hs_fs = MSTATUS_FS; 416 417 tmp = tcg_temp_new(); 418 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 419 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 420 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 421 tcg_temp_free(tmp); 422 } 423 } 424 #else 425 static inline void mark_fs_dirty(DisasContext *ctx) { } 426 #endif 427 428 #ifndef CONFIG_USER_ONLY 429 /* The states of mstatus_vs are: 430 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 431 * We will have already diagnosed disabled state, 432 * and need to turn initial/clean into dirty. 433 */ 434 static void mark_vs_dirty(DisasContext *ctx) 435 { 436 TCGv tmp; 437 438 if (ctx->mstatus_vs != MSTATUS_VS) { 439 /* Remember the state change for the rest of the TB. */ 440 ctx->mstatus_vs = MSTATUS_VS; 441 442 tmp = tcg_temp_new(); 443 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 444 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 445 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 446 tcg_temp_free(tmp); 447 } 448 449 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 450 /* Remember the stage change for the rest of the TB. */ 451 ctx->mstatus_hs_vs = MSTATUS_VS; 452 453 tmp = tcg_temp_new(); 454 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 455 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 456 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 457 tcg_temp_free(tmp); 458 } 459 } 460 #else 461 static inline void mark_vs_dirty(DisasContext *ctx) { } 462 #endif 463 464 static void gen_set_rm(DisasContext *ctx, int rm) 465 { 466 if (ctx->frm == rm) { 467 return; 468 } 469 ctx->frm = rm; 470 471 if (rm == RISCV_FRM_ROD) { 472 gen_helper_set_rod_rounding_mode(cpu_env); 473 return; 474 } 475 476 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 477 } 478 479 static int ex_plus_1(DisasContext *ctx, int nf) 480 { 481 return nf + 1; 482 } 483 484 #define EX_SH(amount) \ 485 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 486 { \ 487 return imm << amount; \ 488 } 489 EX_SH(1) 490 EX_SH(2) 491 EX_SH(3) 492 EX_SH(4) 493 EX_SH(12) 494 495 #define REQUIRE_EXT(ctx, ext) do { \ 496 if (!has_ext(ctx, ext)) { \ 497 return false; \ 498 } \ 499 } while (0) 500 501 #define REQUIRE_32BIT(ctx) do { \ 502 if (get_xl(ctx) != MXL_RV32) { \ 503 return false; \ 504 } \ 505 } while (0) 506 507 #define REQUIRE_64BIT(ctx) do { \ 508 if (get_xl(ctx) != MXL_RV64) { \ 509 return false; \ 510 } \ 511 } while (0) 512 513 #define REQUIRE_128BIT(ctx) do { \ 514 if (get_xl(ctx) != MXL_RV128) { \ 515 return false; \ 516 } \ 517 } while (0) 518 519 #define REQUIRE_64_OR_128BIT(ctx) do { \ 520 if (get_xl(ctx) == MXL_RV32) { \ 521 return false; \ 522 } \ 523 } while (0) 524 525 static int ex_rvc_register(DisasContext *ctx, int reg) 526 { 527 return 8 + reg; 528 } 529 530 static int ex_rvc_shifti(DisasContext *ctx, int imm) 531 { 532 /* For RV128 a shamt of 0 means a shift by 64. */ 533 return imm ? imm : 64; 534 } 535 536 /* Include the auto-generated decoder for 32 bit insn */ 537 #include "decode-insn32.c.inc" 538 539 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 540 void (*func)(TCGv, TCGv, target_long)) 541 { 542 TCGv dest = dest_gpr(ctx, a->rd); 543 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 544 545 func(dest, src1, a->imm); 546 547 if (get_xl(ctx) == MXL_RV128) { 548 TCGv src1h = get_gprh(ctx, a->rs1); 549 TCGv desth = dest_gprh(ctx, a->rd); 550 551 func(desth, src1h, -(a->imm < 0)); 552 gen_set_gpr128(ctx, a->rd, dest, desth); 553 } else { 554 gen_set_gpr(ctx, a->rd, dest); 555 } 556 557 return true; 558 } 559 560 static bool gen_logic(DisasContext *ctx, arg_r *a, 561 void (*func)(TCGv, TCGv, TCGv)) 562 { 563 TCGv dest = dest_gpr(ctx, a->rd); 564 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 565 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 566 567 func(dest, src1, src2); 568 569 if (get_xl(ctx) == MXL_RV128) { 570 TCGv src1h = get_gprh(ctx, a->rs1); 571 TCGv src2h = get_gprh(ctx, a->rs2); 572 TCGv desth = dest_gprh(ctx, a->rd); 573 574 func(desth, src1h, src2h); 575 gen_set_gpr128(ctx, a->rd, dest, desth); 576 } else { 577 gen_set_gpr(ctx, a->rd, dest); 578 } 579 580 return true; 581 } 582 583 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 584 void (*func)(TCGv, TCGv, target_long)) 585 { 586 TCGv dest = dest_gpr(ctx, a->rd); 587 TCGv src1 = get_gpr(ctx, a->rs1, ext); 588 589 func(dest, src1, a->imm); 590 591 gen_set_gpr(ctx, a->rd, dest); 592 return true; 593 } 594 595 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 596 void (*func)(TCGv, TCGv, TCGv)) 597 { 598 TCGv dest = dest_gpr(ctx, a->rd); 599 TCGv src1 = get_gpr(ctx, a->rs1, ext); 600 TCGv src2 = tcg_constant_tl(a->imm); 601 602 func(dest, src1, src2); 603 604 gen_set_gpr(ctx, a->rd, dest); 605 return true; 606 } 607 608 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 609 void (*func)(TCGv, TCGv, TCGv)) 610 { 611 TCGv dest = dest_gpr(ctx, a->rd); 612 TCGv src1 = get_gpr(ctx, a->rs1, ext); 613 TCGv src2 = get_gpr(ctx, a->rs2, ext); 614 615 func(dest, src1, src2); 616 617 gen_set_gpr(ctx, a->rd, dest); 618 return true; 619 } 620 621 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 622 void (*f_tl)(TCGv, TCGv, TCGv), 623 void (*f_32)(TCGv, TCGv, TCGv)) 624 { 625 int olen = get_olen(ctx); 626 627 if (olen != TARGET_LONG_BITS) { 628 if (olen == 32) { 629 f_tl = f_32; 630 } else { 631 g_assert_not_reached(); 632 } 633 } 634 return gen_arith(ctx, a, ext, f_tl); 635 } 636 637 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 638 void (*func)(TCGv, TCGv, target_long)) 639 { 640 TCGv dest, src1; 641 int max_len = get_olen(ctx); 642 643 if (a->shamt >= max_len) { 644 return false; 645 } 646 647 dest = dest_gpr(ctx, a->rd); 648 src1 = get_gpr(ctx, a->rs1, ext); 649 650 func(dest, src1, a->shamt); 651 652 gen_set_gpr(ctx, a->rd, dest); 653 return true; 654 } 655 656 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 657 DisasExtend ext, 658 void (*f_tl)(TCGv, TCGv, target_long), 659 void (*f_32)(TCGv, TCGv, target_long)) 660 { 661 int olen = get_olen(ctx); 662 if (olen != TARGET_LONG_BITS) { 663 if (olen == 32) { 664 f_tl = f_32; 665 } else { 666 g_assert_not_reached(); 667 } 668 } 669 return gen_shift_imm_fn(ctx, a, ext, f_tl); 670 } 671 672 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 673 void (*func)(TCGv, TCGv, TCGv)) 674 { 675 TCGv dest, src1, src2; 676 int max_len = get_olen(ctx); 677 678 if (a->shamt >= max_len) { 679 return false; 680 } 681 682 dest = dest_gpr(ctx, a->rd); 683 src1 = get_gpr(ctx, a->rs1, ext); 684 src2 = tcg_constant_tl(a->shamt); 685 686 func(dest, src1, src2); 687 688 gen_set_gpr(ctx, a->rd, dest); 689 return true; 690 } 691 692 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 693 void (*func)(TCGv, TCGv, TCGv)) 694 { 695 TCGv dest = dest_gpr(ctx, a->rd); 696 TCGv src1 = get_gpr(ctx, a->rs1, ext); 697 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 698 TCGv ext2 = tcg_temp_new(); 699 700 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 701 func(dest, src1, ext2); 702 703 gen_set_gpr(ctx, a->rd, dest); 704 tcg_temp_free(ext2); 705 return true; 706 } 707 708 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 709 void (*f_tl)(TCGv, TCGv, TCGv), 710 void (*f_32)(TCGv, TCGv, TCGv)) 711 { 712 int olen = get_olen(ctx); 713 if (olen != TARGET_LONG_BITS) { 714 if (olen == 32) { 715 f_tl = f_32; 716 } else { 717 g_assert_not_reached(); 718 } 719 } 720 return gen_shift(ctx, a, ext, f_tl); 721 } 722 723 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 724 void (*func)(TCGv, TCGv)) 725 { 726 TCGv dest = dest_gpr(ctx, a->rd); 727 TCGv src1 = get_gpr(ctx, a->rs1, ext); 728 729 func(dest, src1); 730 731 gen_set_gpr(ctx, a->rd, dest); 732 return true; 733 } 734 735 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 736 void (*f_tl)(TCGv, TCGv), 737 void (*f_32)(TCGv, TCGv)) 738 { 739 int olen = get_olen(ctx); 740 741 if (olen != TARGET_LONG_BITS) { 742 if (olen == 32) { 743 f_tl = f_32; 744 } else { 745 g_assert_not_reached(); 746 } 747 } 748 return gen_unary(ctx, a, ext, f_tl); 749 } 750 751 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 752 { 753 DisasContext *ctx = container_of(dcbase, DisasContext, base); 754 CPUState *cpu = ctx->cs; 755 CPURISCVState *env = cpu->env_ptr; 756 757 return cpu_ldl_code(env, pc); 758 } 759 760 /* Include insn module translation function */ 761 #include "insn_trans/trans_rvi.c.inc" 762 #include "insn_trans/trans_rvm.c.inc" 763 #include "insn_trans/trans_rva.c.inc" 764 #include "insn_trans/trans_rvf.c.inc" 765 #include "insn_trans/trans_rvd.c.inc" 766 #include "insn_trans/trans_rvh.c.inc" 767 #include "insn_trans/trans_rvv.c.inc" 768 #include "insn_trans/trans_rvb.c.inc" 769 #include "insn_trans/trans_rvzfh.c.inc" 770 #include "insn_trans/trans_privileged.c.inc" 771 772 /* Include the auto-generated decoder for 16 bit insn */ 773 #include "decode-insn16.c.inc" 774 775 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 776 { 777 /* check for compressed insn */ 778 if (extract16(opcode, 0, 2) != 3) { 779 if (!has_ext(ctx, RVC)) { 780 gen_exception_illegal(ctx); 781 } else { 782 ctx->pc_succ_insn = ctx->base.pc_next + 2; 783 if (!decode_insn16(ctx, opcode)) { 784 gen_exception_illegal(ctx); 785 } 786 } 787 } else { 788 uint32_t opcode32 = opcode; 789 opcode32 = deposit32(opcode32, 16, 16, 790 translator_lduw(env, &ctx->base, 791 ctx->base.pc_next + 2)); 792 ctx->pc_succ_insn = ctx->base.pc_next + 4; 793 if (!decode_insn32(ctx, opcode32)) { 794 gen_exception_illegal(ctx); 795 } 796 } 797 } 798 799 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 800 { 801 DisasContext *ctx = container_of(dcbase, DisasContext, base); 802 CPURISCVState *env = cs->env_ptr; 803 RISCVCPU *cpu = RISCV_CPU(cs); 804 uint32_t tb_flags = ctx->base.tb->flags; 805 806 ctx->pc_succ_insn = ctx->base.pc_first; 807 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 808 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 809 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 810 ctx->priv_ver = env->priv_ver; 811 #if !defined(CONFIG_USER_ONLY) 812 if (riscv_has_ext(env, RVH)) { 813 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 814 } else { 815 ctx->virt_enabled = false; 816 } 817 #else 818 ctx->virt_enabled = false; 819 #endif 820 ctx->misa_ext = env->misa_ext; 821 ctx->frm = -1; /* unknown rounding mode */ 822 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 823 ctx->ext_zfh = cpu->cfg.ext_zfh; 824 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 825 ctx->vlen = cpu->cfg.vlen; 826 ctx->elen = cpu->cfg.elen; 827 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 828 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 829 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 830 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 831 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 832 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 833 ctx->vstart = env->vstart; 834 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 835 ctx->misa_mxl_max = env->misa_mxl_max; 836 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 837 ctx->cs = cs; 838 ctx->ntemp = 0; 839 memset(ctx->temp, 0, sizeof(ctx->temp)); 840 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 841 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 842 ctx->pm_mask = pm_mask[priv]; 843 ctx->pm_base = pm_base[priv]; 844 845 ctx->zero = tcg_constant_tl(0); 846 } 847 848 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 849 { 850 } 851 852 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 853 { 854 DisasContext *ctx = container_of(dcbase, DisasContext, base); 855 856 tcg_gen_insn_start(ctx->base.pc_next); 857 } 858 859 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 860 { 861 DisasContext *ctx = container_of(dcbase, DisasContext, base); 862 CPURISCVState *env = cpu->env_ptr; 863 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 864 865 ctx->ol = ctx->xl; 866 decode_opc(env, ctx, opcode16); 867 ctx->base.pc_next = ctx->pc_succ_insn; 868 869 for (int i = ctx->ntemp - 1; i >= 0; --i) { 870 tcg_temp_free(ctx->temp[i]); 871 ctx->temp[i] = NULL; 872 } 873 ctx->ntemp = 0; 874 875 if (ctx->base.is_jmp == DISAS_NEXT) { 876 target_ulong page_start; 877 878 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 879 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 880 ctx->base.is_jmp = DISAS_TOO_MANY; 881 } 882 } 883 } 884 885 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 886 { 887 DisasContext *ctx = container_of(dcbase, DisasContext, base); 888 889 switch (ctx->base.is_jmp) { 890 case DISAS_TOO_MANY: 891 gen_goto_tb(ctx, 0, ctx->base.pc_next); 892 break; 893 case DISAS_NORETURN: 894 break; 895 default: 896 g_assert_not_reached(); 897 } 898 } 899 900 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 901 { 902 #ifndef CONFIG_USER_ONLY 903 RISCVCPU *rvcpu = RISCV_CPU(cpu); 904 CPURISCVState *env = &rvcpu->env; 905 #endif 906 907 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 908 #ifndef CONFIG_USER_ONLY 909 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 910 #endif 911 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 912 } 913 914 static const TranslatorOps riscv_tr_ops = { 915 .init_disas_context = riscv_tr_init_disas_context, 916 .tb_start = riscv_tr_tb_start, 917 .insn_start = riscv_tr_insn_start, 918 .translate_insn = riscv_tr_translate_insn, 919 .tb_stop = riscv_tr_tb_stop, 920 .disas_log = riscv_tr_disas_log, 921 }; 922 923 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 924 { 925 DisasContext ctx; 926 927 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 928 } 929 930 void riscv_translate_init(void) 931 { 932 int i; 933 934 /* 935 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 936 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 937 * unless you specifically block reads/writes to reg 0. 938 */ 939 cpu_gpr[0] = NULL; 940 cpu_gprh[0] = NULL; 941 942 for (i = 1; i < 32; i++) { 943 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 944 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 945 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 946 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 947 } 948 949 for (i = 0; i < 32; i++) { 950 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 951 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 952 } 953 954 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 955 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 956 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 957 "vstart"); 958 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 959 "load_res"); 960 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 961 "load_val"); 962 #ifndef CONFIG_USER_ONLY 963 /* Assign PM CSRs to tcg globals */ 964 pm_mask[PRV_U] = 965 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 966 pm_base[PRV_U] = 967 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 968 pm_mask[PRV_S] = 969 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 970 pm_base[PRV_S] = 971 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 972 pm_mask[PRV_M] = 973 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 974 pm_base[PRV_M] = 975 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 976 #endif 977 } 978