1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint16_t vlen; 100 uint16_t elen; 101 target_ulong vstart; 102 bool vl_eq_vlmax; 103 uint8_t ntemp; 104 CPUState *cs; 105 TCGv zero; 106 /* Space for 3 operands plus 1 extra for address computation. */ 107 TCGv temp[4]; 108 /* PointerMasking extension */ 109 bool pm_enabled; 110 TCGv pm_mask; 111 TCGv pm_base; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void generate_exception(DisasContext *ctx, int excp) 195 { 196 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 198 ctx->base.is_jmp = DISAS_NORETURN; 199 } 200 201 static void generate_exception_mtval(DisasContext *ctx, int excp) 202 { 203 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 204 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 205 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 206 ctx->base.is_jmp = DISAS_NORETURN; 207 } 208 209 static void gen_exception_illegal(DisasContext *ctx) 210 { 211 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 212 } 213 214 static void gen_exception_inst_addr_mis(DisasContext *ctx) 215 { 216 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 217 } 218 219 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 220 { 221 if (translator_use_goto_tb(&ctx->base, dest)) { 222 tcg_gen_goto_tb(n); 223 tcg_gen_movi_tl(cpu_pc, dest); 224 tcg_gen_exit_tb(ctx->base.tb, n); 225 } else { 226 tcg_gen_movi_tl(cpu_pc, dest); 227 tcg_gen_lookup_and_goto_ptr(); 228 } 229 } 230 231 /* 232 * Wrappers for getting reg values. 233 * 234 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 235 * constant zero as a source, and an uninitialized sink as destination. 236 * 237 * Further, we may provide an extension for word operations. 238 */ 239 static TCGv temp_new(DisasContext *ctx) 240 { 241 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 242 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 243 } 244 245 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 246 { 247 TCGv t; 248 249 if (reg_num == 0) { 250 return ctx->zero; 251 } 252 253 switch (get_ol(ctx)) { 254 case MXL_RV32: 255 switch (ext) { 256 case EXT_NONE: 257 break; 258 case EXT_SIGN: 259 t = temp_new(ctx); 260 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 261 return t; 262 case EXT_ZERO: 263 t = temp_new(ctx); 264 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 265 return t; 266 default: 267 g_assert_not_reached(); 268 } 269 break; 270 case MXL_RV64: 271 case MXL_RV128: 272 break; 273 default: 274 g_assert_not_reached(); 275 } 276 return cpu_gpr[reg_num]; 277 } 278 279 static TCGv get_gprh(DisasContext *ctx, int reg_num) 280 { 281 assert(get_xl(ctx) == MXL_RV128); 282 if (reg_num == 0) { 283 return ctx->zero; 284 } 285 return cpu_gprh[reg_num]; 286 } 287 288 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 289 { 290 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 291 return temp_new(ctx); 292 } 293 return cpu_gpr[reg_num]; 294 } 295 296 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 297 { 298 if (reg_num == 0) { 299 return temp_new(ctx); 300 } 301 return cpu_gprh[reg_num]; 302 } 303 304 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 305 { 306 if (reg_num != 0) { 307 switch (get_ol(ctx)) { 308 case MXL_RV32: 309 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 310 break; 311 case MXL_RV64: 312 case MXL_RV128: 313 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 314 break; 315 default: 316 g_assert_not_reached(); 317 } 318 319 if (get_xl_max(ctx) == MXL_RV128) { 320 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 321 } 322 } 323 } 324 325 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 326 { 327 assert(get_ol(ctx) == MXL_RV128); 328 if (reg_num != 0) { 329 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 330 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 331 } 332 } 333 334 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 335 { 336 target_ulong next_pc; 337 338 /* check misaligned: */ 339 next_pc = ctx->base.pc_next + imm; 340 if (!has_ext(ctx, RVC)) { 341 if ((next_pc & 0x3) != 0) { 342 gen_exception_inst_addr_mis(ctx); 343 return; 344 } 345 } 346 if (rd != 0) { 347 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 348 } 349 350 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 351 ctx->base.is_jmp = DISAS_NORETURN; 352 } 353 354 /* 355 * Generates address adjustment for PointerMasking 356 */ 357 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 358 { 359 TCGv temp; 360 if (!s->pm_enabled) { 361 /* Load unmodified address */ 362 return src; 363 } else { 364 temp = temp_new(s); 365 tcg_gen_andc_tl(temp, src, s->pm_mask); 366 tcg_gen_or_tl(temp, temp, s->pm_base); 367 return temp; 368 } 369 } 370 371 #ifndef CONFIG_USER_ONLY 372 /* The states of mstatus_fs are: 373 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 374 * We will have already diagnosed disabled state, 375 * and need to turn initial/clean into dirty. 376 */ 377 static void mark_fs_dirty(DisasContext *ctx) 378 { 379 TCGv tmp; 380 381 if (ctx->mstatus_fs != MSTATUS_FS) { 382 /* Remember the state change for the rest of the TB. */ 383 ctx->mstatus_fs = MSTATUS_FS; 384 385 tmp = tcg_temp_new(); 386 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 387 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 388 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 389 tcg_temp_free(tmp); 390 } 391 392 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 393 /* Remember the stage change for the rest of the TB. */ 394 ctx->mstatus_hs_fs = MSTATUS_FS; 395 396 tmp = tcg_temp_new(); 397 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 398 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 399 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 400 tcg_temp_free(tmp); 401 } 402 } 403 #else 404 static inline void mark_fs_dirty(DisasContext *ctx) { } 405 #endif 406 407 #ifndef CONFIG_USER_ONLY 408 /* The states of mstatus_vs are: 409 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 410 * We will have already diagnosed disabled state, 411 * and need to turn initial/clean into dirty. 412 */ 413 static void mark_vs_dirty(DisasContext *ctx) 414 { 415 TCGv tmp; 416 417 if (ctx->mstatus_vs != MSTATUS_VS) { 418 /* Remember the state change for the rest of the TB. */ 419 ctx->mstatus_vs = MSTATUS_VS; 420 421 tmp = tcg_temp_new(); 422 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 423 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 424 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 425 tcg_temp_free(tmp); 426 } 427 428 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 429 /* Remember the stage change for the rest of the TB. */ 430 ctx->mstatus_hs_vs = MSTATUS_VS; 431 432 tmp = tcg_temp_new(); 433 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 434 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 435 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 436 tcg_temp_free(tmp); 437 } 438 } 439 #else 440 static inline void mark_vs_dirty(DisasContext *ctx) { } 441 #endif 442 443 static void gen_set_rm(DisasContext *ctx, int rm) 444 { 445 if (ctx->frm == rm) { 446 return; 447 } 448 ctx->frm = rm; 449 450 if (rm == RISCV_FRM_ROD) { 451 gen_helper_set_rod_rounding_mode(cpu_env); 452 return; 453 } 454 455 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 456 } 457 458 static int ex_plus_1(DisasContext *ctx, int nf) 459 { 460 return nf + 1; 461 } 462 463 #define EX_SH(amount) \ 464 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 465 { \ 466 return imm << amount; \ 467 } 468 EX_SH(1) 469 EX_SH(2) 470 EX_SH(3) 471 EX_SH(4) 472 EX_SH(12) 473 474 #define REQUIRE_EXT(ctx, ext) do { \ 475 if (!has_ext(ctx, ext)) { \ 476 return false; \ 477 } \ 478 } while (0) 479 480 #define REQUIRE_32BIT(ctx) do { \ 481 if (get_xl(ctx) != MXL_RV32) { \ 482 return false; \ 483 } \ 484 } while (0) 485 486 #define REQUIRE_64BIT(ctx) do { \ 487 if (get_xl(ctx) != MXL_RV64) { \ 488 return false; \ 489 } \ 490 } while (0) 491 492 #define REQUIRE_128BIT(ctx) do { \ 493 if (get_xl(ctx) != MXL_RV128) { \ 494 return false; \ 495 } \ 496 } while (0) 497 498 #define REQUIRE_64_OR_128BIT(ctx) do { \ 499 if (get_xl(ctx) == MXL_RV32) { \ 500 return false; \ 501 } \ 502 } while (0) 503 504 static int ex_rvc_register(DisasContext *ctx, int reg) 505 { 506 return 8 + reg; 507 } 508 509 static int ex_rvc_shifti(DisasContext *ctx, int imm) 510 { 511 /* For RV128 a shamt of 0 means a shift by 64. */ 512 return imm ? imm : 64; 513 } 514 515 /* Include the auto-generated decoder for 32 bit insn */ 516 #include "decode-insn32.c.inc" 517 518 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 519 void (*func)(TCGv, TCGv, target_long)) 520 { 521 TCGv dest = dest_gpr(ctx, a->rd); 522 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 523 524 func(dest, src1, a->imm); 525 526 if (get_xl(ctx) == MXL_RV128) { 527 TCGv src1h = get_gprh(ctx, a->rs1); 528 TCGv desth = dest_gprh(ctx, a->rd); 529 530 func(desth, src1h, -(a->imm < 0)); 531 gen_set_gpr128(ctx, a->rd, dest, desth); 532 } else { 533 gen_set_gpr(ctx, a->rd, dest); 534 } 535 536 return true; 537 } 538 539 static bool gen_logic(DisasContext *ctx, arg_r *a, 540 void (*func)(TCGv, TCGv, TCGv)) 541 { 542 TCGv dest = dest_gpr(ctx, a->rd); 543 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 544 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 545 546 func(dest, src1, src2); 547 548 if (get_xl(ctx) == MXL_RV128) { 549 TCGv src1h = get_gprh(ctx, a->rs1); 550 TCGv src2h = get_gprh(ctx, a->rs2); 551 TCGv desth = dest_gprh(ctx, a->rd); 552 553 func(desth, src1h, src2h); 554 gen_set_gpr128(ctx, a->rd, dest, desth); 555 } else { 556 gen_set_gpr(ctx, a->rd, dest); 557 } 558 559 return true; 560 } 561 562 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 563 void (*func)(TCGv, TCGv, target_long)) 564 { 565 TCGv dest = dest_gpr(ctx, a->rd); 566 TCGv src1 = get_gpr(ctx, a->rs1, ext); 567 568 func(dest, src1, a->imm); 569 570 gen_set_gpr(ctx, a->rd, dest); 571 return true; 572 } 573 574 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 575 void (*func)(TCGv, TCGv, TCGv)) 576 { 577 TCGv dest = dest_gpr(ctx, a->rd); 578 TCGv src1 = get_gpr(ctx, a->rs1, ext); 579 TCGv src2 = tcg_constant_tl(a->imm); 580 581 func(dest, src1, src2); 582 583 gen_set_gpr(ctx, a->rd, dest); 584 return true; 585 } 586 587 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 588 void (*func)(TCGv, TCGv, TCGv)) 589 { 590 TCGv dest = dest_gpr(ctx, a->rd); 591 TCGv src1 = get_gpr(ctx, a->rs1, ext); 592 TCGv src2 = get_gpr(ctx, a->rs2, ext); 593 594 func(dest, src1, src2); 595 596 gen_set_gpr(ctx, a->rd, dest); 597 return true; 598 } 599 600 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 601 void (*f_tl)(TCGv, TCGv, TCGv), 602 void (*f_32)(TCGv, TCGv, TCGv)) 603 { 604 int olen = get_olen(ctx); 605 606 if (olen != TARGET_LONG_BITS) { 607 if (olen == 32) { 608 f_tl = f_32; 609 } else { 610 g_assert_not_reached(); 611 } 612 } 613 return gen_arith(ctx, a, ext, f_tl); 614 } 615 616 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 617 void (*func)(TCGv, TCGv, target_long)) 618 { 619 TCGv dest, src1; 620 int max_len = get_olen(ctx); 621 622 if (a->shamt >= max_len) { 623 return false; 624 } 625 626 dest = dest_gpr(ctx, a->rd); 627 src1 = get_gpr(ctx, a->rs1, ext); 628 629 func(dest, src1, a->shamt); 630 631 gen_set_gpr(ctx, a->rd, dest); 632 return true; 633 } 634 635 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 636 DisasExtend ext, 637 void (*f_tl)(TCGv, TCGv, target_long), 638 void (*f_32)(TCGv, TCGv, target_long)) 639 { 640 int olen = get_olen(ctx); 641 if (olen != TARGET_LONG_BITS) { 642 if (olen == 32) { 643 f_tl = f_32; 644 } else { 645 g_assert_not_reached(); 646 } 647 } 648 return gen_shift_imm_fn(ctx, a, ext, f_tl); 649 } 650 651 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 652 void (*func)(TCGv, TCGv, TCGv)) 653 { 654 TCGv dest, src1, src2; 655 int max_len = get_olen(ctx); 656 657 if (a->shamt >= max_len) { 658 return false; 659 } 660 661 dest = dest_gpr(ctx, a->rd); 662 src1 = get_gpr(ctx, a->rs1, ext); 663 src2 = tcg_constant_tl(a->shamt); 664 665 func(dest, src1, src2); 666 667 gen_set_gpr(ctx, a->rd, dest); 668 return true; 669 } 670 671 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 672 void (*func)(TCGv, TCGv, TCGv)) 673 { 674 TCGv dest = dest_gpr(ctx, a->rd); 675 TCGv src1 = get_gpr(ctx, a->rs1, ext); 676 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 677 TCGv ext2 = tcg_temp_new(); 678 679 tcg_gen_andi_tl(ext2, src2, get_olen(ctx) - 1); 680 func(dest, src1, ext2); 681 682 gen_set_gpr(ctx, a->rd, dest); 683 tcg_temp_free(ext2); 684 return true; 685 } 686 687 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 688 void (*f_tl)(TCGv, TCGv, TCGv), 689 void (*f_32)(TCGv, TCGv, TCGv)) 690 { 691 int olen = get_olen(ctx); 692 if (olen != TARGET_LONG_BITS) { 693 if (olen == 32) { 694 f_tl = f_32; 695 } else { 696 g_assert_not_reached(); 697 } 698 } 699 return gen_shift(ctx, a, ext, f_tl); 700 } 701 702 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 703 void (*func)(TCGv, TCGv)) 704 { 705 TCGv dest = dest_gpr(ctx, a->rd); 706 TCGv src1 = get_gpr(ctx, a->rs1, ext); 707 708 func(dest, src1); 709 710 gen_set_gpr(ctx, a->rd, dest); 711 return true; 712 } 713 714 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 715 void (*f_tl)(TCGv, TCGv), 716 void (*f_32)(TCGv, TCGv)) 717 { 718 int olen = get_olen(ctx); 719 720 if (olen != TARGET_LONG_BITS) { 721 if (olen == 32) { 722 f_tl = f_32; 723 } else { 724 g_assert_not_reached(); 725 } 726 } 727 return gen_unary(ctx, a, ext, f_tl); 728 } 729 730 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 731 { 732 DisasContext *ctx = container_of(dcbase, DisasContext, base); 733 CPUState *cpu = ctx->cs; 734 CPURISCVState *env = cpu->env_ptr; 735 736 return cpu_ldl_code(env, pc); 737 } 738 739 /* Include insn module translation function */ 740 #include "insn_trans/trans_rvi.c.inc" 741 #include "insn_trans/trans_rvm.c.inc" 742 #include "insn_trans/trans_rva.c.inc" 743 #include "insn_trans/trans_rvf.c.inc" 744 #include "insn_trans/trans_rvd.c.inc" 745 #include "insn_trans/trans_rvh.c.inc" 746 #include "insn_trans/trans_rvv.c.inc" 747 #include "insn_trans/trans_rvb.c.inc" 748 #include "insn_trans/trans_rvzfh.c.inc" 749 #include "insn_trans/trans_privileged.c.inc" 750 751 /* Include the auto-generated decoder for 16 bit insn */ 752 #include "decode-insn16.c.inc" 753 754 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 755 { 756 /* check for compressed insn */ 757 if (extract16(opcode, 0, 2) != 3) { 758 if (!has_ext(ctx, RVC)) { 759 gen_exception_illegal(ctx); 760 } else { 761 ctx->pc_succ_insn = ctx->base.pc_next + 2; 762 if (!decode_insn16(ctx, opcode)) { 763 gen_exception_illegal(ctx); 764 } 765 } 766 } else { 767 uint32_t opcode32 = opcode; 768 opcode32 = deposit32(opcode32, 16, 16, 769 translator_lduw(env, &ctx->base, 770 ctx->base.pc_next + 2)); 771 ctx->pc_succ_insn = ctx->base.pc_next + 4; 772 if (!decode_insn32(ctx, opcode32)) { 773 gen_exception_illegal(ctx); 774 } 775 } 776 } 777 778 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 779 { 780 DisasContext *ctx = container_of(dcbase, DisasContext, base); 781 CPURISCVState *env = cs->env_ptr; 782 RISCVCPU *cpu = RISCV_CPU(cs); 783 uint32_t tb_flags = ctx->base.tb->flags; 784 785 ctx->pc_succ_insn = ctx->base.pc_first; 786 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 787 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 788 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 789 ctx->priv_ver = env->priv_ver; 790 #if !defined(CONFIG_USER_ONLY) 791 if (riscv_has_ext(env, RVH)) { 792 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 793 } else { 794 ctx->virt_enabled = false; 795 } 796 #else 797 ctx->virt_enabled = false; 798 #endif 799 ctx->misa_ext = env->misa_ext; 800 ctx->frm = -1; /* unknown rounding mode */ 801 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 802 ctx->ext_zfh = cpu->cfg.ext_zfh; 803 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 804 ctx->vlen = cpu->cfg.vlen; 805 ctx->elen = cpu->cfg.elen; 806 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 807 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 808 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 809 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 810 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 811 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 812 ctx->vstart = env->vstart; 813 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 814 ctx->misa_mxl_max = env->misa_mxl_max; 815 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 816 ctx->cs = cs; 817 ctx->ntemp = 0; 818 memset(ctx->temp, 0, sizeof(ctx->temp)); 819 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 820 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 821 ctx->pm_mask = pm_mask[priv]; 822 ctx->pm_base = pm_base[priv]; 823 824 ctx->zero = tcg_constant_tl(0); 825 } 826 827 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 828 { 829 } 830 831 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 832 { 833 DisasContext *ctx = container_of(dcbase, DisasContext, base); 834 835 tcg_gen_insn_start(ctx->base.pc_next); 836 } 837 838 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 839 { 840 DisasContext *ctx = container_of(dcbase, DisasContext, base); 841 CPURISCVState *env = cpu->env_ptr; 842 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 843 844 ctx->ol = ctx->xl; 845 decode_opc(env, ctx, opcode16); 846 ctx->base.pc_next = ctx->pc_succ_insn; 847 848 for (int i = ctx->ntemp - 1; i >= 0; --i) { 849 tcg_temp_free(ctx->temp[i]); 850 ctx->temp[i] = NULL; 851 } 852 ctx->ntemp = 0; 853 854 if (ctx->base.is_jmp == DISAS_NEXT) { 855 target_ulong page_start; 856 857 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 858 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 859 ctx->base.is_jmp = DISAS_TOO_MANY; 860 } 861 } 862 } 863 864 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 865 { 866 DisasContext *ctx = container_of(dcbase, DisasContext, base); 867 868 switch (ctx->base.is_jmp) { 869 case DISAS_TOO_MANY: 870 gen_goto_tb(ctx, 0, ctx->base.pc_next); 871 break; 872 case DISAS_NORETURN: 873 break; 874 default: 875 g_assert_not_reached(); 876 } 877 } 878 879 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 880 { 881 #ifndef CONFIG_USER_ONLY 882 RISCVCPU *rvcpu = RISCV_CPU(cpu); 883 CPURISCVState *env = &rvcpu->env; 884 #endif 885 886 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 887 #ifndef CONFIG_USER_ONLY 888 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 889 #endif 890 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 891 } 892 893 static const TranslatorOps riscv_tr_ops = { 894 .init_disas_context = riscv_tr_init_disas_context, 895 .tb_start = riscv_tr_tb_start, 896 .insn_start = riscv_tr_insn_start, 897 .translate_insn = riscv_tr_translate_insn, 898 .tb_stop = riscv_tr_tb_stop, 899 .disas_log = riscv_tr_disas_log, 900 }; 901 902 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 903 { 904 DisasContext ctx; 905 906 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 907 } 908 909 void riscv_translate_init(void) 910 { 911 int i; 912 913 /* 914 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 915 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 916 * unless you specifically block reads/writes to reg 0. 917 */ 918 cpu_gpr[0] = NULL; 919 cpu_gprh[0] = NULL; 920 921 for (i = 1; i < 32; i++) { 922 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 923 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 924 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 925 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 926 } 927 928 for (i = 0; i < 32; i++) { 929 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 930 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 931 } 932 933 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 934 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 935 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 936 "vstart"); 937 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 938 "load_res"); 939 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 940 "load_val"); 941 #ifndef CONFIG_USER_ONLY 942 /* Assign PM CSRs to tcg globals */ 943 pm_mask[PRV_U] = 944 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 945 pm_base[PRV_U] = 946 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 947 pm_mask[PRV_S] = 948 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 949 pm_base[PRV_S] = 950 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 951 pm_mask[PRV_M] = 952 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 953 pm_base[PRV_M] = 954 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 955 #endif 956 } 957