1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask[4]; 42 static TCGv pm_base[4]; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool hlsx; 83 /* vector extension */ 84 bool vill; 85 /* 86 * Encode LMUL to lmul as follows: 87 * LMUL vlmul lmul 88 * 1 000 0 89 * 2 001 1 90 * 4 010 2 91 * 8 011 3 92 * - 100 - 93 * 1/8 101 -3 94 * 1/4 110 -2 95 * 1/2 111 -1 96 */ 97 int8_t lmul; 98 uint8_t sew; 99 uint16_t vlen; 100 uint16_t elen; 101 target_ulong vstart; 102 bool vl_eq_vlmax; 103 uint8_t ntemp; 104 CPUState *cs; 105 TCGv zero; 106 /* Space for 3 operands plus 1 extra for address computation. */ 107 TCGv temp[4]; 108 /* PointerMasking extension */ 109 bool pm_enabled; 110 TCGv pm_mask; 111 TCGv pm_base; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void generate_exception(DisasContext *ctx, int excp) 195 { 196 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 197 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 198 ctx->base.is_jmp = DISAS_NORETURN; 199 } 200 201 static void generate_exception_mtval(DisasContext *ctx, int excp) 202 { 203 tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); 204 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 205 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 206 ctx->base.is_jmp = DISAS_NORETURN; 207 } 208 209 static void gen_exception_illegal(DisasContext *ctx) 210 { 211 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 212 offsetof(CPURISCVState, bins)); 213 214 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 215 } 216 217 static void gen_exception_inst_addr_mis(DisasContext *ctx) 218 { 219 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 220 } 221 222 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 223 { 224 if (translator_use_goto_tb(&ctx->base, dest)) { 225 tcg_gen_goto_tb(n); 226 tcg_gen_movi_tl(cpu_pc, dest); 227 tcg_gen_exit_tb(ctx->base.tb, n); 228 } else { 229 tcg_gen_movi_tl(cpu_pc, dest); 230 tcg_gen_lookup_and_goto_ptr(); 231 } 232 } 233 234 /* 235 * Wrappers for getting reg values. 236 * 237 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 238 * constant zero as a source, and an uninitialized sink as destination. 239 * 240 * Further, we may provide an extension for word operations. 241 */ 242 static TCGv temp_new(DisasContext *ctx) 243 { 244 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 245 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 246 } 247 248 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 249 { 250 TCGv t; 251 252 if (reg_num == 0) { 253 return ctx->zero; 254 } 255 256 switch (get_ol(ctx)) { 257 case MXL_RV32: 258 switch (ext) { 259 case EXT_NONE: 260 break; 261 case EXT_SIGN: 262 t = temp_new(ctx); 263 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 264 return t; 265 case EXT_ZERO: 266 t = temp_new(ctx); 267 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 268 return t; 269 default: 270 g_assert_not_reached(); 271 } 272 break; 273 case MXL_RV64: 274 case MXL_RV128: 275 break; 276 default: 277 g_assert_not_reached(); 278 } 279 return cpu_gpr[reg_num]; 280 } 281 282 static TCGv get_gprh(DisasContext *ctx, int reg_num) 283 { 284 assert(get_xl(ctx) == MXL_RV128); 285 if (reg_num == 0) { 286 return ctx->zero; 287 } 288 return cpu_gprh[reg_num]; 289 } 290 291 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 292 { 293 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 294 return temp_new(ctx); 295 } 296 return cpu_gpr[reg_num]; 297 } 298 299 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 300 { 301 if (reg_num == 0) { 302 return temp_new(ctx); 303 } 304 return cpu_gprh[reg_num]; 305 } 306 307 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 308 { 309 if (reg_num != 0) { 310 switch (get_ol(ctx)) { 311 case MXL_RV32: 312 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 313 break; 314 case MXL_RV64: 315 case MXL_RV128: 316 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 317 break; 318 default: 319 g_assert_not_reached(); 320 } 321 322 if (get_xl_max(ctx) == MXL_RV128) { 323 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 324 } 325 } 326 } 327 328 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 329 { 330 if (reg_num != 0) { 331 switch (get_ol(ctx)) { 332 case MXL_RV32: 333 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 334 break; 335 case MXL_RV64: 336 case MXL_RV128: 337 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 338 break; 339 default: 340 g_assert_not_reached(); 341 } 342 343 if (get_xl_max(ctx) == MXL_RV128) { 344 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 345 } 346 } 347 } 348 349 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 350 { 351 assert(get_ol(ctx) == MXL_RV128); 352 if (reg_num != 0) { 353 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 354 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 355 } 356 } 357 358 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 359 { 360 target_ulong next_pc; 361 362 /* check misaligned: */ 363 next_pc = ctx->base.pc_next + imm; 364 if (!has_ext(ctx, RVC)) { 365 if ((next_pc & 0x3) != 0) { 366 gen_exception_inst_addr_mis(ctx); 367 return; 368 } 369 } 370 if (rd != 0) { 371 tcg_gen_movi_tl(cpu_gpr[rd], ctx->pc_succ_insn); 372 } 373 374 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 375 ctx->base.is_jmp = DISAS_NORETURN; 376 } 377 378 /* 379 * Generates address adjustment for PointerMasking 380 */ 381 static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src) 382 { 383 TCGv temp; 384 if (!s->pm_enabled) { 385 /* Load unmodified address */ 386 return src; 387 } else { 388 temp = temp_new(s); 389 tcg_gen_andc_tl(temp, src, s->pm_mask); 390 tcg_gen_or_tl(temp, temp, s->pm_base); 391 return temp; 392 } 393 } 394 395 #ifndef CONFIG_USER_ONLY 396 /* The states of mstatus_fs are: 397 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 398 * We will have already diagnosed disabled state, 399 * and need to turn initial/clean into dirty. 400 */ 401 static void mark_fs_dirty(DisasContext *ctx) 402 { 403 TCGv tmp; 404 405 if (ctx->mstatus_fs != MSTATUS_FS) { 406 /* Remember the state change for the rest of the TB. */ 407 ctx->mstatus_fs = MSTATUS_FS; 408 409 tmp = tcg_temp_new(); 410 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 411 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 412 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 413 tcg_temp_free(tmp); 414 } 415 416 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 417 /* Remember the stage change for the rest of the TB. */ 418 ctx->mstatus_hs_fs = MSTATUS_FS; 419 420 tmp = tcg_temp_new(); 421 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 422 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 423 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 424 tcg_temp_free(tmp); 425 } 426 } 427 #else 428 static inline void mark_fs_dirty(DisasContext *ctx) { } 429 #endif 430 431 #ifndef CONFIG_USER_ONLY 432 /* The states of mstatus_vs are: 433 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 434 * We will have already diagnosed disabled state, 435 * and need to turn initial/clean into dirty. 436 */ 437 static void mark_vs_dirty(DisasContext *ctx) 438 { 439 TCGv tmp; 440 441 if (ctx->mstatus_vs != MSTATUS_VS) { 442 /* Remember the state change for the rest of the TB. */ 443 ctx->mstatus_vs = MSTATUS_VS; 444 445 tmp = tcg_temp_new(); 446 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 447 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 448 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 449 tcg_temp_free(tmp); 450 } 451 452 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 453 /* Remember the stage change for the rest of the TB. */ 454 ctx->mstatus_hs_vs = MSTATUS_VS; 455 456 tmp = tcg_temp_new(); 457 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 458 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 459 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 460 tcg_temp_free(tmp); 461 } 462 } 463 #else 464 static inline void mark_vs_dirty(DisasContext *ctx) { } 465 #endif 466 467 static void gen_set_rm(DisasContext *ctx, int rm) 468 { 469 if (ctx->frm == rm) { 470 return; 471 } 472 ctx->frm = rm; 473 474 if (rm == RISCV_FRM_ROD) { 475 gen_helper_set_rod_rounding_mode(cpu_env); 476 return; 477 } 478 479 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 480 } 481 482 static int ex_plus_1(DisasContext *ctx, int nf) 483 { 484 return nf + 1; 485 } 486 487 #define EX_SH(amount) \ 488 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 489 { \ 490 return imm << amount; \ 491 } 492 EX_SH(1) 493 EX_SH(2) 494 EX_SH(3) 495 EX_SH(4) 496 EX_SH(12) 497 498 #define REQUIRE_EXT(ctx, ext) do { \ 499 if (!has_ext(ctx, ext)) { \ 500 return false; \ 501 } \ 502 } while (0) 503 504 #define REQUIRE_32BIT(ctx) do { \ 505 if (get_xl(ctx) != MXL_RV32) { \ 506 return false; \ 507 } \ 508 } while (0) 509 510 #define REQUIRE_64BIT(ctx) do { \ 511 if (get_xl(ctx) != MXL_RV64) { \ 512 return false; \ 513 } \ 514 } while (0) 515 516 #define REQUIRE_128BIT(ctx) do { \ 517 if (get_xl(ctx) != MXL_RV128) { \ 518 return false; \ 519 } \ 520 } while (0) 521 522 #define REQUIRE_64_OR_128BIT(ctx) do { \ 523 if (get_xl(ctx) == MXL_RV32) { \ 524 return false; \ 525 } \ 526 } while (0) 527 528 static int ex_rvc_register(DisasContext *ctx, int reg) 529 { 530 return 8 + reg; 531 } 532 533 static int ex_rvc_shifti(DisasContext *ctx, int imm) 534 { 535 /* For RV128 a shamt of 0 means a shift by 64. */ 536 return imm ? imm : 64; 537 } 538 539 /* Include the auto-generated decoder for 32 bit insn */ 540 #include "decode-insn32.c.inc" 541 542 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 543 void (*func)(TCGv, TCGv, target_long)) 544 { 545 TCGv dest = dest_gpr(ctx, a->rd); 546 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 547 548 func(dest, src1, a->imm); 549 550 if (get_xl(ctx) == MXL_RV128) { 551 TCGv src1h = get_gprh(ctx, a->rs1); 552 TCGv desth = dest_gprh(ctx, a->rd); 553 554 func(desth, src1h, -(a->imm < 0)); 555 gen_set_gpr128(ctx, a->rd, dest, desth); 556 } else { 557 gen_set_gpr(ctx, a->rd, dest); 558 } 559 560 return true; 561 } 562 563 static bool gen_logic(DisasContext *ctx, arg_r *a, 564 void (*func)(TCGv, TCGv, TCGv)) 565 { 566 TCGv dest = dest_gpr(ctx, a->rd); 567 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 568 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 569 570 func(dest, src1, src2); 571 572 if (get_xl(ctx) == MXL_RV128) { 573 TCGv src1h = get_gprh(ctx, a->rs1); 574 TCGv src2h = get_gprh(ctx, a->rs2); 575 TCGv desth = dest_gprh(ctx, a->rd); 576 577 func(desth, src1h, src2h); 578 gen_set_gpr128(ctx, a->rd, dest, desth); 579 } else { 580 gen_set_gpr(ctx, a->rd, dest); 581 } 582 583 return true; 584 } 585 586 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 587 void (*func)(TCGv, TCGv, target_long), 588 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 589 { 590 TCGv dest = dest_gpr(ctx, a->rd); 591 TCGv src1 = get_gpr(ctx, a->rs1, ext); 592 593 if (get_ol(ctx) < MXL_RV128) { 594 func(dest, src1, a->imm); 595 gen_set_gpr(ctx, a->rd, dest); 596 } else { 597 if (f128 == NULL) { 598 return false; 599 } 600 601 TCGv src1h = get_gprh(ctx, a->rs1); 602 TCGv desth = dest_gprh(ctx, a->rd); 603 604 f128(dest, desth, src1, src1h, a->imm); 605 gen_set_gpr128(ctx, a->rd, dest, desth); 606 } 607 return true; 608 } 609 610 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 611 void (*func)(TCGv, TCGv, TCGv), 612 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 613 { 614 TCGv dest = dest_gpr(ctx, a->rd); 615 TCGv src1 = get_gpr(ctx, a->rs1, ext); 616 TCGv src2 = tcg_constant_tl(a->imm); 617 618 if (get_ol(ctx) < MXL_RV128) { 619 func(dest, src1, src2); 620 gen_set_gpr(ctx, a->rd, dest); 621 } else { 622 if (f128 == NULL) { 623 return false; 624 } 625 626 TCGv src1h = get_gprh(ctx, a->rs1); 627 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 628 TCGv desth = dest_gprh(ctx, a->rd); 629 630 f128(dest, desth, src1, src1h, src2, src2h); 631 gen_set_gpr128(ctx, a->rd, dest, desth); 632 } 633 return true; 634 } 635 636 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 637 void (*func)(TCGv, TCGv, TCGv), 638 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 639 { 640 TCGv dest = dest_gpr(ctx, a->rd); 641 TCGv src1 = get_gpr(ctx, a->rs1, ext); 642 TCGv src2 = get_gpr(ctx, a->rs2, ext); 643 644 if (get_ol(ctx) < MXL_RV128) { 645 func(dest, src1, src2); 646 gen_set_gpr(ctx, a->rd, dest); 647 } else { 648 if (f128 == NULL) { 649 return false; 650 } 651 652 TCGv src1h = get_gprh(ctx, a->rs1); 653 TCGv src2h = get_gprh(ctx, a->rs2); 654 TCGv desth = dest_gprh(ctx, a->rd); 655 656 f128(dest, desth, src1, src1h, src2, src2h); 657 gen_set_gpr128(ctx, a->rd, dest, desth); 658 } 659 return true; 660 } 661 662 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 663 void (*f_tl)(TCGv, TCGv, TCGv), 664 void (*f_32)(TCGv, TCGv, TCGv), 665 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 666 { 667 int olen = get_olen(ctx); 668 669 if (olen != TARGET_LONG_BITS) { 670 if (olen == 32) { 671 f_tl = f_32; 672 } else if (olen != 128) { 673 g_assert_not_reached(); 674 } 675 } 676 return gen_arith(ctx, a, ext, f_tl, f_128); 677 } 678 679 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 680 void (*func)(TCGv, TCGv, target_long), 681 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 682 { 683 TCGv dest, src1; 684 int max_len = get_olen(ctx); 685 686 if (a->shamt >= max_len) { 687 return false; 688 } 689 690 dest = dest_gpr(ctx, a->rd); 691 src1 = get_gpr(ctx, a->rs1, ext); 692 693 if (max_len < 128) { 694 func(dest, src1, a->shamt); 695 gen_set_gpr(ctx, a->rd, dest); 696 } else { 697 TCGv src1h = get_gprh(ctx, a->rs1); 698 TCGv desth = dest_gprh(ctx, a->rd); 699 700 if (f128 == NULL) { 701 return false; 702 } 703 f128(dest, desth, src1, src1h, a->shamt); 704 gen_set_gpr128(ctx, a->rd, dest, desth); 705 } 706 return true; 707 } 708 709 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 710 DisasExtend ext, 711 void (*f_tl)(TCGv, TCGv, target_long), 712 void (*f_32)(TCGv, TCGv, target_long), 713 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 714 target_long)) 715 { 716 int olen = get_olen(ctx); 717 if (olen != TARGET_LONG_BITS) { 718 if (olen == 32) { 719 f_tl = f_32; 720 } else if (olen != 128) { 721 g_assert_not_reached(); 722 } 723 } 724 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 725 } 726 727 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 728 void (*func)(TCGv, TCGv, TCGv)) 729 { 730 TCGv dest, src1, src2; 731 int max_len = get_olen(ctx); 732 733 if (a->shamt >= max_len) { 734 return false; 735 } 736 737 dest = dest_gpr(ctx, a->rd); 738 src1 = get_gpr(ctx, a->rs1, ext); 739 src2 = tcg_constant_tl(a->shamt); 740 741 func(dest, src1, src2); 742 743 gen_set_gpr(ctx, a->rd, dest); 744 return true; 745 } 746 747 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 748 void (*func)(TCGv, TCGv, TCGv), 749 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 750 { 751 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 752 TCGv ext2 = tcg_temp_new(); 753 int max_len = get_olen(ctx); 754 755 tcg_gen_andi_tl(ext2, src2, max_len - 1); 756 757 TCGv dest = dest_gpr(ctx, a->rd); 758 TCGv src1 = get_gpr(ctx, a->rs1, ext); 759 760 if (max_len < 128) { 761 func(dest, src1, ext2); 762 gen_set_gpr(ctx, a->rd, dest); 763 } else { 764 TCGv src1h = get_gprh(ctx, a->rs1); 765 TCGv desth = dest_gprh(ctx, a->rd); 766 767 if (f128 == NULL) { 768 return false; 769 } 770 f128(dest, desth, src1, src1h, ext2); 771 gen_set_gpr128(ctx, a->rd, dest, desth); 772 } 773 tcg_temp_free(ext2); 774 return true; 775 } 776 777 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 778 void (*f_tl)(TCGv, TCGv, TCGv), 779 void (*f_32)(TCGv, TCGv, TCGv), 780 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 781 { 782 int olen = get_olen(ctx); 783 if (olen != TARGET_LONG_BITS) { 784 if (olen == 32) { 785 f_tl = f_32; 786 } else if (olen != 128) { 787 g_assert_not_reached(); 788 } 789 } 790 return gen_shift(ctx, a, ext, f_tl, f_128); 791 } 792 793 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 794 void (*func)(TCGv, TCGv)) 795 { 796 TCGv dest = dest_gpr(ctx, a->rd); 797 TCGv src1 = get_gpr(ctx, a->rs1, ext); 798 799 func(dest, src1); 800 801 gen_set_gpr(ctx, a->rd, dest); 802 return true; 803 } 804 805 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 806 void (*f_tl)(TCGv, TCGv), 807 void (*f_32)(TCGv, TCGv)) 808 { 809 int olen = get_olen(ctx); 810 811 if (olen != TARGET_LONG_BITS) { 812 if (olen == 32) { 813 f_tl = f_32; 814 } else { 815 g_assert_not_reached(); 816 } 817 } 818 return gen_unary(ctx, a, ext, f_tl); 819 } 820 821 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 822 { 823 DisasContext *ctx = container_of(dcbase, DisasContext, base); 824 CPUState *cpu = ctx->cs; 825 CPURISCVState *env = cpu->env_ptr; 826 827 return cpu_ldl_code(env, pc); 828 } 829 830 /* Include insn module translation function */ 831 #include "insn_trans/trans_rvi.c.inc" 832 #include "insn_trans/trans_rvm.c.inc" 833 #include "insn_trans/trans_rva.c.inc" 834 #include "insn_trans/trans_rvf.c.inc" 835 #include "insn_trans/trans_rvd.c.inc" 836 #include "insn_trans/trans_rvh.c.inc" 837 #include "insn_trans/trans_rvv.c.inc" 838 #include "insn_trans/trans_rvb.c.inc" 839 #include "insn_trans/trans_rvzfh.c.inc" 840 #include "insn_trans/trans_privileged.c.inc" 841 842 /* Include the auto-generated decoder for 16 bit insn */ 843 #include "decode-insn16.c.inc" 844 845 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 846 { 847 /* check for compressed insn */ 848 if (extract16(opcode, 0, 2) != 3) { 849 if (!has_ext(ctx, RVC)) { 850 gen_exception_illegal(ctx); 851 } else { 852 ctx->opcode = opcode; 853 ctx->pc_succ_insn = ctx->base.pc_next + 2; 854 if (!decode_insn16(ctx, opcode)) { 855 gen_exception_illegal(ctx); 856 } 857 } 858 } else { 859 uint32_t opcode32 = opcode; 860 opcode32 = deposit32(opcode32, 16, 16, 861 translator_lduw(env, &ctx->base, 862 ctx->base.pc_next + 2)); 863 ctx->opcode = opcode32; 864 ctx->pc_succ_insn = ctx->base.pc_next + 4; 865 if (!decode_insn32(ctx, opcode32)) { 866 gen_exception_illegal(ctx); 867 } 868 } 869 } 870 871 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 872 { 873 DisasContext *ctx = container_of(dcbase, DisasContext, base); 874 CPURISCVState *env = cs->env_ptr; 875 RISCVCPU *cpu = RISCV_CPU(cs); 876 uint32_t tb_flags = ctx->base.tb->flags; 877 878 ctx->pc_succ_insn = ctx->base.pc_first; 879 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 880 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 881 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 882 ctx->priv_ver = env->priv_ver; 883 #if !defined(CONFIG_USER_ONLY) 884 if (riscv_has_ext(env, RVH)) { 885 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 886 } else { 887 ctx->virt_enabled = false; 888 } 889 #else 890 ctx->virt_enabled = false; 891 #endif 892 ctx->misa_ext = env->misa_ext; 893 ctx->frm = -1; /* unknown rounding mode */ 894 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 895 ctx->ext_zfh = cpu->cfg.ext_zfh; 896 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 897 ctx->vlen = cpu->cfg.vlen; 898 ctx->elen = cpu->cfg.elen; 899 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 900 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 901 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 902 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 903 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 904 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 905 ctx->vstart = env->vstart; 906 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 907 ctx->misa_mxl_max = env->misa_mxl_max; 908 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 909 ctx->cs = cs; 910 ctx->ntemp = 0; 911 memset(ctx->temp, 0, sizeof(ctx->temp)); 912 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 913 int priv = tb_flags & TB_FLAGS_PRIV_MMU_MASK; 914 ctx->pm_mask = pm_mask[priv]; 915 ctx->pm_base = pm_base[priv]; 916 917 ctx->zero = tcg_constant_tl(0); 918 } 919 920 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 921 { 922 } 923 924 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 925 { 926 DisasContext *ctx = container_of(dcbase, DisasContext, base); 927 928 tcg_gen_insn_start(ctx->base.pc_next); 929 } 930 931 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 932 { 933 DisasContext *ctx = container_of(dcbase, DisasContext, base); 934 CPURISCVState *env = cpu->env_ptr; 935 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 936 937 ctx->ol = ctx->xl; 938 decode_opc(env, ctx, opcode16); 939 ctx->base.pc_next = ctx->pc_succ_insn; 940 941 for (int i = ctx->ntemp - 1; i >= 0; --i) { 942 tcg_temp_free(ctx->temp[i]); 943 ctx->temp[i] = NULL; 944 } 945 ctx->ntemp = 0; 946 947 if (ctx->base.is_jmp == DISAS_NEXT) { 948 target_ulong page_start; 949 950 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 951 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 952 ctx->base.is_jmp = DISAS_TOO_MANY; 953 } 954 } 955 } 956 957 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 958 { 959 DisasContext *ctx = container_of(dcbase, DisasContext, base); 960 961 switch (ctx->base.is_jmp) { 962 case DISAS_TOO_MANY: 963 gen_goto_tb(ctx, 0, ctx->base.pc_next); 964 break; 965 case DISAS_NORETURN: 966 break; 967 default: 968 g_assert_not_reached(); 969 } 970 } 971 972 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 973 { 974 #ifndef CONFIG_USER_ONLY 975 RISCVCPU *rvcpu = RISCV_CPU(cpu); 976 CPURISCVState *env = &rvcpu->env; 977 #endif 978 979 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 980 #ifndef CONFIG_USER_ONLY 981 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 982 #endif 983 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 984 } 985 986 static const TranslatorOps riscv_tr_ops = { 987 .init_disas_context = riscv_tr_init_disas_context, 988 .tb_start = riscv_tr_tb_start, 989 .insn_start = riscv_tr_insn_start, 990 .translate_insn = riscv_tr_translate_insn, 991 .tb_stop = riscv_tr_tb_stop, 992 .disas_log = riscv_tr_disas_log, 993 }; 994 995 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 996 { 997 DisasContext ctx; 998 999 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1000 } 1001 1002 void riscv_translate_init(void) 1003 { 1004 int i; 1005 1006 /* 1007 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1008 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1009 * unless you specifically block reads/writes to reg 0. 1010 */ 1011 cpu_gpr[0] = NULL; 1012 cpu_gprh[0] = NULL; 1013 1014 for (i = 1; i < 32; i++) { 1015 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1016 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1017 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1018 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1019 } 1020 1021 for (i = 0; i < 32; i++) { 1022 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1023 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1024 } 1025 1026 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1027 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1028 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1029 "vstart"); 1030 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1031 "load_res"); 1032 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1033 "load_val"); 1034 #ifndef CONFIG_USER_ONLY 1035 /* Assign PM CSRs to tcg globals */ 1036 pm_mask[PRV_U] = 1037 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmmask), "upmmask"); 1038 pm_base[PRV_U] = 1039 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, upmbase), "upmbase"); 1040 pm_mask[PRV_S] = 1041 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmmask), "spmmask"); 1042 pm_base[PRV_S] = 1043 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, spmbase), "spmbase"); 1044 pm_mask[PRV_M] = 1045 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmmask), "mpmmask"); 1046 pm_base[PRV_M] = 1047 tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, mpmbase), "mpmbase"); 1048 #endif 1049 } 1050