1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool ext_zve32f; 83 bool ext_zve64f; 84 bool hlsx; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint16_t vlen; 102 uint16_t elen; 103 target_ulong vstart; 104 bool vl_eq_vlmax; 105 uint8_t ntemp; 106 CPUState *cs; 107 TCGv zero; 108 /* Space for 3 operands plus 1 extra for address computation. */ 109 TCGv temp[4]; 110 /* PointerMasking extension */ 111 bool pm_enabled; 112 } DisasContext; 113 114 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 115 { 116 return ctx->misa_ext & ext; 117 } 118 119 #ifdef TARGET_RISCV32 120 #define get_xl(ctx) MXL_RV32 121 #elif defined(CONFIG_USER_ONLY) 122 #define get_xl(ctx) MXL_RV64 123 #else 124 #define get_xl(ctx) ((ctx)->xl) 125 #endif 126 127 /* The word size for this machine mode. */ 128 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 129 { 130 return 16 << get_xl(ctx); 131 } 132 133 /* The operation length, as opposed to the xlen. */ 134 #ifdef TARGET_RISCV32 135 #define get_ol(ctx) MXL_RV32 136 #else 137 #define get_ol(ctx) ((ctx)->ol) 138 #endif 139 140 static inline int get_olen(DisasContext *ctx) 141 { 142 return 16 << get_ol(ctx); 143 } 144 145 /* The maximum register length */ 146 #ifdef TARGET_RISCV32 147 #define get_xl_max(ctx) MXL_RV32 148 #else 149 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 150 #endif 151 152 /* 153 * RISC-V requires NaN-boxing of narrower width floating point values. 154 * This applies when a 32-bit value is assigned to a 64-bit FP register. 155 * For consistency and simplicity, we nanbox results even when the RVD 156 * extension is not present. 157 */ 158 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 159 { 160 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 161 } 162 163 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 164 { 165 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 166 } 167 168 /* 169 * A narrow n-bit operation, where n < FLEN, checks that input operands 170 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 171 * If so, the least-significant bits of the input are used, otherwise the 172 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 173 * 174 * Here, the result is always nan-boxed, even the canonical nan. 175 */ 176 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 177 { 178 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 179 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 180 181 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 182 tcg_temp_free_i64(t_max); 183 tcg_temp_free_i64(t_nan); 184 } 185 186 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 187 { 188 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 189 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 190 191 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 192 } 193 194 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 195 { 196 if (get_xl(ctx) == MXL_RV32) { 197 dest = (int32_t)dest; 198 } 199 tcg_gen_movi_tl(cpu_pc, dest); 200 } 201 202 static void gen_set_pc(DisasContext *ctx, TCGv dest) 203 { 204 if (get_xl(ctx) == MXL_RV32) { 205 tcg_gen_ext32s_tl(cpu_pc, dest); 206 } else { 207 tcg_gen_mov_tl(cpu_pc, dest); 208 } 209 } 210 211 static void generate_exception(DisasContext *ctx, int excp) 212 { 213 gen_set_pc_imm(ctx, ctx->base.pc_next); 214 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 215 ctx->base.is_jmp = DISAS_NORETURN; 216 } 217 218 static void generate_exception_mtval(DisasContext *ctx, int excp) 219 { 220 gen_set_pc_imm(ctx, ctx->base.pc_next); 221 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 222 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 223 ctx->base.is_jmp = DISAS_NORETURN; 224 } 225 226 static void gen_exception_illegal(DisasContext *ctx) 227 { 228 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 229 offsetof(CPURISCVState, bins)); 230 231 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 232 } 233 234 static void gen_exception_inst_addr_mis(DisasContext *ctx) 235 { 236 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 237 } 238 239 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 240 { 241 if (translator_use_goto_tb(&ctx->base, dest)) { 242 tcg_gen_goto_tb(n); 243 gen_set_pc_imm(ctx, dest); 244 tcg_gen_exit_tb(ctx->base.tb, n); 245 } else { 246 gen_set_pc_imm(ctx, dest); 247 tcg_gen_lookup_and_goto_ptr(); 248 } 249 } 250 251 /* 252 * Wrappers for getting reg values. 253 * 254 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 255 * constant zero as a source, and an uninitialized sink as destination. 256 * 257 * Further, we may provide an extension for word operations. 258 */ 259 static TCGv temp_new(DisasContext *ctx) 260 { 261 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 262 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 263 } 264 265 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 266 { 267 TCGv t; 268 269 if (reg_num == 0) { 270 return ctx->zero; 271 } 272 273 switch (get_ol(ctx)) { 274 case MXL_RV32: 275 switch (ext) { 276 case EXT_NONE: 277 break; 278 case EXT_SIGN: 279 t = temp_new(ctx); 280 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 281 return t; 282 case EXT_ZERO: 283 t = temp_new(ctx); 284 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 285 return t; 286 default: 287 g_assert_not_reached(); 288 } 289 break; 290 case MXL_RV64: 291 case MXL_RV128: 292 break; 293 default: 294 g_assert_not_reached(); 295 } 296 return cpu_gpr[reg_num]; 297 } 298 299 static TCGv get_gprh(DisasContext *ctx, int reg_num) 300 { 301 assert(get_xl(ctx) == MXL_RV128); 302 if (reg_num == 0) { 303 return ctx->zero; 304 } 305 return cpu_gprh[reg_num]; 306 } 307 308 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 309 { 310 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 311 return temp_new(ctx); 312 } 313 return cpu_gpr[reg_num]; 314 } 315 316 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 317 { 318 if (reg_num == 0) { 319 return temp_new(ctx); 320 } 321 return cpu_gprh[reg_num]; 322 } 323 324 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 325 { 326 if (reg_num != 0) { 327 switch (get_ol(ctx)) { 328 case MXL_RV32: 329 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 330 break; 331 case MXL_RV64: 332 case MXL_RV128: 333 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 334 break; 335 default: 336 g_assert_not_reached(); 337 } 338 339 if (get_xl_max(ctx) == MXL_RV128) { 340 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 341 } 342 } 343 } 344 345 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 346 { 347 if (reg_num != 0) { 348 switch (get_ol(ctx)) { 349 case MXL_RV32: 350 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 351 break; 352 case MXL_RV64: 353 case MXL_RV128: 354 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 355 break; 356 default: 357 g_assert_not_reached(); 358 } 359 360 if (get_xl_max(ctx) == MXL_RV128) { 361 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 362 } 363 } 364 } 365 366 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 367 { 368 assert(get_ol(ctx) == MXL_RV128); 369 if (reg_num != 0) { 370 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 371 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 372 } 373 } 374 375 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 376 { 377 target_ulong next_pc; 378 379 /* check misaligned: */ 380 next_pc = ctx->base.pc_next + imm; 381 if (!has_ext(ctx, RVC)) { 382 if ((next_pc & 0x3) != 0) { 383 gen_exception_inst_addr_mis(ctx); 384 return; 385 } 386 } 387 388 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 389 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 390 ctx->base.is_jmp = DISAS_NORETURN; 391 } 392 393 /* Compute a canonical address from a register plus offset. */ 394 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 395 { 396 TCGv addr = temp_new(ctx); 397 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 398 399 tcg_gen_addi_tl(addr, src1, imm); 400 if (ctx->pm_enabled) { 401 tcg_gen_and_tl(addr, addr, pm_mask); 402 tcg_gen_or_tl(addr, addr, pm_base); 403 } else if (get_xl(ctx) == MXL_RV32) { 404 tcg_gen_ext32u_tl(addr, addr); 405 } 406 return addr; 407 } 408 409 #ifndef CONFIG_USER_ONLY 410 /* The states of mstatus_fs are: 411 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 412 * We will have already diagnosed disabled state, 413 * and need to turn initial/clean into dirty. 414 */ 415 static void mark_fs_dirty(DisasContext *ctx) 416 { 417 TCGv tmp; 418 419 if (ctx->mstatus_fs != MSTATUS_FS) { 420 /* Remember the state change for the rest of the TB. */ 421 ctx->mstatus_fs = MSTATUS_FS; 422 423 tmp = tcg_temp_new(); 424 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 425 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 426 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 427 tcg_temp_free(tmp); 428 } 429 430 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 431 /* Remember the stage change for the rest of the TB. */ 432 ctx->mstatus_hs_fs = MSTATUS_FS; 433 434 tmp = tcg_temp_new(); 435 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 436 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 437 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 438 tcg_temp_free(tmp); 439 } 440 } 441 #else 442 static inline void mark_fs_dirty(DisasContext *ctx) { } 443 #endif 444 445 #ifndef CONFIG_USER_ONLY 446 /* The states of mstatus_vs are: 447 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 448 * We will have already diagnosed disabled state, 449 * and need to turn initial/clean into dirty. 450 */ 451 static void mark_vs_dirty(DisasContext *ctx) 452 { 453 TCGv tmp; 454 455 if (ctx->mstatus_vs != MSTATUS_VS) { 456 /* Remember the state change for the rest of the TB. */ 457 ctx->mstatus_vs = MSTATUS_VS; 458 459 tmp = tcg_temp_new(); 460 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 461 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 462 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 463 tcg_temp_free(tmp); 464 } 465 466 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 467 /* Remember the stage change for the rest of the TB. */ 468 ctx->mstatus_hs_vs = MSTATUS_VS; 469 470 tmp = tcg_temp_new(); 471 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 472 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 473 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 474 tcg_temp_free(tmp); 475 } 476 } 477 #else 478 static inline void mark_vs_dirty(DisasContext *ctx) { } 479 #endif 480 481 static void gen_set_rm(DisasContext *ctx, int rm) 482 { 483 if (ctx->frm == rm) { 484 return; 485 } 486 ctx->frm = rm; 487 488 if (rm == RISCV_FRM_ROD) { 489 gen_helper_set_rod_rounding_mode(cpu_env); 490 return; 491 } 492 493 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 494 } 495 496 static int ex_plus_1(DisasContext *ctx, int nf) 497 { 498 return nf + 1; 499 } 500 501 #define EX_SH(amount) \ 502 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 503 { \ 504 return imm << amount; \ 505 } 506 EX_SH(1) 507 EX_SH(2) 508 EX_SH(3) 509 EX_SH(4) 510 EX_SH(12) 511 512 #define REQUIRE_EXT(ctx, ext) do { \ 513 if (!has_ext(ctx, ext)) { \ 514 return false; \ 515 } \ 516 } while (0) 517 518 #define REQUIRE_32BIT(ctx) do { \ 519 if (get_xl(ctx) != MXL_RV32) { \ 520 return false; \ 521 } \ 522 } while (0) 523 524 #define REQUIRE_64BIT(ctx) do { \ 525 if (get_xl(ctx) != MXL_RV64) { \ 526 return false; \ 527 } \ 528 } while (0) 529 530 #define REQUIRE_128BIT(ctx) do { \ 531 if (get_xl(ctx) != MXL_RV128) { \ 532 return false; \ 533 } \ 534 } while (0) 535 536 #define REQUIRE_64_OR_128BIT(ctx) do { \ 537 if (get_xl(ctx) == MXL_RV32) { \ 538 return false; \ 539 } \ 540 } while (0) 541 542 static int ex_rvc_register(DisasContext *ctx, int reg) 543 { 544 return 8 + reg; 545 } 546 547 static int ex_rvc_shifti(DisasContext *ctx, int imm) 548 { 549 /* For RV128 a shamt of 0 means a shift by 64. */ 550 return imm ? imm : 64; 551 } 552 553 /* Include the auto-generated decoder for 32 bit insn */ 554 #include "decode-insn32.c.inc" 555 556 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 557 void (*func)(TCGv, TCGv, target_long)) 558 { 559 TCGv dest = dest_gpr(ctx, a->rd); 560 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 561 562 func(dest, src1, a->imm); 563 564 if (get_xl(ctx) == MXL_RV128) { 565 TCGv src1h = get_gprh(ctx, a->rs1); 566 TCGv desth = dest_gprh(ctx, a->rd); 567 568 func(desth, src1h, -(a->imm < 0)); 569 gen_set_gpr128(ctx, a->rd, dest, desth); 570 } else { 571 gen_set_gpr(ctx, a->rd, dest); 572 } 573 574 return true; 575 } 576 577 static bool gen_logic(DisasContext *ctx, arg_r *a, 578 void (*func)(TCGv, TCGv, TCGv)) 579 { 580 TCGv dest = dest_gpr(ctx, a->rd); 581 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 582 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 583 584 func(dest, src1, src2); 585 586 if (get_xl(ctx) == MXL_RV128) { 587 TCGv src1h = get_gprh(ctx, a->rs1); 588 TCGv src2h = get_gprh(ctx, a->rs2); 589 TCGv desth = dest_gprh(ctx, a->rd); 590 591 func(desth, src1h, src2h); 592 gen_set_gpr128(ctx, a->rd, dest, desth); 593 } else { 594 gen_set_gpr(ctx, a->rd, dest); 595 } 596 597 return true; 598 } 599 600 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 601 void (*func)(TCGv, TCGv, target_long), 602 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 603 { 604 TCGv dest = dest_gpr(ctx, a->rd); 605 TCGv src1 = get_gpr(ctx, a->rs1, ext); 606 607 if (get_ol(ctx) < MXL_RV128) { 608 func(dest, src1, a->imm); 609 gen_set_gpr(ctx, a->rd, dest); 610 } else { 611 if (f128 == NULL) { 612 return false; 613 } 614 615 TCGv src1h = get_gprh(ctx, a->rs1); 616 TCGv desth = dest_gprh(ctx, a->rd); 617 618 f128(dest, desth, src1, src1h, a->imm); 619 gen_set_gpr128(ctx, a->rd, dest, desth); 620 } 621 return true; 622 } 623 624 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 625 void (*func)(TCGv, TCGv, TCGv), 626 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 627 { 628 TCGv dest = dest_gpr(ctx, a->rd); 629 TCGv src1 = get_gpr(ctx, a->rs1, ext); 630 TCGv src2 = tcg_constant_tl(a->imm); 631 632 if (get_ol(ctx) < MXL_RV128) { 633 func(dest, src1, src2); 634 gen_set_gpr(ctx, a->rd, dest); 635 } else { 636 if (f128 == NULL) { 637 return false; 638 } 639 640 TCGv src1h = get_gprh(ctx, a->rs1); 641 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 642 TCGv desth = dest_gprh(ctx, a->rd); 643 644 f128(dest, desth, src1, src1h, src2, src2h); 645 gen_set_gpr128(ctx, a->rd, dest, desth); 646 } 647 return true; 648 } 649 650 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 651 void (*func)(TCGv, TCGv, TCGv), 652 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 653 { 654 TCGv dest = dest_gpr(ctx, a->rd); 655 TCGv src1 = get_gpr(ctx, a->rs1, ext); 656 TCGv src2 = get_gpr(ctx, a->rs2, ext); 657 658 if (get_ol(ctx) < MXL_RV128) { 659 func(dest, src1, src2); 660 gen_set_gpr(ctx, a->rd, dest); 661 } else { 662 if (f128 == NULL) { 663 return false; 664 } 665 666 TCGv src1h = get_gprh(ctx, a->rs1); 667 TCGv src2h = get_gprh(ctx, a->rs2); 668 TCGv desth = dest_gprh(ctx, a->rd); 669 670 f128(dest, desth, src1, src1h, src2, src2h); 671 gen_set_gpr128(ctx, a->rd, dest, desth); 672 } 673 return true; 674 } 675 676 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 677 void (*f_tl)(TCGv, TCGv, TCGv), 678 void (*f_32)(TCGv, TCGv, TCGv), 679 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 680 { 681 int olen = get_olen(ctx); 682 683 if (olen != TARGET_LONG_BITS) { 684 if (olen == 32) { 685 f_tl = f_32; 686 } else if (olen != 128) { 687 g_assert_not_reached(); 688 } 689 } 690 return gen_arith(ctx, a, ext, f_tl, f_128); 691 } 692 693 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 694 void (*func)(TCGv, TCGv, target_long), 695 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 696 { 697 TCGv dest, src1; 698 int max_len = get_olen(ctx); 699 700 if (a->shamt >= max_len) { 701 return false; 702 } 703 704 dest = dest_gpr(ctx, a->rd); 705 src1 = get_gpr(ctx, a->rs1, ext); 706 707 if (max_len < 128) { 708 func(dest, src1, a->shamt); 709 gen_set_gpr(ctx, a->rd, dest); 710 } else { 711 TCGv src1h = get_gprh(ctx, a->rs1); 712 TCGv desth = dest_gprh(ctx, a->rd); 713 714 if (f128 == NULL) { 715 return false; 716 } 717 f128(dest, desth, src1, src1h, a->shamt); 718 gen_set_gpr128(ctx, a->rd, dest, desth); 719 } 720 return true; 721 } 722 723 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 724 DisasExtend ext, 725 void (*f_tl)(TCGv, TCGv, target_long), 726 void (*f_32)(TCGv, TCGv, target_long), 727 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 728 target_long)) 729 { 730 int olen = get_olen(ctx); 731 if (olen != TARGET_LONG_BITS) { 732 if (olen == 32) { 733 f_tl = f_32; 734 } else if (olen != 128) { 735 g_assert_not_reached(); 736 } 737 } 738 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 739 } 740 741 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 742 void (*func)(TCGv, TCGv, TCGv)) 743 { 744 TCGv dest, src1, src2; 745 int max_len = get_olen(ctx); 746 747 if (a->shamt >= max_len) { 748 return false; 749 } 750 751 dest = dest_gpr(ctx, a->rd); 752 src1 = get_gpr(ctx, a->rs1, ext); 753 src2 = tcg_constant_tl(a->shamt); 754 755 func(dest, src1, src2); 756 757 gen_set_gpr(ctx, a->rd, dest); 758 return true; 759 } 760 761 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 762 void (*func)(TCGv, TCGv, TCGv), 763 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 764 { 765 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 766 TCGv ext2 = tcg_temp_new(); 767 int max_len = get_olen(ctx); 768 769 tcg_gen_andi_tl(ext2, src2, max_len - 1); 770 771 TCGv dest = dest_gpr(ctx, a->rd); 772 TCGv src1 = get_gpr(ctx, a->rs1, ext); 773 774 if (max_len < 128) { 775 func(dest, src1, ext2); 776 gen_set_gpr(ctx, a->rd, dest); 777 } else { 778 TCGv src1h = get_gprh(ctx, a->rs1); 779 TCGv desth = dest_gprh(ctx, a->rd); 780 781 if (f128 == NULL) { 782 return false; 783 } 784 f128(dest, desth, src1, src1h, ext2); 785 gen_set_gpr128(ctx, a->rd, dest, desth); 786 } 787 tcg_temp_free(ext2); 788 return true; 789 } 790 791 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 792 void (*f_tl)(TCGv, TCGv, TCGv), 793 void (*f_32)(TCGv, TCGv, TCGv), 794 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 795 { 796 int olen = get_olen(ctx); 797 if (olen != TARGET_LONG_BITS) { 798 if (olen == 32) { 799 f_tl = f_32; 800 } else if (olen != 128) { 801 g_assert_not_reached(); 802 } 803 } 804 return gen_shift(ctx, a, ext, f_tl, f_128); 805 } 806 807 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 808 void (*func)(TCGv, TCGv)) 809 { 810 TCGv dest = dest_gpr(ctx, a->rd); 811 TCGv src1 = get_gpr(ctx, a->rs1, ext); 812 813 func(dest, src1); 814 815 gen_set_gpr(ctx, a->rd, dest); 816 return true; 817 } 818 819 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 820 void (*f_tl)(TCGv, TCGv), 821 void (*f_32)(TCGv, TCGv)) 822 { 823 int olen = get_olen(ctx); 824 825 if (olen != TARGET_LONG_BITS) { 826 if (olen == 32) { 827 f_tl = f_32; 828 } else { 829 g_assert_not_reached(); 830 } 831 } 832 return gen_unary(ctx, a, ext, f_tl); 833 } 834 835 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 836 { 837 DisasContext *ctx = container_of(dcbase, DisasContext, base); 838 CPUState *cpu = ctx->cs; 839 CPURISCVState *env = cpu->env_ptr; 840 841 return cpu_ldl_code(env, pc); 842 } 843 844 /* Include insn module translation function */ 845 #include "insn_trans/trans_rvi.c.inc" 846 #include "insn_trans/trans_rvm.c.inc" 847 #include "insn_trans/trans_rva.c.inc" 848 #include "insn_trans/trans_rvf.c.inc" 849 #include "insn_trans/trans_rvd.c.inc" 850 #include "insn_trans/trans_rvh.c.inc" 851 #include "insn_trans/trans_rvv.c.inc" 852 #include "insn_trans/trans_rvb.c.inc" 853 #include "insn_trans/trans_rvzfh.c.inc" 854 #include "insn_trans/trans_privileged.c.inc" 855 856 /* Include the auto-generated decoder for 16 bit insn */ 857 #include "decode-insn16.c.inc" 858 859 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 860 { 861 /* check for compressed insn */ 862 if (extract16(opcode, 0, 2) != 3) { 863 if (!has_ext(ctx, RVC)) { 864 gen_exception_illegal(ctx); 865 } else { 866 ctx->opcode = opcode; 867 ctx->pc_succ_insn = ctx->base.pc_next + 2; 868 if (!decode_insn16(ctx, opcode)) { 869 gen_exception_illegal(ctx); 870 } 871 } 872 } else { 873 uint32_t opcode32 = opcode; 874 opcode32 = deposit32(opcode32, 16, 16, 875 translator_lduw(env, &ctx->base, 876 ctx->base.pc_next + 2)); 877 ctx->opcode = opcode32; 878 ctx->pc_succ_insn = ctx->base.pc_next + 4; 879 if (!decode_insn32(ctx, opcode32)) { 880 gen_exception_illegal(ctx); 881 } 882 } 883 } 884 885 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 886 { 887 DisasContext *ctx = container_of(dcbase, DisasContext, base); 888 CPURISCVState *env = cs->env_ptr; 889 RISCVCPU *cpu = RISCV_CPU(cs); 890 uint32_t tb_flags = ctx->base.tb->flags; 891 892 ctx->pc_succ_insn = ctx->base.pc_first; 893 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 894 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 895 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 896 ctx->priv_ver = env->priv_ver; 897 #if !defined(CONFIG_USER_ONLY) 898 if (riscv_has_ext(env, RVH)) { 899 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 900 } else { 901 ctx->virt_enabled = false; 902 } 903 #else 904 ctx->virt_enabled = false; 905 #endif 906 ctx->misa_ext = env->misa_ext; 907 ctx->frm = -1; /* unknown rounding mode */ 908 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 909 ctx->ext_zfh = cpu->cfg.ext_zfh; 910 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 911 ctx->ext_zve32f = cpu->cfg.ext_zve32f; 912 ctx->ext_zve64f = cpu->cfg.ext_zve64f; 913 ctx->vlen = cpu->cfg.vlen; 914 ctx->elen = cpu->cfg.elen; 915 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 916 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 917 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 918 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 919 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 920 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 921 ctx->vstart = env->vstart; 922 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 923 ctx->misa_mxl_max = env->misa_mxl_max; 924 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 925 ctx->cs = cs; 926 ctx->ntemp = 0; 927 memset(ctx->temp, 0, sizeof(ctx->temp)); 928 ctx->pm_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_ENABLED); 929 ctx->zero = tcg_constant_tl(0); 930 } 931 932 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 933 { 934 } 935 936 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 937 { 938 DisasContext *ctx = container_of(dcbase, DisasContext, base); 939 940 tcg_gen_insn_start(ctx->base.pc_next); 941 } 942 943 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 944 { 945 DisasContext *ctx = container_of(dcbase, DisasContext, base); 946 CPURISCVState *env = cpu->env_ptr; 947 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 948 949 ctx->ol = ctx->xl; 950 decode_opc(env, ctx, opcode16); 951 ctx->base.pc_next = ctx->pc_succ_insn; 952 953 for (int i = ctx->ntemp - 1; i >= 0; --i) { 954 tcg_temp_free(ctx->temp[i]); 955 ctx->temp[i] = NULL; 956 } 957 ctx->ntemp = 0; 958 959 if (ctx->base.is_jmp == DISAS_NEXT) { 960 target_ulong page_start; 961 962 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 963 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 964 ctx->base.is_jmp = DISAS_TOO_MANY; 965 } 966 } 967 } 968 969 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 970 { 971 DisasContext *ctx = container_of(dcbase, DisasContext, base); 972 973 switch (ctx->base.is_jmp) { 974 case DISAS_TOO_MANY: 975 gen_goto_tb(ctx, 0, ctx->base.pc_next); 976 break; 977 case DISAS_NORETURN: 978 break; 979 default: 980 g_assert_not_reached(); 981 } 982 } 983 984 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 985 { 986 #ifndef CONFIG_USER_ONLY 987 RISCVCPU *rvcpu = RISCV_CPU(cpu); 988 CPURISCVState *env = &rvcpu->env; 989 #endif 990 991 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 992 #ifndef CONFIG_USER_ONLY 993 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 994 #endif 995 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 996 } 997 998 static const TranslatorOps riscv_tr_ops = { 999 .init_disas_context = riscv_tr_init_disas_context, 1000 .tb_start = riscv_tr_tb_start, 1001 .insn_start = riscv_tr_insn_start, 1002 .translate_insn = riscv_tr_translate_insn, 1003 .tb_stop = riscv_tr_tb_stop, 1004 .disas_log = riscv_tr_disas_log, 1005 }; 1006 1007 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1008 { 1009 DisasContext ctx; 1010 1011 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1012 } 1013 1014 void riscv_translate_init(void) 1015 { 1016 int i; 1017 1018 /* 1019 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1020 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1021 * unless you specifically block reads/writes to reg 0. 1022 */ 1023 cpu_gpr[0] = NULL; 1024 cpu_gprh[0] = NULL; 1025 1026 for (i = 1; i < 32; i++) { 1027 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1028 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1029 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1030 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1031 } 1032 1033 for (i = 0; i < 32; i++) { 1034 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1035 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1036 } 1037 1038 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1039 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1040 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1041 "vstart"); 1042 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1043 "load_res"); 1044 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1045 "load_val"); 1046 /* Assign PM CSRs to tcg globals */ 1047 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1048 "pmmask"); 1049 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1050 "pmbase"); 1051 } 1052