1 /* 2 * RISC-V emulation for qemu: main translation routines. 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/log.h" 21 #include "cpu.h" 22 #include "tcg/tcg-op.h" 23 #include "disas/disas.h" 24 #include "exec/cpu_ldst.h" 25 #include "exec/exec-all.h" 26 #include "exec/helper-proto.h" 27 #include "exec/helper-gen.h" 28 29 #include "exec/translator.h" 30 #include "exec/log.h" 31 32 #include "instmap.h" 33 #include "internals.h" 34 35 /* global register indices */ 36 static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; 37 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ 38 static TCGv load_res; 39 static TCGv load_val; 40 /* globals for PM CSRs */ 41 static TCGv pm_mask; 42 static TCGv pm_base; 43 44 #include "exec/gen-icount.h" 45 46 /* 47 * If an operation is being performed on less than TARGET_LONG_BITS, 48 * it may require the inputs to be sign- or zero-extended; which will 49 * depend on the exact operation being performed. 50 */ 51 typedef enum { 52 EXT_NONE, 53 EXT_SIGN, 54 EXT_ZERO, 55 } DisasExtend; 56 57 typedef struct DisasContext { 58 DisasContextBase base; 59 /* pc_succ_insn points to the instruction following base.pc_next */ 60 target_ulong pc_succ_insn; 61 target_ulong priv_ver; 62 RISCVMXL misa_mxl_max; 63 RISCVMXL xl; 64 uint32_t misa_ext; 65 uint32_t opcode; 66 uint32_t mstatus_fs; 67 uint32_t mstatus_vs; 68 uint32_t mstatus_hs_fs; 69 uint32_t mstatus_hs_vs; 70 uint32_t mem_idx; 71 /* Remember the rounding mode encoded in the previous fp instruction, 72 which we have already installed into env->fp_status. Or -1 for 73 no previous fp instruction. Note that we exit the TB when writing 74 to any system register, which includes CSR_FRM, so we do not have 75 to reset this known value. */ 76 int frm; 77 RISCVMXL ol; 78 bool virt_enabled; 79 bool ext_ifencei; 80 bool ext_zfh; 81 bool ext_zfhmin; 82 bool ext_zve32f; 83 bool ext_zve64f; 84 bool hlsx; 85 /* vector extension */ 86 bool vill; 87 /* 88 * Encode LMUL to lmul as follows: 89 * LMUL vlmul lmul 90 * 1 000 0 91 * 2 001 1 92 * 4 010 2 93 * 8 011 3 94 * - 100 - 95 * 1/8 101 -3 96 * 1/4 110 -2 97 * 1/2 111 -1 98 */ 99 int8_t lmul; 100 uint8_t sew; 101 uint16_t vlen; 102 uint16_t elen; 103 target_ulong vstart; 104 bool vl_eq_vlmax; 105 uint8_t ntemp; 106 CPUState *cs; 107 TCGv zero; 108 /* Space for 3 operands plus 1 extra for address computation. */ 109 TCGv temp[4]; 110 /* PointerMasking extension */ 111 bool pm_mask_enabled; 112 bool pm_base_enabled; 113 } DisasContext; 114 115 static inline bool has_ext(DisasContext *ctx, uint32_t ext) 116 { 117 return ctx->misa_ext & ext; 118 } 119 120 #ifdef TARGET_RISCV32 121 #define get_xl(ctx) MXL_RV32 122 #elif defined(CONFIG_USER_ONLY) 123 #define get_xl(ctx) MXL_RV64 124 #else 125 #define get_xl(ctx) ((ctx)->xl) 126 #endif 127 128 /* The word size for this machine mode. */ 129 static inline int __attribute__((unused)) get_xlen(DisasContext *ctx) 130 { 131 return 16 << get_xl(ctx); 132 } 133 134 /* The operation length, as opposed to the xlen. */ 135 #ifdef TARGET_RISCV32 136 #define get_ol(ctx) MXL_RV32 137 #else 138 #define get_ol(ctx) ((ctx)->ol) 139 #endif 140 141 static inline int get_olen(DisasContext *ctx) 142 { 143 return 16 << get_ol(ctx); 144 } 145 146 /* The maximum register length */ 147 #ifdef TARGET_RISCV32 148 #define get_xl_max(ctx) MXL_RV32 149 #else 150 #define get_xl_max(ctx) ((ctx)->misa_mxl_max) 151 #endif 152 153 /* 154 * RISC-V requires NaN-boxing of narrower width floating point values. 155 * This applies when a 32-bit value is assigned to a 64-bit FP register. 156 * For consistency and simplicity, we nanbox results even when the RVD 157 * extension is not present. 158 */ 159 static void gen_nanbox_s(TCGv_i64 out, TCGv_i64 in) 160 { 161 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(32, 32)); 162 } 163 164 static void gen_nanbox_h(TCGv_i64 out, TCGv_i64 in) 165 { 166 tcg_gen_ori_i64(out, in, MAKE_64BIT_MASK(16, 48)); 167 } 168 169 /* 170 * A narrow n-bit operation, where n < FLEN, checks that input operands 171 * are correctly Nan-boxed, i.e., all upper FLEN - n bits are 1. 172 * If so, the least-significant bits of the input are used, otherwise the 173 * input value is treated as an n-bit canonical NaN (v2.2 section 9.2). 174 * 175 * Here, the result is always nan-boxed, even the canonical nan. 176 */ 177 static void gen_check_nanbox_h(TCGv_i64 out, TCGv_i64 in) 178 { 179 TCGv_i64 t_max = tcg_const_i64(0xffffffffffff0000ull); 180 TCGv_i64 t_nan = tcg_const_i64(0xffffffffffff7e00ull); 181 182 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 183 tcg_temp_free_i64(t_max); 184 tcg_temp_free_i64(t_nan); 185 } 186 187 static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in) 188 { 189 TCGv_i64 t_max = tcg_constant_i64(0xffffffff00000000ull); 190 TCGv_i64 t_nan = tcg_constant_i64(0xffffffff7fc00000ull); 191 192 tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan); 193 } 194 195 static void gen_set_pc_imm(DisasContext *ctx, target_ulong dest) 196 { 197 if (get_xl(ctx) == MXL_RV32) { 198 dest = (int32_t)dest; 199 } 200 tcg_gen_movi_tl(cpu_pc, dest); 201 } 202 203 static void gen_set_pc(DisasContext *ctx, TCGv dest) 204 { 205 if (get_xl(ctx) == MXL_RV32) { 206 tcg_gen_ext32s_tl(cpu_pc, dest); 207 } else { 208 tcg_gen_mov_tl(cpu_pc, dest); 209 } 210 } 211 212 static void generate_exception(DisasContext *ctx, int excp) 213 { 214 gen_set_pc_imm(ctx, ctx->base.pc_next); 215 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 216 ctx->base.is_jmp = DISAS_NORETURN; 217 } 218 219 static void generate_exception_mtval(DisasContext *ctx, int excp) 220 { 221 gen_set_pc_imm(ctx, ctx->base.pc_next); 222 tcg_gen_st_tl(cpu_pc, cpu_env, offsetof(CPURISCVState, badaddr)); 223 gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp)); 224 ctx->base.is_jmp = DISAS_NORETURN; 225 } 226 227 static void gen_exception_illegal(DisasContext *ctx) 228 { 229 tcg_gen_st_i32(tcg_constant_i32(ctx->opcode), cpu_env, 230 offsetof(CPURISCVState, bins)); 231 232 generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); 233 } 234 235 static void gen_exception_inst_addr_mis(DisasContext *ctx) 236 { 237 generate_exception_mtval(ctx, RISCV_EXCP_INST_ADDR_MIS); 238 } 239 240 static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) 241 { 242 if (translator_use_goto_tb(&ctx->base, dest)) { 243 tcg_gen_goto_tb(n); 244 gen_set_pc_imm(ctx, dest); 245 tcg_gen_exit_tb(ctx->base.tb, n); 246 } else { 247 gen_set_pc_imm(ctx, dest); 248 tcg_gen_lookup_and_goto_ptr(); 249 } 250 } 251 252 /* 253 * Wrappers for getting reg values. 254 * 255 * The $zero register does not have cpu_gpr[0] allocated -- we supply the 256 * constant zero as a source, and an uninitialized sink as destination. 257 * 258 * Further, we may provide an extension for word operations. 259 */ 260 static TCGv temp_new(DisasContext *ctx) 261 { 262 assert(ctx->ntemp < ARRAY_SIZE(ctx->temp)); 263 return ctx->temp[ctx->ntemp++] = tcg_temp_new(); 264 } 265 266 static TCGv get_gpr(DisasContext *ctx, int reg_num, DisasExtend ext) 267 { 268 TCGv t; 269 270 if (reg_num == 0) { 271 return ctx->zero; 272 } 273 274 switch (get_ol(ctx)) { 275 case MXL_RV32: 276 switch (ext) { 277 case EXT_NONE: 278 break; 279 case EXT_SIGN: 280 t = temp_new(ctx); 281 tcg_gen_ext32s_tl(t, cpu_gpr[reg_num]); 282 return t; 283 case EXT_ZERO: 284 t = temp_new(ctx); 285 tcg_gen_ext32u_tl(t, cpu_gpr[reg_num]); 286 return t; 287 default: 288 g_assert_not_reached(); 289 } 290 break; 291 case MXL_RV64: 292 case MXL_RV128: 293 break; 294 default: 295 g_assert_not_reached(); 296 } 297 return cpu_gpr[reg_num]; 298 } 299 300 static TCGv get_gprh(DisasContext *ctx, int reg_num) 301 { 302 assert(get_xl(ctx) == MXL_RV128); 303 if (reg_num == 0) { 304 return ctx->zero; 305 } 306 return cpu_gprh[reg_num]; 307 } 308 309 static TCGv dest_gpr(DisasContext *ctx, int reg_num) 310 { 311 if (reg_num == 0 || get_olen(ctx) < TARGET_LONG_BITS) { 312 return temp_new(ctx); 313 } 314 return cpu_gpr[reg_num]; 315 } 316 317 static TCGv dest_gprh(DisasContext *ctx, int reg_num) 318 { 319 if (reg_num == 0) { 320 return temp_new(ctx); 321 } 322 return cpu_gprh[reg_num]; 323 } 324 325 static void gen_set_gpr(DisasContext *ctx, int reg_num, TCGv t) 326 { 327 if (reg_num != 0) { 328 switch (get_ol(ctx)) { 329 case MXL_RV32: 330 tcg_gen_ext32s_tl(cpu_gpr[reg_num], t); 331 break; 332 case MXL_RV64: 333 case MXL_RV128: 334 tcg_gen_mov_tl(cpu_gpr[reg_num], t); 335 break; 336 default: 337 g_assert_not_reached(); 338 } 339 340 if (get_xl_max(ctx) == MXL_RV128) { 341 tcg_gen_sari_tl(cpu_gprh[reg_num], cpu_gpr[reg_num], 63); 342 } 343 } 344 } 345 346 static void gen_set_gpri(DisasContext *ctx, int reg_num, target_long imm) 347 { 348 if (reg_num != 0) { 349 switch (get_ol(ctx)) { 350 case MXL_RV32: 351 tcg_gen_movi_tl(cpu_gpr[reg_num], (int32_t)imm); 352 break; 353 case MXL_RV64: 354 case MXL_RV128: 355 tcg_gen_movi_tl(cpu_gpr[reg_num], imm); 356 break; 357 default: 358 g_assert_not_reached(); 359 } 360 361 if (get_xl_max(ctx) == MXL_RV128) { 362 tcg_gen_movi_tl(cpu_gprh[reg_num], -(imm < 0)); 363 } 364 } 365 } 366 367 static void gen_set_gpr128(DisasContext *ctx, int reg_num, TCGv rl, TCGv rh) 368 { 369 assert(get_ol(ctx) == MXL_RV128); 370 if (reg_num != 0) { 371 tcg_gen_mov_tl(cpu_gpr[reg_num], rl); 372 tcg_gen_mov_tl(cpu_gprh[reg_num], rh); 373 } 374 } 375 376 static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) 377 { 378 target_ulong next_pc; 379 380 /* check misaligned: */ 381 next_pc = ctx->base.pc_next + imm; 382 if (!has_ext(ctx, RVC)) { 383 if ((next_pc & 0x3) != 0) { 384 gen_exception_inst_addr_mis(ctx); 385 return; 386 } 387 } 388 389 gen_set_gpri(ctx, rd, ctx->pc_succ_insn); 390 gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ 391 ctx->base.is_jmp = DISAS_NORETURN; 392 } 393 394 /* Compute a canonical address from a register plus offset. */ 395 static TCGv get_address(DisasContext *ctx, int rs1, int imm) 396 { 397 TCGv addr = temp_new(ctx); 398 TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); 399 400 tcg_gen_addi_tl(addr, src1, imm); 401 if (ctx->pm_mask_enabled) { 402 tcg_gen_and_tl(addr, addr, pm_mask); 403 } else if (get_xl(ctx) == MXL_RV32) { 404 tcg_gen_ext32u_tl(addr, addr); 405 } 406 if (ctx->pm_base_enabled) { 407 tcg_gen_or_tl(addr, addr, pm_base); 408 } 409 return addr; 410 } 411 412 #ifndef CONFIG_USER_ONLY 413 /* The states of mstatus_fs are: 414 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 415 * We will have already diagnosed disabled state, 416 * and need to turn initial/clean into dirty. 417 */ 418 static void mark_fs_dirty(DisasContext *ctx) 419 { 420 TCGv tmp; 421 422 if (ctx->mstatus_fs != MSTATUS_FS) { 423 /* Remember the state change for the rest of the TB. */ 424 ctx->mstatus_fs = MSTATUS_FS; 425 426 tmp = tcg_temp_new(); 427 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 428 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 429 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 430 tcg_temp_free(tmp); 431 } 432 433 if (ctx->virt_enabled && ctx->mstatus_hs_fs != MSTATUS_FS) { 434 /* Remember the stage change for the rest of the TB. */ 435 ctx->mstatus_hs_fs = MSTATUS_FS; 436 437 tmp = tcg_temp_new(); 438 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 439 tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); 440 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 441 tcg_temp_free(tmp); 442 } 443 } 444 #else 445 static inline void mark_fs_dirty(DisasContext *ctx) { } 446 #endif 447 448 #ifndef CONFIG_USER_ONLY 449 /* The states of mstatus_vs are: 450 * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty 451 * We will have already diagnosed disabled state, 452 * and need to turn initial/clean into dirty. 453 */ 454 static void mark_vs_dirty(DisasContext *ctx) 455 { 456 TCGv tmp; 457 458 if (ctx->mstatus_vs != MSTATUS_VS) { 459 /* Remember the state change for the rest of the TB. */ 460 ctx->mstatus_vs = MSTATUS_VS; 461 462 tmp = tcg_temp_new(); 463 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 464 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 465 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); 466 tcg_temp_free(tmp); 467 } 468 469 if (ctx->virt_enabled && ctx->mstatus_hs_vs != MSTATUS_VS) { 470 /* Remember the stage change for the rest of the TB. */ 471 ctx->mstatus_hs_vs = MSTATUS_VS; 472 473 tmp = tcg_temp_new(); 474 tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 475 tcg_gen_ori_tl(tmp, tmp, MSTATUS_VS); 476 tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs)); 477 tcg_temp_free(tmp); 478 } 479 } 480 #else 481 static inline void mark_vs_dirty(DisasContext *ctx) { } 482 #endif 483 484 static void gen_set_rm(DisasContext *ctx, int rm) 485 { 486 if (ctx->frm == rm) { 487 return; 488 } 489 ctx->frm = rm; 490 491 if (rm == RISCV_FRM_ROD) { 492 gen_helper_set_rod_rounding_mode(cpu_env); 493 return; 494 } 495 496 gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); 497 } 498 499 static int ex_plus_1(DisasContext *ctx, int nf) 500 { 501 return nf + 1; 502 } 503 504 #define EX_SH(amount) \ 505 static int ex_shift_##amount(DisasContext *ctx, int imm) \ 506 { \ 507 return imm << amount; \ 508 } 509 EX_SH(1) 510 EX_SH(2) 511 EX_SH(3) 512 EX_SH(4) 513 EX_SH(12) 514 515 #define REQUIRE_EXT(ctx, ext) do { \ 516 if (!has_ext(ctx, ext)) { \ 517 return false; \ 518 } \ 519 } while (0) 520 521 #define REQUIRE_32BIT(ctx) do { \ 522 if (get_xl(ctx) != MXL_RV32) { \ 523 return false; \ 524 } \ 525 } while (0) 526 527 #define REQUIRE_64BIT(ctx) do { \ 528 if (get_xl(ctx) != MXL_RV64) { \ 529 return false; \ 530 } \ 531 } while (0) 532 533 #define REQUIRE_128BIT(ctx) do { \ 534 if (get_xl(ctx) != MXL_RV128) { \ 535 return false; \ 536 } \ 537 } while (0) 538 539 #define REQUIRE_64_OR_128BIT(ctx) do { \ 540 if (get_xl(ctx) == MXL_RV32) { \ 541 return false; \ 542 } \ 543 } while (0) 544 545 static int ex_rvc_register(DisasContext *ctx, int reg) 546 { 547 return 8 + reg; 548 } 549 550 static int ex_rvc_shifti(DisasContext *ctx, int imm) 551 { 552 /* For RV128 a shamt of 0 means a shift by 64. */ 553 return imm ? imm : 64; 554 } 555 556 /* Include the auto-generated decoder for 32 bit insn */ 557 #include "decode-insn32.c.inc" 558 559 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, 560 void (*func)(TCGv, TCGv, target_long)) 561 { 562 TCGv dest = dest_gpr(ctx, a->rd); 563 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 564 565 func(dest, src1, a->imm); 566 567 if (get_xl(ctx) == MXL_RV128) { 568 TCGv src1h = get_gprh(ctx, a->rs1); 569 TCGv desth = dest_gprh(ctx, a->rd); 570 571 func(desth, src1h, -(a->imm < 0)); 572 gen_set_gpr128(ctx, a->rd, dest, desth); 573 } else { 574 gen_set_gpr(ctx, a->rd, dest); 575 } 576 577 return true; 578 } 579 580 static bool gen_logic(DisasContext *ctx, arg_r *a, 581 void (*func)(TCGv, TCGv, TCGv)) 582 { 583 TCGv dest = dest_gpr(ctx, a->rd); 584 TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); 585 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 586 587 func(dest, src1, src2); 588 589 if (get_xl(ctx) == MXL_RV128) { 590 TCGv src1h = get_gprh(ctx, a->rs1); 591 TCGv src2h = get_gprh(ctx, a->rs2); 592 TCGv desth = dest_gprh(ctx, a->rd); 593 594 func(desth, src1h, src2h); 595 gen_set_gpr128(ctx, a->rd, dest, desth); 596 } else { 597 gen_set_gpr(ctx, a->rd, dest); 598 } 599 600 return true; 601 } 602 603 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a, DisasExtend ext, 604 void (*func)(TCGv, TCGv, target_long), 605 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 606 { 607 TCGv dest = dest_gpr(ctx, a->rd); 608 TCGv src1 = get_gpr(ctx, a->rs1, ext); 609 610 if (get_ol(ctx) < MXL_RV128) { 611 func(dest, src1, a->imm); 612 gen_set_gpr(ctx, a->rd, dest); 613 } else { 614 if (f128 == NULL) { 615 return false; 616 } 617 618 TCGv src1h = get_gprh(ctx, a->rs1); 619 TCGv desth = dest_gprh(ctx, a->rd); 620 621 f128(dest, desth, src1, src1h, a->imm); 622 gen_set_gpr128(ctx, a->rd, dest, desth); 623 } 624 return true; 625 } 626 627 static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a, DisasExtend ext, 628 void (*func)(TCGv, TCGv, TCGv), 629 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 630 { 631 TCGv dest = dest_gpr(ctx, a->rd); 632 TCGv src1 = get_gpr(ctx, a->rs1, ext); 633 TCGv src2 = tcg_constant_tl(a->imm); 634 635 if (get_ol(ctx) < MXL_RV128) { 636 func(dest, src1, src2); 637 gen_set_gpr(ctx, a->rd, dest); 638 } else { 639 if (f128 == NULL) { 640 return false; 641 } 642 643 TCGv src1h = get_gprh(ctx, a->rs1); 644 TCGv src2h = tcg_constant_tl(-(a->imm < 0)); 645 TCGv desth = dest_gprh(ctx, a->rd); 646 647 f128(dest, desth, src1, src1h, src2, src2h); 648 gen_set_gpr128(ctx, a->rd, dest, desth); 649 } 650 return true; 651 } 652 653 static bool gen_arith(DisasContext *ctx, arg_r *a, DisasExtend ext, 654 void (*func)(TCGv, TCGv, TCGv), 655 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 656 { 657 TCGv dest = dest_gpr(ctx, a->rd); 658 TCGv src1 = get_gpr(ctx, a->rs1, ext); 659 TCGv src2 = get_gpr(ctx, a->rs2, ext); 660 661 if (get_ol(ctx) < MXL_RV128) { 662 func(dest, src1, src2); 663 gen_set_gpr(ctx, a->rd, dest); 664 } else { 665 if (f128 == NULL) { 666 return false; 667 } 668 669 TCGv src1h = get_gprh(ctx, a->rs1); 670 TCGv src2h = get_gprh(ctx, a->rs2); 671 TCGv desth = dest_gprh(ctx, a->rd); 672 673 f128(dest, desth, src1, src1h, src2, src2h); 674 gen_set_gpr128(ctx, a->rd, dest, desth); 675 } 676 return true; 677 } 678 679 static bool gen_arith_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 680 void (*f_tl)(TCGv, TCGv, TCGv), 681 void (*f_32)(TCGv, TCGv, TCGv), 682 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv, TCGv)) 683 { 684 int olen = get_olen(ctx); 685 686 if (olen != TARGET_LONG_BITS) { 687 if (olen == 32) { 688 f_tl = f_32; 689 } else if (olen != 128) { 690 g_assert_not_reached(); 691 } 692 } 693 return gen_arith(ctx, a, ext, f_tl, f_128); 694 } 695 696 static bool gen_shift_imm_fn(DisasContext *ctx, arg_shift *a, DisasExtend ext, 697 void (*func)(TCGv, TCGv, target_long), 698 void (*f128)(TCGv, TCGv, TCGv, TCGv, target_long)) 699 { 700 TCGv dest, src1; 701 int max_len = get_olen(ctx); 702 703 if (a->shamt >= max_len) { 704 return false; 705 } 706 707 dest = dest_gpr(ctx, a->rd); 708 src1 = get_gpr(ctx, a->rs1, ext); 709 710 if (max_len < 128) { 711 func(dest, src1, a->shamt); 712 gen_set_gpr(ctx, a->rd, dest); 713 } else { 714 TCGv src1h = get_gprh(ctx, a->rs1); 715 TCGv desth = dest_gprh(ctx, a->rd); 716 717 if (f128 == NULL) { 718 return false; 719 } 720 f128(dest, desth, src1, src1h, a->shamt); 721 gen_set_gpr128(ctx, a->rd, dest, desth); 722 } 723 return true; 724 } 725 726 static bool gen_shift_imm_fn_per_ol(DisasContext *ctx, arg_shift *a, 727 DisasExtend ext, 728 void (*f_tl)(TCGv, TCGv, target_long), 729 void (*f_32)(TCGv, TCGv, target_long), 730 void (*f_128)(TCGv, TCGv, TCGv, TCGv, 731 target_long)) 732 { 733 int olen = get_olen(ctx); 734 if (olen != TARGET_LONG_BITS) { 735 if (olen == 32) { 736 f_tl = f_32; 737 } else if (olen != 128) { 738 g_assert_not_reached(); 739 } 740 } 741 return gen_shift_imm_fn(ctx, a, ext, f_tl, f_128); 742 } 743 744 static bool gen_shift_imm_tl(DisasContext *ctx, arg_shift *a, DisasExtend ext, 745 void (*func)(TCGv, TCGv, TCGv)) 746 { 747 TCGv dest, src1, src2; 748 int max_len = get_olen(ctx); 749 750 if (a->shamt >= max_len) { 751 return false; 752 } 753 754 dest = dest_gpr(ctx, a->rd); 755 src1 = get_gpr(ctx, a->rs1, ext); 756 src2 = tcg_constant_tl(a->shamt); 757 758 func(dest, src1, src2); 759 760 gen_set_gpr(ctx, a->rd, dest); 761 return true; 762 } 763 764 static bool gen_shift(DisasContext *ctx, arg_r *a, DisasExtend ext, 765 void (*func)(TCGv, TCGv, TCGv), 766 void (*f128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 767 { 768 TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); 769 TCGv ext2 = tcg_temp_new(); 770 int max_len = get_olen(ctx); 771 772 tcg_gen_andi_tl(ext2, src2, max_len - 1); 773 774 TCGv dest = dest_gpr(ctx, a->rd); 775 TCGv src1 = get_gpr(ctx, a->rs1, ext); 776 777 if (max_len < 128) { 778 func(dest, src1, ext2); 779 gen_set_gpr(ctx, a->rd, dest); 780 } else { 781 TCGv src1h = get_gprh(ctx, a->rs1); 782 TCGv desth = dest_gprh(ctx, a->rd); 783 784 if (f128 == NULL) { 785 return false; 786 } 787 f128(dest, desth, src1, src1h, ext2); 788 gen_set_gpr128(ctx, a->rd, dest, desth); 789 } 790 tcg_temp_free(ext2); 791 return true; 792 } 793 794 static bool gen_shift_per_ol(DisasContext *ctx, arg_r *a, DisasExtend ext, 795 void (*f_tl)(TCGv, TCGv, TCGv), 796 void (*f_32)(TCGv, TCGv, TCGv), 797 void (*f_128)(TCGv, TCGv, TCGv, TCGv, TCGv)) 798 { 799 int olen = get_olen(ctx); 800 if (olen != TARGET_LONG_BITS) { 801 if (olen == 32) { 802 f_tl = f_32; 803 } else if (olen != 128) { 804 g_assert_not_reached(); 805 } 806 } 807 return gen_shift(ctx, a, ext, f_tl, f_128); 808 } 809 810 static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 811 void (*func)(TCGv, TCGv)) 812 { 813 TCGv dest = dest_gpr(ctx, a->rd); 814 TCGv src1 = get_gpr(ctx, a->rs1, ext); 815 816 func(dest, src1); 817 818 gen_set_gpr(ctx, a->rd, dest); 819 return true; 820 } 821 822 static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext, 823 void (*f_tl)(TCGv, TCGv), 824 void (*f_32)(TCGv, TCGv)) 825 { 826 int olen = get_olen(ctx); 827 828 if (olen != TARGET_LONG_BITS) { 829 if (olen == 32) { 830 f_tl = f_32; 831 } else { 832 g_assert_not_reached(); 833 } 834 } 835 return gen_unary(ctx, a, ext, f_tl); 836 } 837 838 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) 839 { 840 DisasContext *ctx = container_of(dcbase, DisasContext, base); 841 CPUState *cpu = ctx->cs; 842 CPURISCVState *env = cpu->env_ptr; 843 844 return cpu_ldl_code(env, pc); 845 } 846 847 /* Include insn module translation function */ 848 #include "insn_trans/trans_rvi.c.inc" 849 #include "insn_trans/trans_rvm.c.inc" 850 #include "insn_trans/trans_rva.c.inc" 851 #include "insn_trans/trans_rvf.c.inc" 852 #include "insn_trans/trans_rvd.c.inc" 853 #include "insn_trans/trans_rvh.c.inc" 854 #include "insn_trans/trans_rvv.c.inc" 855 #include "insn_trans/trans_rvb.c.inc" 856 #include "insn_trans/trans_rvzfh.c.inc" 857 #include "insn_trans/trans_privileged.c.inc" 858 859 /* Include the auto-generated decoder for 16 bit insn */ 860 #include "decode-insn16.c.inc" 861 862 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) 863 { 864 /* check for compressed insn */ 865 if (extract16(opcode, 0, 2) != 3) { 866 if (!has_ext(ctx, RVC)) { 867 gen_exception_illegal(ctx); 868 } else { 869 ctx->opcode = opcode; 870 ctx->pc_succ_insn = ctx->base.pc_next + 2; 871 if (!decode_insn16(ctx, opcode)) { 872 gen_exception_illegal(ctx); 873 } 874 } 875 } else { 876 uint32_t opcode32 = opcode; 877 opcode32 = deposit32(opcode32, 16, 16, 878 translator_lduw(env, &ctx->base, 879 ctx->base.pc_next + 2)); 880 ctx->opcode = opcode32; 881 ctx->pc_succ_insn = ctx->base.pc_next + 4; 882 if (!decode_insn32(ctx, opcode32)) { 883 gen_exception_illegal(ctx); 884 } 885 } 886 } 887 888 static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) 889 { 890 DisasContext *ctx = container_of(dcbase, DisasContext, base); 891 CPURISCVState *env = cs->env_ptr; 892 RISCVCPU *cpu = RISCV_CPU(cs); 893 uint32_t tb_flags = ctx->base.tb->flags; 894 895 ctx->pc_succ_insn = ctx->base.pc_first; 896 ctx->mem_idx = FIELD_EX32(tb_flags, TB_FLAGS, MEM_IDX); 897 ctx->mstatus_fs = tb_flags & TB_FLAGS_MSTATUS_FS; 898 ctx->mstatus_vs = tb_flags & TB_FLAGS_MSTATUS_VS; 899 ctx->priv_ver = env->priv_ver; 900 #if !defined(CONFIG_USER_ONLY) 901 if (riscv_has_ext(env, RVH)) { 902 ctx->virt_enabled = riscv_cpu_virt_enabled(env); 903 } else { 904 ctx->virt_enabled = false; 905 } 906 #else 907 ctx->virt_enabled = false; 908 #endif 909 ctx->misa_ext = env->misa_ext; 910 ctx->frm = -1; /* unknown rounding mode */ 911 ctx->ext_ifencei = cpu->cfg.ext_ifencei; 912 ctx->ext_zfh = cpu->cfg.ext_zfh; 913 ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; 914 ctx->ext_zve32f = cpu->cfg.ext_zve32f; 915 ctx->ext_zve64f = cpu->cfg.ext_zve64f; 916 ctx->vlen = cpu->cfg.vlen; 917 ctx->elen = cpu->cfg.elen; 918 ctx->mstatus_hs_fs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_FS); 919 ctx->mstatus_hs_vs = FIELD_EX32(tb_flags, TB_FLAGS, MSTATUS_HS_VS); 920 ctx->hlsx = FIELD_EX32(tb_flags, TB_FLAGS, HLSX); 921 ctx->vill = FIELD_EX32(tb_flags, TB_FLAGS, VILL); 922 ctx->sew = FIELD_EX32(tb_flags, TB_FLAGS, SEW); 923 ctx->lmul = sextract32(FIELD_EX32(tb_flags, TB_FLAGS, LMUL), 0, 3); 924 ctx->vstart = env->vstart; 925 ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); 926 ctx->misa_mxl_max = env->misa_mxl_max; 927 ctx->xl = FIELD_EX32(tb_flags, TB_FLAGS, XL); 928 ctx->cs = cs; 929 ctx->ntemp = 0; 930 memset(ctx->temp, 0, sizeof(ctx->temp)); 931 ctx->pm_mask_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLED); 932 ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); 933 ctx->zero = tcg_constant_tl(0); 934 } 935 936 static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) 937 { 938 } 939 940 static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) 941 { 942 DisasContext *ctx = container_of(dcbase, DisasContext, base); 943 944 tcg_gen_insn_start(ctx->base.pc_next); 945 } 946 947 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) 948 { 949 DisasContext *ctx = container_of(dcbase, DisasContext, base); 950 CPURISCVState *env = cpu->env_ptr; 951 uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); 952 953 ctx->ol = ctx->xl; 954 decode_opc(env, ctx, opcode16); 955 ctx->base.pc_next = ctx->pc_succ_insn; 956 957 for (int i = ctx->ntemp - 1; i >= 0; --i) { 958 tcg_temp_free(ctx->temp[i]); 959 ctx->temp[i] = NULL; 960 } 961 ctx->ntemp = 0; 962 963 if (ctx->base.is_jmp == DISAS_NEXT) { 964 target_ulong page_start; 965 966 page_start = ctx->base.pc_first & TARGET_PAGE_MASK; 967 if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { 968 ctx->base.is_jmp = DISAS_TOO_MANY; 969 } 970 } 971 } 972 973 static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) 974 { 975 DisasContext *ctx = container_of(dcbase, DisasContext, base); 976 977 switch (ctx->base.is_jmp) { 978 case DISAS_TOO_MANY: 979 gen_goto_tb(ctx, 0, ctx->base.pc_next); 980 break; 981 case DISAS_NORETURN: 982 break; 983 default: 984 g_assert_not_reached(); 985 } 986 } 987 988 static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) 989 { 990 #ifndef CONFIG_USER_ONLY 991 RISCVCPU *rvcpu = RISCV_CPU(cpu); 992 CPURISCVState *env = &rvcpu->env; 993 #endif 994 995 qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); 996 #ifndef CONFIG_USER_ONLY 997 qemu_log("Priv: "TARGET_FMT_ld"; Virt: "TARGET_FMT_ld"\n", env->priv, env->virt); 998 #endif 999 log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); 1000 } 1001 1002 static const TranslatorOps riscv_tr_ops = { 1003 .init_disas_context = riscv_tr_init_disas_context, 1004 .tb_start = riscv_tr_tb_start, 1005 .insn_start = riscv_tr_insn_start, 1006 .translate_insn = riscv_tr_translate_insn, 1007 .tb_stop = riscv_tr_tb_stop, 1008 .disas_log = riscv_tr_disas_log, 1009 }; 1010 1011 void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) 1012 { 1013 DisasContext ctx; 1014 1015 translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns); 1016 } 1017 1018 void riscv_translate_init(void) 1019 { 1020 int i; 1021 1022 /* 1023 * cpu_gpr[0] is a placeholder for the zero register. Do not use it. 1024 * Use the gen_set_gpr and get_gpr helper functions when accessing regs, 1025 * unless you specifically block reads/writes to reg 0. 1026 */ 1027 cpu_gpr[0] = NULL; 1028 cpu_gprh[0] = NULL; 1029 1030 for (i = 1; i < 32; i++) { 1031 cpu_gpr[i] = tcg_global_mem_new(cpu_env, 1032 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); 1033 cpu_gprh[i] = tcg_global_mem_new(cpu_env, 1034 offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]); 1035 } 1036 1037 for (i = 0; i < 32; i++) { 1038 cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, 1039 offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); 1040 } 1041 1042 cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, pc), "pc"); 1043 cpu_vl = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vl), "vl"); 1044 cpu_vstart = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, vstart), 1045 "vstart"); 1046 load_res = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_res), 1047 "load_res"); 1048 load_val = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, load_val), 1049 "load_val"); 1050 /* Assign PM CSRs to tcg globals */ 1051 pm_mask = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmmask), 1052 "pmmask"); 1053 pm_base = tcg_global_mem_new(cpu_env, offsetof(CPURISCVState, cur_pmbase), 1054 "pmbase"); 1055 } 1056